From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 27 Mar 2018 15:22:31 +0000 (+0100)
Subject: arch-arm: Fix secure write of SCTLR when EL3 is AArch64
X-Git-Tag: v19.0.0.0~2180
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=96bba0c50cda359b23365e3cb3a3f295796b06e4;p=gem5.git

arch-arm: Fix secure write of SCTLR when EL3 is AArch64

MiscRegisters are not banked between secure and non-secure mode if EL3
is not implemented or if EL3 is using AArch64 (highestELIs64).  In this
scenario a unique register is used and it is mapped to the NS version
(see snsBankedIndex implementation), so that a secure world read/write
should access the non secure storage.

Change-Id: Ica4182e3cdf4021d2bd1db23e477ce2bbf055926
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9502
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index d0dccdd3e..899cda9b5 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -952,8 +952,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
             {
                 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
                 scr = readMiscRegNoEffect(MISCREG_SCR);
-                MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
-                                         ? MISCREG_SCTLR_S : MISCREG_SCTLR_NS;
+
+                MiscRegIndex sctlr_idx;
+                if (haveSecurity && !highestELIs64 && !scr.ns) {
+                    sctlr_idx = MISCREG_SCTLR_S;
+                } else {
+                    sctlr_idx =  MISCREG_SCTLR_NS;
+                }
+
                 SCTLR sctlr = miscRegs[sctlr_idx];
                 SCTLR new_sctlr = newVal;
                 new_sctlr.nmfi =  ((bool)sctlr.nmfi) && !haveVirtualization;