From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 29 Apr 2015 05:44:57 +0000 (+0200)
Subject: Preserve important attributes in splitnets
X-Git-Tag: yosys-0.6~299
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=96be31de89bfcfb64d195dbdc0891bd507aec399;p=yosys.git

Preserve important attributes in splitnets
---

diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index d4e721a5d..d22d65000 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -54,6 +54,19 @@ struct SplitnetsWorker
 		new_wire->port_input = wire->port_input;
 		new_wire->port_output = wire->port_output;
 
+		if (wire->attributes.count("\\src"))
+			new_wire->attributes["\\src"] = wire->attributes.at("\\src");
+
+		if (wire->attributes.count("\\keep"))
+			new_wire->attributes["\\keep"] = wire->attributes.at("\\keep");
+
+		if (wire->attributes.count("\\init")) {
+			Const old_init = wire->attributes.at("\\init"), new_init;
+			for (int i = offset; i < offset+width; i++)
+				new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
+			new_wire->attributes["\\init"] = new_init;
+		}
+
 		std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
 		splitmap[wire].insert(splitmap[wire].end(), sigvec.begin(), sigvec.end());
 	}