From: Florent Kermarrec Date: Fri, 11 Oct 2019 19:55:26 +0000 (+0200) Subject: integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo) X-Git-Tag: 24jan2021_ls180~913 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=96c369f3e443976c8a008e763741e29321c19fc0;p=litex.git integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo) --- diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index eecfb54a..e4a23429 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -182,15 +182,12 @@ class SoCCore(Module): self.cpu.set_reset_address(self.soc_mem_map["rom"] if integrated_rom_size else cpu_reset_address) self.config["CPU_RESET_ADDR"] = self.cpu.reset_address - # Add CPU buses as Wisbone masters - for bus in self.cpu.buses: - assert bus.data_width in [32, 64, 128] - # Down Convert CPU buses to 32-bit if needed - if bus.data_width != 32: - dc_bus = wishbone.Interface() - self.submodules += wishbone.Converter(bus, dc_bus) - bus = dc_bus - self.add_wb_master(bus) + # Add CPU buses as 32-bit Wishbone masters + for cpu_bus in self.cpu.buses: + assert cpu_bus.data_width in [32, 64, 128] + soc_bus = wishbone.Interface(data_width=32) + self.submodules += wishbone.Converter(cpu_bus, soc_bus) + self.add_wb_master(soc_bus) # Add CPU CSR (dynamic) self.add_csr("cpu", allow_user_defined=True)