From: klehman <klehman9@comcast.net>
Date: Wed, 15 Sep 2021 19:13:12 +0000 (-0400)
Subject: expected class WIP
X-Git-Tag: DRAFT_SVP64_0_1~19
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=96d9e1f949c6b6d0a9a9cee75075cf0361853d67;p=openpower-isa.git

expected class WIP
---

diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py
index 701c69f7..87338aa2 100644
--- a/src/openpower/test/state.py
+++ b/src/openpower/test/state.py
@@ -111,8 +111,47 @@ class SimState(State):
         log("class sim pc", hex(self.pc))
 
 
+class ExpectedState(State):
+    def __init__(self):
+        pass
+
+    def get_intregs(self):
+        if False:
+            yield
+        self.intregs = []
+        for i in range(32):
+            self.intregs.append(0)
+        log("class expected int regs", list(map(hex, self.intregs)))
+
+    def get_crregs(self):
+        if False:
+            yield
+        self.crregs = []
+        for i in range(8):
+            self.crregs.append(0)
+        log("class expected cr regs", list(map(hex, self.crregs)))
+
+    def get_xregs(self):
+        if False:
+            yield
+        self.xregs = []
+        self.so = 0
+        self.ov = 0
+        self.ca = 0
+        self.xregs.extend((self.so, self.ov, self.ca))
+        log("class expected xregs", list(map(hex, self.xregs)))
+
+    def get_pc(self):
+        if False:
+            yield
+        self.pcl = []
+        self.pc = 0
+        self.pcl.append(self.pc)
+        log("class expected pc", hex(self.pc))
+
+
 global state_factory
-state_factory = {'sim': SimState}
+state_factory = {'sim': SimState, 'expected': ExpectedState}
 
 
 def state_add(name, kls):