From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 4 Jun 2020 17:48:46 +0000 (+0100)
Subject: comment clarify on core
X-Git-Tag: div_pipeline~590
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=96ddc2959d8ce96bf88cd53d7f9353add52fdedf;p=soc.git

comment clarify on core
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 68357ac2..da844e34 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -146,11 +146,11 @@ class TestRunner(FHDLTestCase):
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
-                # set up INT regfile, "direct" write from sim data
+                # set up INT regfile, "direct" write (bypass rd/write ports)
                 for i in range(32):
                     yield core.regs.int.regs[i].reg.eq(test.regs[i])
 
-                # set up XER
+                # set up XER.  "direct" write (bypass rd/write ports)
                 xregs = core.regs.xer
                 print ("sprs", test.sprs)
                 if special_sprs['XER'] in test.sprs: