From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 15 Aug 2019 19:30:46 +0000 (-0700)
Subject: Simplify
X-Git-Tag: working-ls180~1039^2~233
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=96ee7b9cf7a6a9010bc820dc110bf945c35cb32e;p=yosys.git

Simplify
---

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 11064e072..b387ca0a2 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -92,16 +92,12 @@ match ffFJKG
 endmatch
 
 code sigH sigO clock clock_pol
-	sigO = sigH;
-
 	if (ffFJKG) {
 		sigH = port(ffFJKG, \Q);
 		for (auto b : sigH)
 			if (b.wire->get_bool_attribute(\keep))
 				reject;
 
-		sigO = sigH;
-
 		SigBit c = port(ffFJKG, \CLK).as_bit();
 		bool cp = param(ffFJKG, \CLK_POLARITY).as_bool();
 
@@ -111,6 +107,8 @@ code sigH sigO clock clock_pol
 		clock = c;
 		clock_pol = cp;
 	}
+
+	sigO = sigH;
 endcode
 
 match addA