From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 00:51:50 +0000 (-0700)
Subject: Typo
X-Git-Tag: working-ls180~881^2^2~221
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=96f00e9147967b587ee3b0118b944464b06da0b6;p=yosys.git

Typo
---

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 56b4fe7f9..dc5032d23 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -165,7 +165,7 @@ module RAM64X1D (
   \$__ABC_LUTMUX6 spo (.A(\$SPO ), .S({A0, A1, A2, A3, A4, A5}), .Y(SPO));
 endmodule
 
-module \$__ABC_RAM128X1D (
+module RAM128X1D (
   output       DPO, SPO,
   input        D,
   input        WCLK,