From: Sebastien Bourdeauducq Date: Tue, 19 Nov 2013 22:48:00 +0000 (+0100) Subject: Revert "framebuffer: reset VTG" X-Git-Tag: 24jan2021_ls180~2787 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=96fcb3574e00d14a58d798c8d012f6d4dcacf53c;p=litex.git Revert "framebuffer: reset VTG" This reverts commit 6cb18f5ce3c9c63250cfbe738b84ec7beb1a9412. Conflicts: misoclib/framebuffer/__init__.py misoclib/framebuffer/format.py --- diff --git a/misoclib/framebuffer/__init__.py b/misoclib/framebuffer/__init__.py index 360a245f..7033ed0d 100644 --- a/misoclib/framebuffer/__init__.py +++ b/misoclib/framebuffer/__init__.py @@ -29,7 +29,6 @@ class Framebuffer(Module, AutoCSR): self.comb += [ self.fi.trigger.eq(self._enable.storage), self.dma.generator.trigger.eq(self._enable.storage), - vtg.enable.eq(self._enable.storage) ] class Blender(PipelinedActor, AutoCSR): @@ -99,7 +98,6 @@ class MixFramebuffer(Module, AutoCSR): setattr(self, "dma"+str(n), dma) vtg = VTG(pack_factor) - self.comb += vtg.enable.eq(self._enable.storage) g.add_connection(self.fi, vtg, sink_ep="timing") g.add_connection(self.blender, vtg, sink_ep="pixels") g.add_connection(vtg, self.driver) diff --git a/misoclib/framebuffer/format.py b/misoclib/framebuffer/format.py index 5a72a49d..25f3588d 100644 --- a/misoclib/framebuffer/format.py +++ b/misoclib/framebuffer/format.py @@ -49,7 +49,6 @@ class FrameInitiator(spi.SingleGenerator): class VTG(Module): def __init__(self, pack_factor): hbits_dyn = _hbits - log2_int(pack_factor) - self.enable = Signal() self.timing = Sink([ ("hres", hbits_dyn), ("hsync_start", hbits_dyn), @@ -63,8 +62,6 @@ class VTG(Module): self.phy = Source(phy_layout(pack_factor)) self.busy = Signal() - ### - hactive = Signal() vactive = Signal() active = Signal() @@ -83,39 +80,33 @@ class VTG(Module): ), generate_en.eq(self.timing.stb & (~active | self.pixels.stb)), - self.pixels.ack.eq(~self.enable | (self.phy.ack & active)), + self.pixels.ack.eq(self.phy.ack & active), self.phy.stb.eq(generate_en), self.busy.eq(generate_en) ] tp = self.timing.payload self.sync += [ - If(self.enable, - self.timing.ack.eq(0), - If(generate_en & self.phy.ack, - hcounter.eq(hcounter + 1), + self.timing.ack.eq(0), + If(generate_en & self.phy.ack, + hcounter.eq(hcounter + 1), + + If(hcounter == 0, hactive.eq(1)), + If(hcounter == tp.hres, hactive.eq(0)), + If(hcounter == tp.hsync_start, self.phy.payload.hsync.eq(1)), + If(hcounter == tp.hsync_end, self.phy.payload.hsync.eq(0)), + If(hcounter == tp.hscan, + hcounter.eq(0), + If(vcounter == tp.vscan, + vcounter.eq(0), + self.timing.ack.eq(1) + ).Else( + vcounter.eq(vcounter + 1) + ) + ), - If(hcounter == 0, hactive.eq(1)), - If(hcounter == tp.hres, hactive.eq(0)), - If(hcounter == tp.hsync_start, self.phy.payload.hsync.eq(1)), - If(hcounter == tp.hsync_end, self.phy.payload.hsync.eq(0)), - If(hcounter == tp.hscan, - hcounter.eq(0), - If(vcounter == tp.vscan, - vcounter.eq(0), - self.timing.ack.eq(1) - ).Else( - vcounter.eq(vcounter + 1) - ) - ), - - If(vcounter == 0, vactive.eq(1)), - If(vcounter == tp.vres, vactive.eq(0)), - If(vcounter == tp.vsync_start, self.phy.payload.vsync.eq(1)), - If(vcounter == tp.vsync_end, self.phy.payload.vsync.eq(0)) - ) - ).Else( - self.timing.ack.eq(1), - hcounter.eq(0), - vcounter.eq(0) + If(vcounter == 0, vactive.eq(1)), + If(vcounter == tp.vres, vactive.eq(0)), + If(vcounter == tp.vsync_start, self.phy.payload.vsync.eq(1)), + If(vcounter == tp.vsync_end, self.phy.payload.vsync.eq(0)) ) ]