From: Luke Kenneth Casson Leighton Date: Sat, 28 Mar 2020 14:26:09 +0000 (+0000) Subject: Re: [libre-riscv-dev] Clock Gating (was cache SRAM organisation) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=96fd049df0f48dbdcbafedc1eb7982a38c565aa3;p=libre-riscv-dev.git Re: [libre-riscv-dev] Clock Gating (was cache SRAM organisation) --- diff --git a/fb/bda7a0805eea2a732bf9da8705b49023fa273f b/fb/bda7a0805eea2a732bf9da8705b49023fa273f new file mode 100644 index 0000000..4aea2ab --- /dev/null +++ b/fb/bda7a0805eea2a732bf9da8705b49023fa273f @@ -0,0 +1,79 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Sat, 28 Mar 2020 14:26:45 +0000 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-riscv.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jICQ7-0004ub-CX; Sat, 28 Mar 2020 14:26:43 +0000 +Received: from lkcl.net ([217.147.94.29]) + by libre-riscv.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.89) (envelope-from ) id 1jICQ6-0004uV-I2 + for libre-riscv-dev@lists.libre-riscv.org; Sat, 28 Mar 2020 14:26:42 +0000 +DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lkcl.net; + s=201607131; + h=Content-Type:To:Subject:Message-ID:Date:From:In-Reply-To:References:MIME-Version; + bh=JSe+hEtKn9Tpzo3hRY03QxKWgOmPJcIWKGWXZgV2jqs=; + b=acXeuY/+WeHKZOshwPgRa5tCOj/biR8HH9HgVqT6x9CMJUV3AA8aFxlURjaj1wkwpvvkcQ+n1zJ/3nxsiSJEyX2DyA59eSGM4ElTyrUzv4h8y4kgA7Lai2Mml7/Cs5CR4aJy61cf26t1/nl5AHNcoe+bsStSGflhm0khHy9IFC4=; +Received: from mail-lj1-f174.google.com ([209.85.208.174]) + by lkcl.net with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) + (Exim 4.84_2) (envelope-from ) id 1jICQ6-0004N2-2x + for libre-riscv-dev@lists.libre-riscv.org; Sat, 28 Mar 2020 14:26:42 +0000 +Received: by mail-lj1-f174.google.com with SMTP id p10so12936286ljn.1 + for ; + Sat, 28 Mar 2020 07:26:26 -0700 (PDT) +X-Gm-Message-State: AGi0Puai323zdOfT9nzNQk4gdWEEwEP8Dv2944HVyV20zudtXg/LVVXv + ikI9UP/0/akYtUE8ddJGmoZqOl25eKe3NrkTeFA= +X-Google-Smtp-Source: APiQypLYJs3/dUpiwZYj/C2O+YHlAsUTE/vwNGIhELNaYHnGMnxrAb+7nadSV2ZkDcVORKsVZTSGS15+MKXr3m+Xdn8= +X-Received: by 2002:a2e:6c0a:: with SMTP id h10mr2231700ljc.195.1585405581136; + Sat, 28 Mar 2020 07:26:21 -0700 (PDT) +MIME-Version: 1.0 +References: + <29b1a9ecedda151dc9c8da6516c3691dfede62ef.camel@fibraservi.eu> + + <6fa40cb78b3f8c013ca4953ccb4daa5c23e3b501.camel@fibraservi.eu> + + + + + + <6fbfb2a3258be77f4fce69661b283dc31a683f7b.camel@fibraservi.eu> + + <9e44930a0332eff507661e617796b9d0674b0e05.camel@fibraservi.eu> + + <0d35e45bd81eeaecedeb64dc5061c1e33c89630c.camel@fibraservi.eu> +In-Reply-To: <0d35e45bd81eeaecedeb64dc5061c1e33c89630c.camel@fibraservi.eu> +From: Luke Kenneth Casson Leighton +Date: Sat, 28 Mar 2020 14:26:09 +0000 +X-Gmail-Original-Message-ID: +Message-ID: +To: Libre-RISCV General Development +Subject: Re: [libre-riscv-dev] Clock Gating (was cache SRAM organisation) +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: text/plain; charset="utf-8" +Content-Transfer-Encoding: base64 +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + +T24gU2F0LCBNYXIgMjgsIDIwMjAgYXQgMjowOCBQTSBTdGFmIFZlcmhhZWdlbiA8c3RhZkBmaWJy +YXNlcnZpLmV1PiB3cm90ZToKCj4gVGhlcmUgaXMgYW4gKElNTyBiZXR0ZXIpIGFsdGVybmF0aXZl +IGZvciB3aGF0IHlvdSBhcmUgZG9pbmcgd2l0aCB5b3VyIHBhc3MtdGhyb3VnaCByZWdpc3RlcnMg +YW5kIHRoYXQgaXMgY2xvY2sgZ2F0aW5nICh3aWtpcGVkaWEsIGFsbGFib3V0Y2lyY3VpdHMpLgoK +b2sgdGhhdCdzIHZlcnkgdmFsdWFibGUgYW5kIGFwcHJlY2lhdGVkLiAgd2lsbCByZXBseSBoZXJl +Cmh0dHA6Ly9idWdzLmxpYnJlLXJpc2N2Lm9yZy9zaG93X2J1Zy5jZ2k/aWQ9MjcwCgpfX19fX19f +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaWJyZS1yaXNjdi1kZXYg +bWFpbGluZyBsaXN0CmxpYnJlLXJpc2N2LWRldkBsaXN0cy5saWJyZS1yaXNjdi5vcmcKaHR0cDov +L2xpc3RzLmxpYnJlLXJpc2N2Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpYnJlLXJpc2N2LWRldgo= +