From: Dmitry Selyutin <dmitry.selyutin@3mdeb.com>
Date: Sun, 29 Aug 2021 18:16:26 +0000 (+0000)
Subject: fixedarith: switch divwX to XLEN
X-Git-Tag: xlen-bcd~49
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=970dc264166ef3ed184ae60fbe91d43d9c4d350e;p=openpower-isa.git

fixedarith: switch divwX to XLEN
---

diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn
index d6aca118..9dd7f1f4 100644
--- a/openpower/isa/fixedarith.mdwn
+++ b/openpower/isa/fixedarith.mdwn
@@ -388,16 +388,16 @@ XO-Form
 
 Pseudo-code:
 
-    dividend[0:31] <- (RA)[32:63]
-    divisor[0:31] <- (RB) [32:63]
-    if (((dividend = 0x8000_0000) &
-         (divisor = [1]*32)) |
-         (divisor = [0]*32)) then
-        RT[0:63] <- undefined([0]*64)
+    dividend[0:(XLEN/2)-1] <- (RA)[XLEN/2:XLEN-1]
+    divisor[0:(XLEN/2)-1] <- (RB) [XLEN/2:XLEN-1]
+    if (((dividend = (0b1 || ([0b0] * ((XLEN/2)-1)))) &
+         (divisor = [1]*XLEN/2)) |
+         (divisor = [0]*XLEN/2)) then
+        RT[0:XLEN-1] <- undefined([0]*XLEN)
         overflow <- 1
     else
-        RT[32:63] <- DIVS(dividend, divisor)
-        RT[0:31] <- undefined([0]*32)
+        RT[XLEN/2:XLEN-1] <- DIVS(dividend, divisor)
+        RT[0:(XLEN/2)-1] <- undefined([0]*XLEN/2)
         overflow <- 0
 
 Special Registers Altered: