From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 22 Apr 2021 14:05:37 +0000 (+0100)
Subject: error using sync, should have been comb
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=971164a56b993d7f5d8377c02d323316124e897a;p=soc.git

error using sync, should have been comb
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 7a7e9dd3..c3bc1f4f 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -600,29 +600,29 @@ class DCache(Elaboratable):
             sync += Display("request collision loadstore vs MMU")
 
         with m.If(m_in.valid):
-            sync += r.req.valid.eq(1)
-            sync += r.req.load.eq(~(m_in.tlbie | m_in.tlbld))
-            sync += r.req.dcbz.eq(0)
-            sync += r.req.nc.eq(0)
-            sync += r.req.reserve.eq(0)
-            sync += r.req.virt_mode.eq(0)
-            sync += r.req.priv_mode.eq(1)
-            sync += r.req.addr.eq(m_in.addr)
-            sync += r.req.data.eq(m_in.pte)
-            sync += r.req.byte_sel.eq(~0) # Const -1 sets all to 0b111....
-            sync += r.tlbie.eq(m_in.tlbie)
-            sync += r.doall.eq(m_in.doall)
-            sync += r.tlbld.eq(m_in.tlbld)
-            sync += r.mmu_req.eq(1)
+            comb += r.req.valid.eq(1)
+            comb += r.req.load.eq(~(m_in.tlbie | m_in.tlbld))
+            comb += r.req.dcbz.eq(0)
+            comb += r.req.nc.eq(0)
+            comb += r.req.reserve.eq(0)
+            comb += r.req.virt_mode.eq(0)
+            comb += r.req.priv_mode.eq(1)
+            comb += r.req.addr.eq(m_in.addr)
+            comb += r.req.data.eq(m_in.pte)
+            comb += r.req.byte_sel.eq(~0) # Const -1 sets all to 0b111....
+            comb += r.tlbie.eq(m_in.tlbie)
+            comb += r.doall.eq(m_in.doall)
+            comb += r.tlbld.eq(m_in.tlbld)
+            comb += r.mmu_req.eq(1)
         with m.Else():
-            sync += r.req.eq(d_in)
-            sync += r.tlbie.eq(0)
-            sync += r.doall.eq(0)
-            sync += r.tlbld.eq(0)
-            sync += r.mmu_req.eq(0)
-            with m.If(~(r1.full & r0_full)):
-                sync += r0.eq(r)
-                sync += r0_full.eq(r.req.valid)
+            comb += r.req.eq(d_in)
+            comb += r.tlbie.eq(0)
+            comb += r.doall.eq(0)
+            comb += r.tlbld.eq(0)
+            comb += r.mmu_req.eq(0)
+        with m.If(~(r1.full & r0_full)):
+            sync += r0.eq(r)
+            sync += r0_full.eq(r.req.valid)
 
     def tlb_read(self, m, r0_stall, tlb_valid_way,
                  tlb_tag_way, tlb_pte_way, dtlb_valid_bits,