From: Jason Ekstrand <jason.ekstrand@intel.com>
Date: Mon, 29 Feb 2016 22:13:56 +0000 (-0800)
Subject: anv/pipeline: Follow push constant alignment restrictions on BDW+ and HSW gt3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9715724015b49278fa3d110221ab39e1ed00c8c2;p=mesa.git

anv/pipeline: Follow push constant alignment restrictions on BDW+ and HSW gt3
---

diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index cbd3a21abd7..3dab205e5cc 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -894,9 +894,16 @@ gen7_compute_urb_partition(struct anv_pipeline *pipeline)
 
    const unsigned stages =
       _mesa_bitcount(pipeline->active_stages & VK_SHADER_STAGE_ALL_GRAPHICS);
-   const unsigned size_per_stage = stages ? (push_constant_kb / stages) : 0;
+   unsigned size_per_stage = stages ? (push_constant_kb / stages) : 0;
    unsigned used_kb = 0;
 
+   /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
+    * units of 2KB.  Incidentally, these are the same platforms that have
+    * 32KB worth of push constant space.
+    */
+   if (push_constant_kb == 32)
+      size_per_stage &= ~1u;
+
    for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_FRAGMENT; i++) {
       pipeline->urb.push_size[i] =
          (pipeline->active_stages & (1 << i)) ? size_per_stage : 0;