From: Luke Kenneth Casson Leighton Date: Thu, 2 Jul 2020 18:32:38 +0000 (+0000) Subject: add div pipeline X-Git-Tag: partial-core-ls180-gdsii~110 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=971e077f2e7241f7bec3e0e543bad105a64ba683;p=soclayout.git add div pipeline --- diff --git a/experiments9/cells.lst b/experiments9/cells.lst index 463027f..8d61f43 100644 --- a/experiments9/cells.lst +++ b/experiments9/cells.lst @@ -58,6 +58,7 @@ dec_sub4 dec_sub8 dec_sub9 dec +div0 fast fus idx_l diff --git a/experiments9/non_generated/test_issuer.il b/experiments9/non_generated/test_issuer.il index ea053fd..e083de0 100644 --- a/experiments9/non_generated/test_issuer.il +++ b/experiments9/non_generated/test_issuer.il @@ -65447,8 +65447,119368 @@ module \trap0 end end attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.p" +module \p$46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.n" +module \n$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_start.p" +module \p$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_start.n" +module \n$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_start.input" +module \input$50 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 input 24 \xer_ca + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 25 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 26 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 27 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 28 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 29 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 30 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 31 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 32 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 33 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 34 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 35 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 37 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 39 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 44 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 45 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 46 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 47 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 48 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24" + wire width 64 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $25 + end + process $group_0 + assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23" + switch { \op__invert_a } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23" + case 1'1 + assign \a $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:25" + case + assign \a \ra + end + sync init + end + process $group_1 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \a + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 \xer_ca$27 + process $group_2 + assign \xer_ca$27 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:36" + switch \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:37" + attribute \nmigen.decoding "ZERO/0" + case 2'00 + assign \xer_ca$27 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + attribute \nmigen.decoding "ONE/1" + case 2'01 + assign \xer_ca$27 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41" + attribute \nmigen.decoding "CA/2" + case 2'10 + assign \xer_ca$27 \xer_ca + end + sync init + end + process $group_3 + assign \xer_so$24 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47" + switch { \op__oe__oe_ok } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47" + case 1'1 + assign \xer_so$24 \xer_so + end + sync init + end + process $group_4 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_5 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_25 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_start.setup_stage" +module \setup_stage + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 24 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 25 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 26 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 27 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 28 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 29 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 30 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 31 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 32 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 33 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 34 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 35 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 36 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 38 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 43 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 44 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 45 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 46 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 47 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:101" + wire width 128 output 48 \dividend + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:102" + wire width 64 output 49 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:103" + wire width 2 output 50 \operation + wire width 1 $verilog_initial_trigger + process $group_0 + assign \operation 2'00 + assign \operation 2'01 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:48" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:48" + cell $mux $24 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \op__is_32bit + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:48" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:48" + cell $and $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $23 + connect \B \op__is_signed + connect \Y $25 + end + process $group_1 + assign \dividend_neg 1'0 + assign \dividend_neg $25 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:49" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:49" + cell $mux $28 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \op__is_32bit + connect \Y $27 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:49" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:49" + cell $and $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $27 + connect \B \op__is_signed + connect \Y $29 + end + process $group_2 + assign \divisor_neg 1'0 + assign \divisor_neg $29 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + wire width 64 \abs_dor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:56" + wire width 65 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:56" + wire width 65 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:56" + cell $neg $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $32 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 65 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $34 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:56" + wire width 65 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:56" + cell $mux $37 + parameter \WIDTH 65 + connect \A $34 + connect \B $32 + connect \S \divisor_neg + connect \Y $36 + end + connect $31 $36 + process $group_3 + assign \abs_dor 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \abs_dor $31 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:55" + wire width 64 \abs_dend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" + wire width 65 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" + wire width 65 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" + cell $neg $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $39 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 65 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + cell $pos $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" + wire width 65 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" + cell $mux $44 + parameter \WIDTH 65 + connect \A $41 + connect \B $39 + connect \S \dividend_neg + connect \Y $43 + end + connect $38 $43 + process $group_4 + assign \abs_dend 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \abs_dend $38 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:42" + wire width 1 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" + cell $ge $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \abs_dend + connect \B \abs_dor + connect \Y $45 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $eq $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \op__insn_type + connect \B 7'0011110 + connect \Y $47 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $and $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $45 + connect \B $47 + connect \Y $49 + end + process $group_5 + assign \dive_abs_ov64 1'0 + assign \dive_abs_ov64 $49 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:41" + wire width 1 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:63" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:63" + cell $ge $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \abs_dend [31:0] + connect \B \abs_dor [31:0] + connect \Y $51 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:64" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:64" + cell $eq $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \op__insn_type + connect \B 7'0011110 + connect \Y $53 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:64" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:64" + cell $and $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $51 + connect \B $53 + connect \Y $55 + end + process $group_6 + assign \dive_abs_ov32 1'0 + assign \dive_abs_ov32 $55 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:18" + wire width 32 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:18" + cell $mux $58 + parameter \WIDTH 32 + connect \A \abs_dor [63:32] + connect \B 32'00000000000000000000000000000000 + connect \S \op__is_32bit + connect \Y $57 + end + process $group_7 + assign \divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand [31:0] \abs_dor [31:0] + assign \divisor_radicand [63:32] $57 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:36" + wire width 1 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:70" + wire width 1 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:70" + cell $eq $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $59 + end + process $group_8 + assign \div_by_zero 1'0 + assign \div_by_zero $59 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:18" + wire width 32 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:18" + cell $mux $62 + parameter \WIDTH 32 + connect \A \abs_dend [63:32] + connect \B 32'00000000000000000000000000000000 + connect \S \op__is_32bit + connect \Y $61 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:82" + wire width 128 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:82" + wire width 95 $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:82" + cell $sshl $65 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 95 + connect \A \abs_dend [31:0] + connect \B 6'100000 + connect \Y $64 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:82" + cell $pos $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 95 + parameter \Y_WIDTH 128 + connect \A $64 + connect \Y $63 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:84" + wire width 191 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:84" + wire width 191 $68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:84" + cell $sshl $69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 + connect \A \abs_dend + connect \B 7'1000000 + connect \Y $68 + end + connect $67 $68 + process $group_9 + assign \dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:75" + switch \op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:77" + attribute \nmigen.decoding "OP_DIV/29|OP_MOD/47" + case 7'0011101, 7'0101111 + assign \dividend [31:0] \abs_dend [31:0] + assign \dividend [63:32] $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:80" + attribute \nmigen.decoding "OP_DIVE/30" + case 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" + switch { \op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" + case 1'1 + assign \dividend $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:83" + case + assign \dividend $67 [127:0] + end + end + sync init + end + process $group_10 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_11 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_12 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_start.core_setup_stage.core" +module \core$51 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:101" + wire width 128 input 0 \dividend + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:102" + wire width 64 input 1 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:103" + wire width 2 input 2 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 3 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 4 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 5 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 6 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 7 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 8 \compare_rhs + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + wire width 1 $verilog_initial_trigger + process $group_1 + assign \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + process $group_2 + assign \root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:241" + wire width 192 \lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:246" + wire width 255 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:246" + wire width 255 $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:246" + cell $sshl $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 255 + connect \A \dividend + connect \B 7'1000000 + connect \Y $4 + end + connect $3 $4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:248" + wire width 319 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:248" + wire width 319 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:248" + cell $sshl $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 319 + connect \A \divisor_radicand + connect \B 8'10000000 + connect \Y $7 + end + connect $6 $7 + process $group_3 + assign \lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:244" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:245" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \lhs $3 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:247" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \lhs $6 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:249" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + end + sync init + end + process $group_4 + assign \compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs \lhs + sync init + end + process $group_5 + assign \compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + end + process $group_6 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_start.core_setup_stage" +module \core_setup_stage + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:101" + wire width 128 input 26 \dividend + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:102" + wire width 64 input 27 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:103" + wire width 2 input 28 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 29 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 30 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 31 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 32 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 33 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 34 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 35 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 41 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 43 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 46 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 48 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 49 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 50 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 51 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 52 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 53 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 54 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 55 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 56 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 57 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 58 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 59 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 60 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:101" + wire width 128 \core_dividend + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:102" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:103" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + cell \core$51 \core + connect \dividend \core_dividend + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \divisor_radicand$1 \core_divisor_radicand$29 + connect \operation$2 \core_operation$30 + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_dividend \dividend + sync init + end + process $group_27 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_29 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$29 + sync init + end + process $group_30 + assign \operation$28 2'00 + assign \operation$28 \core_operation$30 + sync init + end + process $group_31 + assign \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root \core_quotient_root + sync init + end + process $group_32 + assign \root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand \core_root_times_radicand + sync init + end + process $group_33 + assign \compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs \core_compare_lhs + sync init + end + process $group_34 + assign \compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs \core_compare_rhs + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_start" +module \pipe_start + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 5 \op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 7 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 8 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 9 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 10 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 11 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 12 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 13 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 14 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 15 \op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 16 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 17 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 18 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 19 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 20 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 21 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 22 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 23 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 24 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 25 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 26 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 28 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 29 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 30 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 31 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 32 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 33 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 34 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 35 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 36 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 37 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 38 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 39 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 40 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 41 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 42 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 43 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 44 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 45 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 46 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 47 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 48 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 49 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 50 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 51 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 52 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 53 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 54 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 55 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 56 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 57 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 58 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 59 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 60 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 61 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 input 62 \xer_ca + cell \p$48 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$49 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \input_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \input_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \input_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \input_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \input_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \input_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \input_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \input_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \input_muxid$25 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \input_op__insn_type$26 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \input_op__fn_unit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \input_op__imm_data__imm$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__imm_data__imm_ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__lk$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__rc__rc$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__rc__rc_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__oe__oe$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__oe__oe_ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__invert_a$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__zero_a$36 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \input_op__input_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__invert_out$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \input_op__write_cr__data$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__write_cr__ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__output_carry$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__is_32bit$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \input_op__is_signed$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \input_op__data_len$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \input_op__insn$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \input_ra$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \input_rb$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \input_xer_so$48 + cell \input$50 \input + connect \muxid \input_muxid + connect \op__insn_type \input_op__insn_type + connect \op__fn_unit \input_op__fn_unit + connect \op__imm_data__imm \input_op__imm_data__imm + connect \op__imm_data__imm_ok \input_op__imm_data__imm_ok + connect \op__lk \input_op__lk + connect \op__rc__rc \input_op__rc__rc + connect \op__rc__rc_ok \input_op__rc__rc_ok + connect \op__oe__oe \input_op__oe__oe + connect \op__oe__oe_ok \input_op__oe__oe_ok + connect \op__invert_a \input_op__invert_a + connect \op__zero_a \input_op__zero_a + connect \op__input_carry \input_op__input_carry + connect \op__invert_out \input_op__invert_out + connect \op__write_cr__data \input_op__write_cr__data + connect \op__write_cr__ok \input_op__write_cr__ok + connect \op__output_carry \input_op__output_carry + connect \op__is_32bit \input_op__is_32bit + connect \op__is_signed \input_op__is_signed + connect \op__data_len \input_op__data_len + connect \op__insn \input_op__insn + connect \ra \input_ra + connect \rb \input_rb + connect \xer_so \input_xer_so + connect \xer_ca \input_xer_ca + connect \muxid$1 \input_muxid$25 + connect \op__insn_type$2 \input_op__insn_type$26 + connect \op__fn_unit$3 \input_op__fn_unit$27 + connect \op__imm_data__imm$4 \input_op__imm_data__imm$28 + connect \op__imm_data__imm_ok$5 \input_op__imm_data__imm_ok$29 + connect \op__lk$6 \input_op__lk$30 + connect \op__rc__rc$7 \input_op__rc__rc$31 + connect \op__rc__rc_ok$8 \input_op__rc__rc_ok$32 + connect \op__oe__oe$9 \input_op__oe__oe$33 + connect \op__oe__oe_ok$10 \input_op__oe__oe_ok$34 + connect \op__invert_a$11 \input_op__invert_a$35 + connect \op__zero_a$12 \input_op__zero_a$36 + connect \op__input_carry$13 \input_op__input_carry$37 + connect \op__invert_out$14 \input_op__invert_out$38 + connect \op__write_cr__data$15 \input_op__write_cr__data$39 + connect \op__write_cr__ok$16 \input_op__write_cr__ok$40 + connect \op__output_carry$17 \input_op__output_carry$41 + connect \op__is_32bit$18 \input_op__is_32bit$42 + connect \op__is_signed$19 \input_op__is_signed$43 + connect \op__data_len$20 \input_op__data_len$44 + connect \op__insn$21 \input_op__insn$45 + connect \ra$22 \input_ra$46 + connect \rb$23 \input_rb$47 + connect \xer_so$24 \input_xer_so$48 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \setup_stage_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \setup_stage_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \setup_stage_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \setup_stage_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \setup_stage_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \setup_stage_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \setup_stage_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \setup_stage_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \setup_stage_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \setup_stage_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \setup_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \setup_stage_muxid$49 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \setup_stage_op__insn_type$50 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \setup_stage_op__fn_unit$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \setup_stage_op__imm_data__imm$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__imm_data__imm_ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__lk$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__rc__rc$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__rc__rc_ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__oe__oe$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__oe__oe_ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__invert_a$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__zero_a$60 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \setup_stage_op__input_carry$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__invert_out$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \setup_stage_op__write_cr__data$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__write_cr__ok$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__is_32bit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \setup_stage_op__is_signed$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \setup_stage_op__data_len$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \setup_stage_op__insn$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \setup_stage_xer_so$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \setup_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \setup_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:101" + wire width 128 \setup_stage_dividend + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:102" + wire width 64 \setup_stage_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:103" + wire width 2 \setup_stage_operation + cell \setup_stage \setup_stage + connect \muxid \setup_stage_muxid + connect \op__insn_type \setup_stage_op__insn_type + connect \op__fn_unit \setup_stage_op__fn_unit + connect \op__imm_data__imm \setup_stage_op__imm_data__imm + connect \op__imm_data__imm_ok \setup_stage_op__imm_data__imm_ok + connect \op__lk \setup_stage_op__lk + connect \op__rc__rc \setup_stage_op__rc__rc + connect \op__rc__rc_ok \setup_stage_op__rc__rc_ok + connect \op__oe__oe \setup_stage_op__oe__oe + connect \op__oe__oe_ok \setup_stage_op__oe__oe_ok + connect \op__invert_a \setup_stage_op__invert_a + connect \op__zero_a \setup_stage_op__zero_a + connect \op__input_carry \setup_stage_op__input_carry + connect \op__invert_out \setup_stage_op__invert_out + connect \op__write_cr__data \setup_stage_op__write_cr__data + connect \op__write_cr__ok \setup_stage_op__write_cr__ok + connect \op__output_carry \setup_stage_op__output_carry + connect \op__is_32bit \setup_stage_op__is_32bit + connect \op__is_signed \setup_stage_op__is_signed + connect \op__data_len \setup_stage_op__data_len + connect \op__insn \setup_stage_op__insn + connect \ra \setup_stage_ra + connect \rb \setup_stage_rb + connect \xer_so \setup_stage_xer_so + connect \muxid$1 \setup_stage_muxid$49 + connect \op__insn_type$2 \setup_stage_op__insn_type$50 + connect \op__fn_unit$3 \setup_stage_op__fn_unit$51 + connect \op__imm_data__imm$4 \setup_stage_op__imm_data__imm$52 + connect \op__imm_data__imm_ok$5 \setup_stage_op__imm_data__imm_ok$53 + connect \op__lk$6 \setup_stage_op__lk$54 + connect \op__rc__rc$7 \setup_stage_op__rc__rc$55 + connect \op__rc__rc_ok$8 \setup_stage_op__rc__rc_ok$56 + connect \op__oe__oe$9 \setup_stage_op__oe__oe$57 + connect \op__oe__oe_ok$10 \setup_stage_op__oe__oe_ok$58 + connect \op__invert_a$11 \setup_stage_op__invert_a$59 + connect \op__zero_a$12 \setup_stage_op__zero_a$60 + connect \op__input_carry$13 \setup_stage_op__input_carry$61 + connect \op__invert_out$14 \setup_stage_op__invert_out$62 + connect \op__write_cr__data$15 \setup_stage_op__write_cr__data$63 + connect \op__write_cr__ok$16 \setup_stage_op__write_cr__ok$64 + connect \op__output_carry$17 \setup_stage_op__output_carry$65 + connect \op__is_32bit$18 \setup_stage_op__is_32bit$66 + connect \op__is_signed$19 \setup_stage_op__is_signed$67 + connect \op__data_len$20 \setup_stage_op__data_len$68 + connect \op__insn$21 \setup_stage_op__insn$69 + connect \xer_so$22 \setup_stage_xer_so$70 + connect \divisor_neg \setup_stage_divisor_neg + connect \dividend_neg \setup_stage_dividend_neg + connect \dividend \setup_stage_dividend + connect \divisor_radicand \setup_stage_divisor_radicand + connect \operation \setup_stage_operation + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_setup_stage_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_setup_stage_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_setup_stage_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_setup_stage_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_setup_stage_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_setup_stage_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_setup_stage_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_setup_stage_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_setup_stage_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_setup_stage_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_setup_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_setup_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_setup_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:101" + wire width 128 \core_setup_stage_dividend + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:102" + wire width 64 \core_setup_stage_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:103" + wire width 2 \core_setup_stage_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_setup_stage_muxid$71 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_setup_stage_op__insn_type$72 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_setup_stage_op__fn_unit$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_setup_stage_op__imm_data__imm$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__imm_data__imm_ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__lk$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__rc__rc$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__rc__rc_ok$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__oe__oe$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__oe__oe_ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__invert_a$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__zero_a$82 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_setup_stage_op__input_carry$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__invert_out$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_setup_stage_op__write_cr__data$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__write_cr__ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__output_carry$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__is_32bit$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_setup_stage_op__is_signed$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_setup_stage_op__data_len$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_setup_stage_op__insn$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_setup_stage_ra$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_setup_stage_rb$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_setup_stage_xer_so$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_setup_stage_divisor_neg$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_setup_stage_dividend_neg$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_setup_stage_divisor_radicand$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_setup_stage_operation$98 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_setup_stage_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_setup_stage_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_setup_stage_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_setup_stage_compare_rhs + cell \core_setup_stage \core_setup_stage + connect \muxid \core_setup_stage_muxid + connect \op__insn_type \core_setup_stage_op__insn_type + connect \op__fn_unit \core_setup_stage_op__fn_unit + connect \op__imm_data__imm \core_setup_stage_op__imm_data__imm + connect \op__imm_data__imm_ok \core_setup_stage_op__imm_data__imm_ok + connect \op__lk \core_setup_stage_op__lk + connect \op__rc__rc \core_setup_stage_op__rc__rc + connect \op__rc__rc_ok \core_setup_stage_op__rc__rc_ok + connect \op__oe__oe \core_setup_stage_op__oe__oe + connect \op__oe__oe_ok \core_setup_stage_op__oe__oe_ok + connect \op__invert_a \core_setup_stage_op__invert_a + connect \op__zero_a \core_setup_stage_op__zero_a + connect \op__input_carry \core_setup_stage_op__input_carry + connect \op__invert_out \core_setup_stage_op__invert_out + connect \op__write_cr__data \core_setup_stage_op__write_cr__data + connect \op__write_cr__ok \core_setup_stage_op__write_cr__ok + connect \op__output_carry \core_setup_stage_op__output_carry + connect \op__is_32bit \core_setup_stage_op__is_32bit + connect \op__is_signed \core_setup_stage_op__is_signed + connect \op__data_len \core_setup_stage_op__data_len + connect \op__insn \core_setup_stage_op__insn + connect \ra \core_setup_stage_ra + connect \rb \core_setup_stage_rb + connect \xer_so \core_setup_stage_xer_so + connect \divisor_neg \core_setup_stage_divisor_neg + connect \dividend_neg \core_setup_stage_dividend_neg + connect \dividend \core_setup_stage_dividend + connect \divisor_radicand \core_setup_stage_divisor_radicand + connect \operation \core_setup_stage_operation + connect \muxid$1 \core_setup_stage_muxid$71 + connect \op__insn_type$2 \core_setup_stage_op__insn_type$72 + connect \op__fn_unit$3 \core_setup_stage_op__fn_unit$73 + connect \op__imm_data__imm$4 \core_setup_stage_op__imm_data__imm$74 + connect \op__imm_data__imm_ok$5 \core_setup_stage_op__imm_data__imm_ok$75 + connect \op__lk$6 \core_setup_stage_op__lk$76 + connect \op__rc__rc$7 \core_setup_stage_op__rc__rc$77 + connect \op__rc__rc_ok$8 \core_setup_stage_op__rc__rc_ok$78 + connect \op__oe__oe$9 \core_setup_stage_op__oe__oe$79 + connect \op__oe__oe_ok$10 \core_setup_stage_op__oe__oe_ok$80 + connect \op__invert_a$11 \core_setup_stage_op__invert_a$81 + connect \op__zero_a$12 \core_setup_stage_op__zero_a$82 + connect \op__input_carry$13 \core_setup_stage_op__input_carry$83 + connect \op__invert_out$14 \core_setup_stage_op__invert_out$84 + connect \op__write_cr__data$15 \core_setup_stage_op__write_cr__data$85 + connect \op__write_cr__ok$16 \core_setup_stage_op__write_cr__ok$86 + connect \op__output_carry$17 \core_setup_stage_op__output_carry$87 + connect \op__is_32bit$18 \core_setup_stage_op__is_32bit$88 + connect \op__is_signed$19 \core_setup_stage_op__is_signed$89 + connect \op__data_len$20 \core_setup_stage_op__data_len$90 + connect \op__insn$21 \core_setup_stage_op__insn$91 + connect \ra$22 \core_setup_stage_ra$92 + connect \rb$23 \core_setup_stage_rb$93 + connect \xer_so$24 \core_setup_stage_xer_so$94 + connect \divisor_neg$25 \core_setup_stage_divisor_neg$95 + connect \dividend_neg$26 \core_setup_stage_dividend_neg$96 + connect \divisor_radicand$27 \core_setup_stage_divisor_radicand$97 + connect \operation$28 \core_setup_stage_operation$98 + connect \quotient_root \core_setup_stage_quotient_root + connect \root_times_radicand \core_setup_stage_root_times_radicand + connect \compare_lhs \core_setup_stage_compare_lhs + connect \compare_rhs \core_setup_stage_compare_rhs + end + process $group_0 + assign \input_muxid 2'00 + assign \input_muxid \muxid$1 + sync init + end + process $group_1 + assign \input_op__insn_type 7'0000000 + assign \input_op__fn_unit 10'0000000000 + assign \input_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_op__imm_data__imm_ok 1'0 + assign \input_op__lk 1'0 + assign \input_op__rc__rc 1'0 + assign \input_op__rc__rc_ok 1'0 + assign \input_op__oe__oe 1'0 + assign \input_op__oe__oe_ok 1'0 + assign \input_op__invert_a 1'0 + assign \input_op__zero_a 1'0 + assign \input_op__input_carry 2'00 + assign \input_op__invert_out 1'0 + assign \input_op__write_cr__data 3'000 + assign \input_op__write_cr__ok 1'0 + assign \input_op__output_carry 1'0 + assign \input_op__is_32bit 1'0 + assign \input_op__is_signed 1'0 + assign \input_op__data_len 4'0000 + assign \input_op__insn 32'00000000000000000000000000000000 + assign { \input_op__insn \input_op__data_len \input_op__is_signed \input_op__is_32bit \input_op__output_carry { \input_op__write_cr__ok \input_op__write_cr__data } \input_op__invert_out \input_op__input_carry \input_op__zero_a \input_op__invert_a { \input_op__oe__oe_ok \input_op__oe__oe } { \input_op__rc__rc_ok \input_op__rc__rc } \input_op__lk { \input_op__imm_data__imm_ok \input_op__imm_data__imm } \input_op__fn_unit \input_op__insn_type } { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } + sync init + end + process $group_21 + assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_ra \ra$22 + sync init + end + process $group_22 + assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \input_rb \rb$23 + sync init + end + process $group_23 + assign \input_xer_so 1'0 + assign \input_xer_so \xer_so$24 + sync init + end + process $group_24 + assign \input_xer_ca 2'00 + assign \input_xer_ca \xer_ca + sync init + end + process $group_25 + assign \setup_stage_muxid 2'00 + assign \setup_stage_muxid \input_muxid$25 + sync init + end + process $group_26 + assign \setup_stage_op__insn_type 7'0000000 + assign \setup_stage_op__fn_unit 10'0000000000 + assign \setup_stage_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \setup_stage_op__imm_data__imm_ok 1'0 + assign \setup_stage_op__lk 1'0 + assign \setup_stage_op__rc__rc 1'0 + assign \setup_stage_op__rc__rc_ok 1'0 + assign \setup_stage_op__oe__oe 1'0 + assign \setup_stage_op__oe__oe_ok 1'0 + assign \setup_stage_op__invert_a 1'0 + assign \setup_stage_op__zero_a 1'0 + assign \setup_stage_op__input_carry 2'00 + assign \setup_stage_op__invert_out 1'0 + assign \setup_stage_op__write_cr__data 3'000 + assign \setup_stage_op__write_cr__ok 1'0 + assign \setup_stage_op__output_carry 1'0 + assign \setup_stage_op__is_32bit 1'0 + assign \setup_stage_op__is_signed 1'0 + assign \setup_stage_op__data_len 4'0000 + assign \setup_stage_op__insn 32'00000000000000000000000000000000 + assign { \setup_stage_op__insn \setup_stage_op__data_len \setup_stage_op__is_signed \setup_stage_op__is_32bit \setup_stage_op__output_carry { \setup_stage_op__write_cr__ok \setup_stage_op__write_cr__data } \setup_stage_op__invert_out \setup_stage_op__input_carry \setup_stage_op__zero_a \setup_stage_op__invert_a { \setup_stage_op__oe__oe_ok \setup_stage_op__oe__oe } { \setup_stage_op__rc__rc_ok \setup_stage_op__rc__rc } \setup_stage_op__lk { \setup_stage_op__imm_data__imm_ok \setup_stage_op__imm_data__imm } \setup_stage_op__fn_unit \setup_stage_op__insn_type } { \input_op__insn$45 \input_op__data_len$44 \input_op__is_signed$43 \input_op__is_32bit$42 \input_op__output_carry$41 { \input_op__write_cr__ok$40 \input_op__write_cr__data$39 } \input_op__invert_out$38 \input_op__input_carry$37 \input_op__zero_a$36 \input_op__invert_a$35 { \input_op__oe__oe_ok$34 \input_op__oe__oe$33 } { \input_op__rc__rc_ok$32 \input_op__rc__rc$31 } \input_op__lk$30 { \input_op__imm_data__imm_ok$29 \input_op__imm_data__imm$28 } \input_op__fn_unit$27 \input_op__insn_type$26 } + sync init + end + process $group_46 + assign \setup_stage_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \setup_stage_ra \input_ra$46 + sync init + end + process $group_47 + assign \setup_stage_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \setup_stage_rb \input_rb$47 + sync init + end + process $group_48 + assign \setup_stage_xer_so 1'0 + assign \setup_stage_xer_so \input_xer_so$48 + sync init + end + process $group_49 + assign \core_setup_stage_muxid 2'00 + assign \core_setup_stage_muxid \setup_stage_muxid$49 + sync init + end + process $group_50 + assign \core_setup_stage_op__insn_type 7'0000000 + assign \core_setup_stage_op__fn_unit 10'0000000000 + assign \core_setup_stage_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_setup_stage_op__imm_data__imm_ok 1'0 + assign \core_setup_stage_op__lk 1'0 + assign \core_setup_stage_op__rc__rc 1'0 + assign \core_setup_stage_op__rc__rc_ok 1'0 + assign \core_setup_stage_op__oe__oe 1'0 + assign \core_setup_stage_op__oe__oe_ok 1'0 + assign \core_setup_stage_op__invert_a 1'0 + assign \core_setup_stage_op__zero_a 1'0 + assign \core_setup_stage_op__input_carry 2'00 + assign \core_setup_stage_op__invert_out 1'0 + assign \core_setup_stage_op__write_cr__data 3'000 + assign \core_setup_stage_op__write_cr__ok 1'0 + assign \core_setup_stage_op__output_carry 1'0 + assign \core_setup_stage_op__is_32bit 1'0 + assign \core_setup_stage_op__is_signed 1'0 + assign \core_setup_stage_op__data_len 4'0000 + assign \core_setup_stage_op__insn 32'00000000000000000000000000000000 + assign { \core_setup_stage_op__insn \core_setup_stage_op__data_len \core_setup_stage_op__is_signed \core_setup_stage_op__is_32bit \core_setup_stage_op__output_carry { \core_setup_stage_op__write_cr__ok \core_setup_stage_op__write_cr__data } \core_setup_stage_op__invert_out \core_setup_stage_op__input_carry \core_setup_stage_op__zero_a \core_setup_stage_op__invert_a { \core_setup_stage_op__oe__oe_ok \core_setup_stage_op__oe__oe } { \core_setup_stage_op__rc__rc_ok \core_setup_stage_op__rc__rc } \core_setup_stage_op__lk { \core_setup_stage_op__imm_data__imm_ok \core_setup_stage_op__imm_data__imm } \core_setup_stage_op__fn_unit \core_setup_stage_op__insn_type } { \setup_stage_op__insn$69 \setup_stage_op__data_len$68 \setup_stage_op__is_signed$67 \setup_stage_op__is_32bit$66 \setup_stage_op__output_carry$65 { \setup_stage_op__write_cr__ok$64 \setup_stage_op__write_cr__data$63 } \setup_stage_op__invert_out$62 \setup_stage_op__input_carry$61 \setup_stage_op__zero_a$60 \setup_stage_op__invert_a$59 { \setup_stage_op__oe__oe_ok$58 \setup_stage_op__oe__oe$57 } { \setup_stage_op__rc__rc_ok$56 \setup_stage_op__rc__rc$55 } \setup_stage_op__lk$54 { \setup_stage_op__imm_data__imm_ok$53 \setup_stage_op__imm_data__imm$52 } \setup_stage_op__fn_unit$51 \setup_stage_op__insn_type$50 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$99 + process $group_70 + assign \core_setup_stage_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_setup_stage_ra \ra$99 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$100 + process $group_71 + assign \core_setup_stage_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_setup_stage_rb \rb$100 + sync init + end + process $group_72 + assign \core_setup_stage_xer_so 1'0 + assign \core_setup_stage_xer_so \setup_stage_xer_so$70 + sync init + end + process $group_73 + assign \core_setup_stage_divisor_neg 1'0 + assign \core_setup_stage_divisor_neg \setup_stage_divisor_neg + sync init + end + process $group_74 + assign \core_setup_stage_dividend_neg 1'0 + assign \core_setup_stage_dividend_neg \setup_stage_dividend_neg + sync init + end + process $group_75 + assign \core_setup_stage_dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_setup_stage_dividend \setup_stage_dividend + sync init + end + process $group_76 + assign \core_setup_stage_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_setup_stage_divisor_radicand \setup_stage_divisor_radicand + sync init + end + process $group_77 + assign \core_setup_stage_operation 2'00 + assign \core_setup_stage_operation \setup_stage_operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$101 + process $group_78 + assign \p_valid_i$101 1'0 + assign \p_valid_i$101 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_79 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $102 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$101 + connect \B \p_ready_o + connect \Y $102 + end + process $group_80 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $102 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$104 + process $group_81 + assign \muxid$104 2'00 + assign \muxid$104 \core_setup_stage_muxid$71 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$105 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$115 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$124 + process $group_82 + assign \op__insn_type$105 7'0000000 + assign \op__fn_unit$106 10'0000000000 + assign \op__imm_data__imm$107 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$108 1'0 + assign \op__lk$109 1'0 + assign \op__rc__rc$110 1'0 + assign \op__rc__rc_ok$111 1'0 + assign \op__oe__oe$112 1'0 + assign \op__oe__oe_ok$113 1'0 + assign \op__invert_a$114 1'0 + assign \op__zero_a$115 1'0 + assign \op__input_carry$116 2'00 + assign \op__invert_out$117 1'0 + assign \op__write_cr__data$118 3'000 + assign \op__write_cr__ok$119 1'0 + assign \op__output_carry$120 1'0 + assign \op__is_32bit$121 1'0 + assign \op__is_signed$122 1'0 + assign \op__data_len$123 4'0000 + assign \op__insn$124 32'00000000000000000000000000000000 + assign { \op__insn$124 \op__data_len$123 \op__is_signed$122 \op__is_32bit$121 \op__output_carry$120 { \op__write_cr__ok$119 \op__write_cr__data$118 } \op__invert_out$117 \op__input_carry$116 \op__zero_a$115 \op__invert_a$114 { \op__oe__oe_ok$113 \op__oe__oe$112 } { \op__rc__rc_ok$111 \op__rc__rc$110 } \op__lk$109 { \op__imm_data__imm_ok$108 \op__imm_data__imm$107 } \op__fn_unit$106 \op__insn_type$105 } { \core_setup_stage_op__insn$91 \core_setup_stage_op__data_len$90 \core_setup_stage_op__is_signed$89 \core_setup_stage_op__is_32bit$88 \core_setup_stage_op__output_carry$87 { \core_setup_stage_op__write_cr__ok$86 \core_setup_stage_op__write_cr__data$85 } \core_setup_stage_op__invert_out$84 \core_setup_stage_op__input_carry$83 \core_setup_stage_op__zero_a$82 \core_setup_stage_op__invert_a$81 { \core_setup_stage_op__oe__oe_ok$80 \core_setup_stage_op__oe__oe$79 } { \core_setup_stage_op__rc__rc_ok$78 \core_setup_stage_op__rc__rc$77 } \core_setup_stage_op__lk$76 { \core_setup_stage_op__imm_data__imm_ok$75 \core_setup_stage_op__imm_data__imm$74 } \core_setup_stage_op__fn_unit$73 \core_setup_stage_op__insn_type$72 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$125 + process $group_102 + assign \ra$125 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$125 \core_setup_stage_ra$92 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$126 + process $group_103 + assign \rb$126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$126 \core_setup_stage_rb$93 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$127 + process $group_104 + assign \xer_so$127 1'0 + assign \xer_so$127 \core_setup_stage_xer_so$94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$128 + process $group_105 + assign \divisor_neg$128 1'0 + assign \divisor_neg$128 \core_setup_stage_divisor_neg$95 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$129 + process $group_106 + assign \dividend_neg$129 1'0 + assign \dividend_neg$129 \core_setup_stage_dividend_neg$96 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$130 + process $group_107 + assign \divisor_radicand$130 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$130 \core_setup_stage_divisor_radicand$97 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$131 + process $group_108 + assign \operation$131 2'00 + assign \operation$131 \core_setup_stage_operation$98 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$132 + process $group_109 + assign \quotient_root$132 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$132 \core_setup_stage_quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$133 + process $group_110 + assign \root_times_radicand$133 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$133 \core_setup_stage_root_times_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$134 + process $group_111 + assign \compare_lhs$134 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$134 \core_setup_stage_compare_lhs + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$135 + process $group_112 + assign \compare_rhs$135 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$135 \core_setup_stage_compare_rhs + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_113 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_114 + assign \muxid$next \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$next \muxid$104 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$next \muxid$104 + end + sync init + update \muxid 2'00 + sync posedge \clk + update \muxid \muxid$next + end + process $group_115 + assign \op__insn_type$next \op__insn_type + assign \op__fn_unit$next \op__fn_unit + assign \op__imm_data__imm$next \op__imm_data__imm + assign \op__imm_data__imm_ok$next \op__imm_data__imm_ok + assign \op__lk$next \op__lk + assign \op__rc__rc$next \op__rc__rc + assign \op__rc__rc_ok$next \op__rc__rc_ok + assign \op__oe__oe$next \op__oe__oe + assign \op__oe__oe_ok$next \op__oe__oe_ok + assign \op__invert_a$next \op__invert_a + assign \op__zero_a$next \op__zero_a + assign \op__input_carry$next \op__input_carry + assign \op__invert_out$next \op__invert_out + assign \op__write_cr__data$next \op__write_cr__data + assign \op__write_cr__ok$next \op__write_cr__ok + assign \op__output_carry$next \op__output_carry + assign \op__is_32bit$next \op__is_32bit + assign \op__is_signed$next \op__is_signed + assign \op__data_len$next \op__data_len + assign \op__insn$next \op__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__insn$next \op__data_len$next \op__is_signed$next \op__is_32bit$next \op__output_carry$next { \op__write_cr__ok$next \op__write_cr__data$next } \op__invert_out$next \op__input_carry$next \op__zero_a$next \op__invert_a$next { \op__oe__oe_ok$next \op__oe__oe$next } { \op__rc__rc_ok$next \op__rc__rc$next } \op__lk$next { \op__imm_data__imm_ok$next \op__imm_data__imm$next } \op__fn_unit$next \op__insn_type$next } { \op__insn$124 \op__data_len$123 \op__is_signed$122 \op__is_32bit$121 \op__output_carry$120 { \op__write_cr__ok$119 \op__write_cr__data$118 } \op__invert_out$117 \op__input_carry$116 \op__zero_a$115 \op__invert_a$114 { \op__oe__oe_ok$113 \op__oe__oe$112 } { \op__rc__rc_ok$111 \op__rc__rc$110 } \op__lk$109 { \op__imm_data__imm_ok$108 \op__imm_data__imm$107 } \op__fn_unit$106 \op__insn_type$105 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__insn$next \op__data_len$next \op__is_signed$next \op__is_32bit$next \op__output_carry$next { \op__write_cr__ok$next \op__write_cr__data$next } \op__invert_out$next \op__input_carry$next \op__zero_a$next \op__invert_a$next { \op__oe__oe_ok$next \op__oe__oe$next } { \op__rc__rc_ok$next \op__rc__rc$next } \op__lk$next { \op__imm_data__imm_ok$next \op__imm_data__imm$next } \op__fn_unit$next \op__insn_type$next } { \op__insn$124 \op__data_len$123 \op__is_signed$122 \op__is_32bit$121 \op__output_carry$120 { \op__write_cr__ok$119 \op__write_cr__data$118 } \op__invert_out$117 \op__input_carry$116 \op__zero_a$115 \op__invert_a$114 { \op__oe__oe_ok$113 \op__oe__oe$112 } { \op__rc__rc_ok$111 \op__rc__rc$110 } \op__lk$109 { \op__imm_data__imm_ok$108 \op__imm_data__imm$107 } \op__fn_unit$106 \op__insn_type$105 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$next 1'0 + assign \op__rc__rc$next 1'0 + assign \op__rc__rc_ok$next 1'0 + assign \op__oe__oe$next 1'0 + assign \op__oe__oe_ok$next 1'0 + assign \op__write_cr__data$next 3'000 + assign \op__write_cr__ok$next 1'0 + assign \op__insn$next 32'00000000000000000000000000000000 + end + sync init + update \op__insn_type 7'0000000 + update \op__fn_unit 10'0000000000 + update \op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \op__imm_data__imm_ok 1'0 + update \op__lk 1'0 + update \op__rc__rc 1'0 + update \op__rc__rc_ok 1'0 + update \op__oe__oe 1'0 + update \op__oe__oe_ok 1'0 + update \op__invert_a 1'0 + update \op__zero_a 1'0 + update \op__input_carry 2'00 + update \op__invert_out 1'0 + update \op__write_cr__data 3'000 + update \op__write_cr__ok 1'0 + update \op__output_carry 1'0 + update \op__is_32bit 1'0 + update \op__is_signed 1'0 + update \op__data_len 4'0000 + update \op__insn 32'00000000000000000000000000000000 + sync posedge \clk + update \op__insn_type \op__insn_type$next + update \op__fn_unit \op__fn_unit$next + update \op__imm_data__imm \op__imm_data__imm$next + update \op__imm_data__imm_ok \op__imm_data__imm_ok$next + update \op__lk \op__lk$next + update \op__rc__rc \op__rc__rc$next + update \op__rc__rc_ok \op__rc__rc_ok$next + update \op__oe__oe \op__oe__oe$next + update \op__oe__oe_ok \op__oe__oe_ok$next + update \op__invert_a \op__invert_a$next + update \op__zero_a \op__zero_a$next + update \op__input_carry \op__input_carry$next + update \op__invert_out \op__invert_out$next + update \op__write_cr__data \op__write_cr__data$next + update \op__write_cr__ok \op__write_cr__ok$next + update \op__output_carry \op__output_carry$next + update \op__is_32bit \op__is_32bit$next + update \op__is_signed \op__is_signed$next + update \op__data_len \op__data_len$next + update \op__insn \op__insn$next + end + process $group_135 + assign \ra$next \ra + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$next \ra$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$next \ra$125 + end + sync init + update \ra 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \ra \ra$next + end + process $group_136 + assign \rb$next \rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$next \rb$126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$next \rb$126 + end + sync init + update \rb 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \rb \rb$next + end + process $group_137 + assign \xer_so$next \xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$next \xer_so$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$next \xer_so$127 + end + sync init + update \xer_so 1'0 + sync posedge \clk + update \xer_so \xer_so$next + end + process $group_138 + assign \divisor_neg$next \divisor_neg + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$next \divisor_neg$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$next \divisor_neg$128 + end + sync init + update \divisor_neg 1'0 + sync posedge \clk + update \divisor_neg \divisor_neg$next + end + process $group_139 + assign \dividend_neg$next \dividend_neg + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$next \dividend_neg$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$next \dividend_neg$129 + end + sync init + update \dividend_neg 1'0 + sync posedge \clk + update \dividend_neg \dividend_neg$next + end + process $group_140 + assign \divisor_radicand$next \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$next \divisor_radicand$130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$next \divisor_radicand$130 + end + sync init + update \divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \divisor_radicand \divisor_radicand$next + end + process $group_141 + assign \operation$next \operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$next \operation$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$next \operation$131 + end + sync init + update \operation 2'00 + sync posedge \clk + update \operation \operation$next + end + process $group_142 + assign \quotient_root$next \quotient_root + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$next \quotient_root$132 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$next \quotient_root$132 + end + sync init + update \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \quotient_root \quotient_root$next + end + process $group_143 + assign \root_times_radicand$next \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$next \root_times_radicand$133 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$next \root_times_radicand$133 + end + sync init + update \root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \root_times_radicand \root_times_radicand$next + end + process $group_144 + assign \compare_lhs$next \compare_lhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$next \compare_lhs$134 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$next \compare_lhs$134 + end + sync init + update \compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_lhs \compare_lhs$next + end + process $group_145 + assign \compare_rhs$next \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$next \compare_rhs$135 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$next \compare_rhs$135 + end + sync init + update \compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_rhs \compare_rhs$next + end + process $group_146 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_147 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end + connect \ra$99 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \rb$100 64'0000000000000000000000000000000000000000000000000000000000000000 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.p" +module \p$52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.n" +module \n$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_0.core.trial0" +module \trial0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000000 + connect \B 8'10111010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1111010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_0.core.trial1" +module \trial1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000001 + connect \B 8'10111010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1111010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_0.core.trial2" +module \trial2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000100 + connect \B 8'10111010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1111010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_0.core.trial3" +module \trial3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'001001 + connect \B 8'10111010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1111010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_0.core.trial4" +module \trial4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'010000 + connect \B 8'10111010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1111010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_0.core.trial5" +module \trial5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'011001 + connect \B 8'10111010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1111010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_0.core.trial6" +module \trial6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'100100 + connect \B 8'10111010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1111010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_0.core.trial7" +module \trial7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'110001 + connect \B 8'10111010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1111010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_0.core.pe" +module \pe + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_0.core" +module \core$54 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 66 + connect \A \next_bits + connect \B 6'111101 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 66 + connect \A \quotient_root + connect \B $31 + connect \Y $33 + end + connect $30 $33 + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $30 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 130 $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 130 + connect \A $36 + connect \B 6'111101 + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 130 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B $38 + connect \Y $40 + end + connect $35 $40 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $35 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_0" +module \core_calculate_stage_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$54 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_1.core.trial0" +module \trial0$56 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000000 + connect \B 8'10110100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1110100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_1.core.trial1" +module \trial1$57 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000001 + connect \B 8'10110100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1110100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_1.core.trial2" +module \trial2$58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000100 + connect \B 8'10110100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1110100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_1.core.trial3" +module \trial3$59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'001001 + connect \B 8'10110100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1110100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_1.core.trial4" +module \trial4$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'010000 + connect \B 8'10110100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1110100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_1.core.trial5" +module \trial5$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'011001 + connect \B 8'10110100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1110100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_1.core.trial6" +module \trial6$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'100100 + connect \B 8'10110100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1110100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_1.core.trial7" +module \trial7$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1111010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'110001 + connect \B 8'10110100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1110100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_1.core.pe" +module \pe$64 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_1.core" +module \core$55 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$56 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$57 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$58 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$59 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$60 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$61 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$62 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$63 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$64 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 66 + connect \A \next_bits + connect \B 6'111010 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 66 + connect \A \quotient_root + connect \B $31 + connect \Y $33 + end + connect $30 $33 + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $30 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 130 $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 130 + connect \A $36 + connect \B 6'111010 + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 130 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B $38 + connect \Y $40 + end + connect $35 $40 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $35 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2.core_calculate_stage_1" +module \core_calculate_stage_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$55 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_0_to_2" +module \pipe_0_to_2 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 4 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 5 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 7 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 16 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 18 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 20 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 21 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 22 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 23 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 24 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 25 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 26 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 28 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 29 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 30 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 31 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 32 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 33 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 34 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 35 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 36 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 37 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 38 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$1$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 39 \op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 40 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 41 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 46 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 50 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 51 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 52 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 53 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 54 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 55 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 56 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 57 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 58 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 59 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 60 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 61 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 62 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 63 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$26$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 64 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 65 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 66 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 67 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 68 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 69 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$32$next + cell \p$52 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$53 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_0_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_0_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_0_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_0_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_0_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_0_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_0_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_0_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_0_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_0_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_0_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_0_muxid$33 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_0_op__insn_type$34 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_0_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_0_op__imm_data__imm$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__imm_data__imm_ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__lk$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__invert_a$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_0_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_0_op__write_cr__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__write_cr__ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__output_carry$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__is_32bit$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_0_op__is_signed$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_0_op__data_len$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_0_op__insn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_0_ra$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_0_rb$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_0_xer_so$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_0_divisor_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_0_dividend_neg$58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_0_divisor_radicand$59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_0_operation$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_0_quotient_root$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_0_root_times_radicand$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_0_compare_lhs$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_0_compare_rhs$64 + cell \core_calculate_stage_0 \core_calculate_stage_0 + connect \muxid \core_calculate_stage_0_muxid + connect \op__insn_type \core_calculate_stage_0_op__insn_type + connect \op__fn_unit \core_calculate_stage_0_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_0_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_0_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_0_op__lk + connect \op__rc__rc \core_calculate_stage_0_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_0_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_0_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_0_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_0_op__invert_a + connect \op__zero_a \core_calculate_stage_0_op__zero_a + connect \op__input_carry \core_calculate_stage_0_op__input_carry + connect \op__invert_out \core_calculate_stage_0_op__invert_out + connect \op__write_cr__data \core_calculate_stage_0_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_0_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_0_op__output_carry + connect \op__is_32bit \core_calculate_stage_0_op__is_32bit + connect \op__is_signed \core_calculate_stage_0_op__is_signed + connect \op__data_len \core_calculate_stage_0_op__data_len + connect \op__insn \core_calculate_stage_0_op__insn + connect \ra \core_calculate_stage_0_ra + connect \rb \core_calculate_stage_0_rb + connect \xer_so \core_calculate_stage_0_xer_so + connect \divisor_neg \core_calculate_stage_0_divisor_neg + connect \dividend_neg \core_calculate_stage_0_dividend_neg + connect \divisor_radicand \core_calculate_stage_0_divisor_radicand + connect \operation \core_calculate_stage_0_operation + connect \quotient_root \core_calculate_stage_0_quotient_root + connect \root_times_radicand \core_calculate_stage_0_root_times_radicand + connect \compare_lhs \core_calculate_stage_0_compare_lhs + connect \compare_rhs \core_calculate_stage_0_compare_rhs + connect \muxid$1 \core_calculate_stage_0_muxid$33 + connect \op__insn_type$2 \core_calculate_stage_0_op__insn_type$34 + connect \op__fn_unit$3 \core_calculate_stage_0_op__fn_unit$35 + connect \op__imm_data__imm$4 \core_calculate_stage_0_op__imm_data__imm$36 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_0_op__imm_data__imm_ok$37 + connect \op__lk$6 \core_calculate_stage_0_op__lk$38 + connect \op__rc__rc$7 \core_calculate_stage_0_op__rc__rc$39 + connect \op__rc__rc_ok$8 \core_calculate_stage_0_op__rc__rc_ok$40 + connect \op__oe__oe$9 \core_calculate_stage_0_op__oe__oe$41 + connect \op__oe__oe_ok$10 \core_calculate_stage_0_op__oe__oe_ok$42 + connect \op__invert_a$11 \core_calculate_stage_0_op__invert_a$43 + connect \op__zero_a$12 \core_calculate_stage_0_op__zero_a$44 + connect \op__input_carry$13 \core_calculate_stage_0_op__input_carry$45 + connect \op__invert_out$14 \core_calculate_stage_0_op__invert_out$46 + connect \op__write_cr__data$15 \core_calculate_stage_0_op__write_cr__data$47 + connect \op__write_cr__ok$16 \core_calculate_stage_0_op__write_cr__ok$48 + connect \op__output_carry$17 \core_calculate_stage_0_op__output_carry$49 + connect \op__is_32bit$18 \core_calculate_stage_0_op__is_32bit$50 + connect \op__is_signed$19 \core_calculate_stage_0_op__is_signed$51 + connect \op__data_len$20 \core_calculate_stage_0_op__data_len$52 + connect \op__insn$21 \core_calculate_stage_0_op__insn$53 + connect \ra$22 \core_calculate_stage_0_ra$54 + connect \rb$23 \core_calculate_stage_0_rb$55 + connect \xer_so$24 \core_calculate_stage_0_xer_so$56 + connect \divisor_neg$25 \core_calculate_stage_0_divisor_neg$57 + connect \dividend_neg$26 \core_calculate_stage_0_dividend_neg$58 + connect \divisor_radicand$27 \core_calculate_stage_0_divisor_radicand$59 + connect \operation$28 \core_calculate_stage_0_operation$60 + connect \quotient_root$29 \core_calculate_stage_0_quotient_root$61 + connect \root_times_radicand$30 \core_calculate_stage_0_root_times_radicand$62 + connect \compare_lhs$31 \core_calculate_stage_0_compare_lhs$63 + connect \compare_rhs$32 \core_calculate_stage_0_compare_rhs$64 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_1_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_1_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_1_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_1_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_1_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_1_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_1_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_1_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_1_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_1_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_1_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_1_muxid$65 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_1_op__insn_type$66 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_1_op__fn_unit$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_1_op__imm_data__imm$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__imm_data__imm_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__lk$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__rc__rc_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__oe__oe_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__invert_a$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__zero_a$76 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_1_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_1_op__write_cr__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__write_cr__ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_1_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_1_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_1_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_1_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_1_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_1_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_1_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_1_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_1_divisor_radicand$91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_1_operation$92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_1_quotient_root$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_1_root_times_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_1_compare_lhs$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_1_compare_rhs$96 + cell \core_calculate_stage_1 \core_calculate_stage_1 + connect \muxid \core_calculate_stage_1_muxid + connect \op__insn_type \core_calculate_stage_1_op__insn_type + connect \op__fn_unit \core_calculate_stage_1_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_1_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_1_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_1_op__lk + connect \op__rc__rc \core_calculate_stage_1_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_1_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_1_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_1_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_1_op__invert_a + connect \op__zero_a \core_calculate_stage_1_op__zero_a + connect \op__input_carry \core_calculate_stage_1_op__input_carry + connect \op__invert_out \core_calculate_stage_1_op__invert_out + connect \op__write_cr__data \core_calculate_stage_1_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_1_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_1_op__output_carry + connect \op__is_32bit \core_calculate_stage_1_op__is_32bit + connect \op__is_signed \core_calculate_stage_1_op__is_signed + connect \op__data_len \core_calculate_stage_1_op__data_len + connect \op__insn \core_calculate_stage_1_op__insn + connect \ra \core_calculate_stage_1_ra + connect \rb \core_calculate_stage_1_rb + connect \xer_so \core_calculate_stage_1_xer_so + connect \divisor_neg \core_calculate_stage_1_divisor_neg + connect \dividend_neg \core_calculate_stage_1_dividend_neg + connect \divisor_radicand \core_calculate_stage_1_divisor_radicand + connect \operation \core_calculate_stage_1_operation + connect \quotient_root \core_calculate_stage_1_quotient_root + connect \root_times_radicand \core_calculate_stage_1_root_times_radicand + connect \compare_lhs \core_calculate_stage_1_compare_lhs + connect \compare_rhs \core_calculate_stage_1_compare_rhs + connect \muxid$1 \core_calculate_stage_1_muxid$65 + connect \op__insn_type$2 \core_calculate_stage_1_op__insn_type$66 + connect \op__fn_unit$3 \core_calculate_stage_1_op__fn_unit$67 + connect \op__imm_data__imm$4 \core_calculate_stage_1_op__imm_data__imm$68 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_1_op__imm_data__imm_ok$69 + connect \op__lk$6 \core_calculate_stage_1_op__lk$70 + connect \op__rc__rc$7 \core_calculate_stage_1_op__rc__rc$71 + connect \op__rc__rc_ok$8 \core_calculate_stage_1_op__rc__rc_ok$72 + connect \op__oe__oe$9 \core_calculate_stage_1_op__oe__oe$73 + connect \op__oe__oe_ok$10 \core_calculate_stage_1_op__oe__oe_ok$74 + connect \op__invert_a$11 \core_calculate_stage_1_op__invert_a$75 + connect \op__zero_a$12 \core_calculate_stage_1_op__zero_a$76 + connect \op__input_carry$13 \core_calculate_stage_1_op__input_carry$77 + connect \op__invert_out$14 \core_calculate_stage_1_op__invert_out$78 + connect \op__write_cr__data$15 \core_calculate_stage_1_op__write_cr__data$79 + connect \op__write_cr__ok$16 \core_calculate_stage_1_op__write_cr__ok$80 + connect \op__output_carry$17 \core_calculate_stage_1_op__output_carry$81 + connect \op__is_32bit$18 \core_calculate_stage_1_op__is_32bit$82 + connect \op__is_signed$19 \core_calculate_stage_1_op__is_signed$83 + connect \op__data_len$20 \core_calculate_stage_1_op__data_len$84 + connect \op__insn$21 \core_calculate_stage_1_op__insn$85 + connect \ra$22 \core_calculate_stage_1_ra$86 + connect \rb$23 \core_calculate_stage_1_rb$87 + connect \xer_so$24 \core_calculate_stage_1_xer_so$88 + connect \divisor_neg$25 \core_calculate_stage_1_divisor_neg$89 + connect \dividend_neg$26 \core_calculate_stage_1_dividend_neg$90 + connect \divisor_radicand$27 \core_calculate_stage_1_divisor_radicand$91 + connect \operation$28 \core_calculate_stage_1_operation$92 + connect \quotient_root$29 \core_calculate_stage_1_quotient_root$93 + connect \root_times_radicand$30 \core_calculate_stage_1_root_times_radicand$94 + connect \compare_lhs$31 \core_calculate_stage_1_compare_lhs$95 + connect \compare_rhs$32 \core_calculate_stage_1_compare_rhs$96 + end + process $group_0 + assign \core_calculate_stage_0_muxid 2'00 + assign \core_calculate_stage_0_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_0_op__insn_type 7'0000000 + assign \core_calculate_stage_0_op__fn_unit 10'0000000000 + assign \core_calculate_stage_0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_0_op__lk 1'0 + assign \core_calculate_stage_0_op__rc__rc 1'0 + assign \core_calculate_stage_0_op__rc__rc_ok 1'0 + assign \core_calculate_stage_0_op__oe__oe 1'0 + assign \core_calculate_stage_0_op__oe__oe_ok 1'0 + assign \core_calculate_stage_0_op__invert_a 1'0 + assign \core_calculate_stage_0_op__zero_a 1'0 + assign \core_calculate_stage_0_op__input_carry 2'00 + assign \core_calculate_stage_0_op__invert_out 1'0 + assign \core_calculate_stage_0_op__write_cr__data 3'000 + assign \core_calculate_stage_0_op__write_cr__ok 1'0 + assign \core_calculate_stage_0_op__output_carry 1'0 + assign \core_calculate_stage_0_op__is_32bit 1'0 + assign \core_calculate_stage_0_op__is_signed 1'0 + assign \core_calculate_stage_0_op__data_len 4'0000 + assign \core_calculate_stage_0_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_0_op__insn \core_calculate_stage_0_op__data_len \core_calculate_stage_0_op__is_signed \core_calculate_stage_0_op__is_32bit \core_calculate_stage_0_op__output_carry { \core_calculate_stage_0_op__write_cr__ok \core_calculate_stage_0_op__write_cr__data } \core_calculate_stage_0_op__invert_out \core_calculate_stage_0_op__input_carry \core_calculate_stage_0_op__zero_a \core_calculate_stage_0_op__invert_a { \core_calculate_stage_0_op__oe__oe_ok \core_calculate_stage_0_op__oe__oe } { \core_calculate_stage_0_op__rc__rc_ok \core_calculate_stage_0_op__rc__rc } \core_calculate_stage_0_op__lk { \core_calculate_stage_0_op__imm_data__imm_ok \core_calculate_stage_0_op__imm_data__imm } \core_calculate_stage_0_op__fn_unit \core_calculate_stage_0_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \core_calculate_stage_0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_ra \ra + sync init + end + process $group_22 + assign \core_calculate_stage_0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_rb \rb + sync init + end + process $group_23 + assign \core_calculate_stage_0_xer_so 1'0 + assign \core_calculate_stage_0_xer_so \xer_so + sync init + end + process $group_24 + assign \core_calculate_stage_0_divisor_neg 1'0 + assign \core_calculate_stage_0_divisor_neg \divisor_neg + sync init + end + process $group_25 + assign \core_calculate_stage_0_dividend_neg 1'0 + assign \core_calculate_stage_0_dividend_neg \dividend_neg + sync init + end + process $group_26 + assign \core_calculate_stage_0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_calculate_stage_0_operation 2'00 + assign \core_calculate_stage_0_operation \operation + sync init + end + process $group_28 + assign \core_calculate_stage_0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_calculate_stage_0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_calculate_stage_0_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_calculate_stage_0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_0_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \core_calculate_stage_1_muxid 2'00 + assign \core_calculate_stage_1_muxid \core_calculate_stage_0_muxid$33 + sync init + end + process $group_33 + assign \core_calculate_stage_1_op__insn_type 7'0000000 + assign \core_calculate_stage_1_op__fn_unit 10'0000000000 + assign \core_calculate_stage_1_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_1_op__lk 1'0 + assign \core_calculate_stage_1_op__rc__rc 1'0 + assign \core_calculate_stage_1_op__rc__rc_ok 1'0 + assign \core_calculate_stage_1_op__oe__oe 1'0 + assign \core_calculate_stage_1_op__oe__oe_ok 1'0 + assign \core_calculate_stage_1_op__invert_a 1'0 + assign \core_calculate_stage_1_op__zero_a 1'0 + assign \core_calculate_stage_1_op__input_carry 2'00 + assign \core_calculate_stage_1_op__invert_out 1'0 + assign \core_calculate_stage_1_op__write_cr__data 3'000 + assign \core_calculate_stage_1_op__write_cr__ok 1'0 + assign \core_calculate_stage_1_op__output_carry 1'0 + assign \core_calculate_stage_1_op__is_32bit 1'0 + assign \core_calculate_stage_1_op__is_signed 1'0 + assign \core_calculate_stage_1_op__data_len 4'0000 + assign \core_calculate_stage_1_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_1_op__insn \core_calculate_stage_1_op__data_len \core_calculate_stage_1_op__is_signed \core_calculate_stage_1_op__is_32bit \core_calculate_stage_1_op__output_carry { \core_calculate_stage_1_op__write_cr__ok \core_calculate_stage_1_op__write_cr__data } \core_calculate_stage_1_op__invert_out \core_calculate_stage_1_op__input_carry \core_calculate_stage_1_op__zero_a \core_calculate_stage_1_op__invert_a { \core_calculate_stage_1_op__oe__oe_ok \core_calculate_stage_1_op__oe__oe } { \core_calculate_stage_1_op__rc__rc_ok \core_calculate_stage_1_op__rc__rc } \core_calculate_stage_1_op__lk { \core_calculate_stage_1_op__imm_data__imm_ok \core_calculate_stage_1_op__imm_data__imm } \core_calculate_stage_1_op__fn_unit \core_calculate_stage_1_op__insn_type } { \core_calculate_stage_0_op__insn$53 \core_calculate_stage_0_op__data_len$52 \core_calculate_stage_0_op__is_signed$51 \core_calculate_stage_0_op__is_32bit$50 \core_calculate_stage_0_op__output_carry$49 { \core_calculate_stage_0_op__write_cr__ok$48 \core_calculate_stage_0_op__write_cr__data$47 } \core_calculate_stage_0_op__invert_out$46 \core_calculate_stage_0_op__input_carry$45 \core_calculate_stage_0_op__zero_a$44 \core_calculate_stage_0_op__invert_a$43 { \core_calculate_stage_0_op__oe__oe_ok$42 \core_calculate_stage_0_op__oe__oe$41 } { \core_calculate_stage_0_op__rc__rc_ok$40 \core_calculate_stage_0_op__rc__rc$39 } \core_calculate_stage_0_op__lk$38 { \core_calculate_stage_0_op__imm_data__imm_ok$37 \core_calculate_stage_0_op__imm_data__imm$36 } \core_calculate_stage_0_op__fn_unit$35 \core_calculate_stage_0_op__insn_type$34 } + sync init + end + process $group_53 + assign \core_calculate_stage_1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_ra \core_calculate_stage_0_ra$54 + sync init + end + process $group_54 + assign \core_calculate_stage_1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_rb \core_calculate_stage_0_rb$55 + sync init + end + process $group_55 + assign \core_calculate_stage_1_xer_so 1'0 + assign \core_calculate_stage_1_xer_so \core_calculate_stage_0_xer_so$56 + sync init + end + process $group_56 + assign \core_calculate_stage_1_divisor_neg 1'0 + assign \core_calculate_stage_1_divisor_neg \core_calculate_stage_0_divisor_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_1_dividend_neg 1'0 + assign \core_calculate_stage_1_dividend_neg \core_calculate_stage_0_dividend_neg$58 + sync init + end + process $group_58 + assign \core_calculate_stage_1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_divisor_radicand \core_calculate_stage_0_divisor_radicand$59 + sync init + end + process $group_59 + assign \core_calculate_stage_1_operation 2'00 + assign \core_calculate_stage_1_operation \core_calculate_stage_0_operation$60 + sync init + end + process $group_60 + assign \core_calculate_stage_1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_quotient_root \core_calculate_stage_0_quotient_root$61 + sync init + end + process $group_61 + assign \core_calculate_stage_1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_root_times_radicand \core_calculate_stage_0_root_times_radicand$62 + sync init + end + process $group_62 + assign \core_calculate_stage_1_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_compare_lhs \core_calculate_stage_0_compare_lhs$63 + sync init + end + process $group_63 + assign \core_calculate_stage_1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_1_compare_rhs \core_calculate_stage_0_compare_rhs$64 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$97 + process $group_64 + assign \p_valid_i$97 1'0 + assign \p_valid_i$97 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_65 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $98 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$97 + connect \B \p_ready_o + connect \Y $98 + end + process $group_66 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $98 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$100 + process $group_67 + assign \muxid$100 2'00 + assign \muxid$100 \core_calculate_stage_1_muxid$65 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$111 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$120 + process $group_68 + assign \op__insn_type$101 7'0000000 + assign \op__fn_unit$102 10'0000000000 + assign \op__imm_data__imm$103 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$104 1'0 + assign \op__lk$105 1'0 + assign \op__rc__rc$106 1'0 + assign \op__rc__rc_ok$107 1'0 + assign \op__oe__oe$108 1'0 + assign \op__oe__oe_ok$109 1'0 + assign \op__invert_a$110 1'0 + assign \op__zero_a$111 1'0 + assign \op__input_carry$112 2'00 + assign \op__invert_out$113 1'0 + assign \op__write_cr__data$114 3'000 + assign \op__write_cr__ok$115 1'0 + assign \op__output_carry$116 1'0 + assign \op__is_32bit$117 1'0 + assign \op__is_signed$118 1'0 + assign \op__data_len$119 4'0000 + assign \op__insn$120 32'00000000000000000000000000000000 + assign { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } { \core_calculate_stage_1_op__insn$85 \core_calculate_stage_1_op__data_len$84 \core_calculate_stage_1_op__is_signed$83 \core_calculate_stage_1_op__is_32bit$82 \core_calculate_stage_1_op__output_carry$81 { \core_calculate_stage_1_op__write_cr__ok$80 \core_calculate_stage_1_op__write_cr__data$79 } \core_calculate_stage_1_op__invert_out$78 \core_calculate_stage_1_op__input_carry$77 \core_calculate_stage_1_op__zero_a$76 \core_calculate_stage_1_op__invert_a$75 { \core_calculate_stage_1_op__oe__oe_ok$74 \core_calculate_stage_1_op__oe__oe$73 } { \core_calculate_stage_1_op__rc__rc_ok$72 \core_calculate_stage_1_op__rc__rc$71 } \core_calculate_stage_1_op__lk$70 { \core_calculate_stage_1_op__imm_data__imm_ok$69 \core_calculate_stage_1_op__imm_data__imm$68 } \core_calculate_stage_1_op__fn_unit$67 \core_calculate_stage_1_op__insn_type$66 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$121 + process $group_88 + assign \ra$121 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$121 \core_calculate_stage_1_ra$86 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$122 + process $group_89 + assign \rb$122 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$122 \core_calculate_stage_1_rb$87 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$123 + process $group_90 + assign \xer_so$123 1'0 + assign \xer_so$123 \core_calculate_stage_1_xer_so$88 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$124 + process $group_91 + assign \divisor_neg$124 1'0 + assign \divisor_neg$124 \core_calculate_stage_1_divisor_neg$89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$125 + process $group_92 + assign \dividend_neg$125 1'0 + assign \dividend_neg$125 \core_calculate_stage_1_dividend_neg$90 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$126 + process $group_93 + assign \divisor_radicand$126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$126 \core_calculate_stage_1_divisor_radicand$91 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$127 + process $group_94 + assign \operation$127 2'00 + assign \operation$127 \core_calculate_stage_1_operation$92 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$128 + process $group_95 + assign \quotient_root$128 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$128 \core_calculate_stage_1_quotient_root$93 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$129 + process $group_96 + assign \root_times_radicand$129 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$129 \core_calculate_stage_1_root_times_radicand$94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$130 + process $group_97 + assign \compare_lhs$130 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$130 \core_calculate_stage_1_compare_lhs$95 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$131 + process $group_98 + assign \compare_rhs$131 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$131 \core_calculate_stage_1_compare_rhs$96 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_99 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_100 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$100 + end + sync init + update \muxid$1 2'00 + sync posedge \clk + update \muxid$1 \muxid$1$next + end + process $group_101 + assign \op__insn_type$2$next \op__insn_type$2 + assign \op__fn_unit$3$next \op__fn_unit$3 + assign \op__imm_data__imm$4$next \op__imm_data__imm$4 + assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5 + assign \op__lk$6$next \op__lk$6 + assign \op__rc__rc$7$next \op__rc__rc$7 + assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8 + assign \op__oe__oe$9$next \op__oe__oe$9 + assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10 + assign \op__invert_a$11$next \op__invert_a$11 + assign \op__zero_a$12$next \op__zero_a$12 + assign \op__input_carry$13$next \op__input_carry$13 + assign \op__invert_out$14$next \op__invert_out$14 + assign \op__write_cr__data$15$next \op__write_cr__data$15 + assign \op__write_cr__ok$16$next \op__write_cr__ok$16 + assign \op__output_carry$17$next \op__output_carry$17 + assign \op__is_32bit$18$next \op__is_32bit$18 + assign \op__is_signed$19$next \op__is_signed$19 + assign \op__data_len$20$next \op__data_len$20 + assign \op__insn$21$next \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5$next 1'0 + assign \op__rc__rc$7$next 1'0 + assign \op__rc__rc_ok$8$next 1'0 + assign \op__oe__oe$9$next 1'0 + assign \op__oe__oe_ok$10$next 1'0 + assign \op__write_cr__data$15$next 3'000 + assign \op__write_cr__ok$16$next 1'0 + assign \op__insn$21$next 32'00000000000000000000000000000000 + end + sync init + update \op__insn_type$2 7'0000000 + update \op__fn_unit$3 10'0000000000 + update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \op__imm_data__imm_ok$5 1'0 + update \op__lk$6 1'0 + update \op__rc__rc$7 1'0 + update \op__rc__rc_ok$8 1'0 + update \op__oe__oe$9 1'0 + update \op__oe__oe_ok$10 1'0 + update \op__invert_a$11 1'0 + update \op__zero_a$12 1'0 + update \op__input_carry$13 2'00 + update \op__invert_out$14 1'0 + update \op__write_cr__data$15 3'000 + update \op__write_cr__ok$16 1'0 + update \op__output_carry$17 1'0 + update \op__is_32bit$18 1'0 + update \op__is_signed$19 1'0 + update \op__data_len$20 4'0000 + update \op__insn$21 32'00000000000000000000000000000000 + sync posedge \clk + update \op__insn_type$2 \op__insn_type$2$next + update \op__fn_unit$3 \op__fn_unit$3$next + update \op__imm_data__imm$4 \op__imm_data__imm$4$next + update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next + update \op__lk$6 \op__lk$6$next + update \op__rc__rc$7 \op__rc__rc$7$next + update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next + update \op__oe__oe$9 \op__oe__oe$9$next + update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next + update \op__invert_a$11 \op__invert_a$11$next + update \op__zero_a$12 \op__zero_a$12$next + update \op__input_carry$13 \op__input_carry$13$next + update \op__invert_out$14 \op__invert_out$14$next + update \op__write_cr__data$15 \op__write_cr__data$15$next + update \op__write_cr__ok$16 \op__write_cr__ok$16$next + update \op__output_carry$17 \op__output_carry$17$next + update \op__is_32bit$18 \op__is_32bit$18$next + update \op__is_signed$19 \op__is_signed$19$next + update \op__data_len$20 \op__data_len$20$next + update \op__insn$21 \op__insn$21$next + end + process $group_121 + assign \ra$22$next \ra$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$22$next \ra$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$22$next \ra$121 + end + sync init + update \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \ra$22 \ra$22$next + end + process $group_122 + assign \rb$23$next \rb$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$23$next \rb$122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$23$next \rb$122 + end + sync init + update \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \rb$23 \rb$23$next + end + process $group_123 + assign \xer_so$24$next \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$24$next \xer_so$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$24$next \xer_so$123 + end + sync init + update \xer_so$24 1'0 + sync posedge \clk + update \xer_so$24 \xer_so$24$next + end + process $group_124 + assign \divisor_neg$25$next \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$25$next \divisor_neg$124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$25$next \divisor_neg$124 + end + sync init + update \divisor_neg$25 1'0 + sync posedge \clk + update \divisor_neg$25 \divisor_neg$25$next + end + process $group_125 + assign \dividend_neg$26$next \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$26$next \dividend_neg$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$26$next \dividend_neg$125 + end + sync init + update \dividend_neg$26 1'0 + sync posedge \clk + update \dividend_neg$26 \dividend_neg$26$next + end + process $group_126 + assign \divisor_radicand$27$next \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$27$next \divisor_radicand$126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$27$next \divisor_radicand$126 + end + sync init + update \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \divisor_radicand$27 \divisor_radicand$27$next + end + process $group_127 + assign \operation$28$next \operation$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$28$next \operation$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$28$next \operation$127 + end + sync init + update \operation$28 2'00 + sync posedge \clk + update \operation$28 \operation$28$next + end + process $group_128 + assign \quotient_root$29$next \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$29$next \quotient_root$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$29$next \quotient_root$128 + end + sync init + update \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \quotient_root$29 \quotient_root$29$next + end + process $group_129 + assign \root_times_radicand$30$next \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$30$next \root_times_radicand$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$30$next \root_times_radicand$129 + end + sync init + update \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \root_times_radicand$30 \root_times_radicand$30$next + end + process $group_130 + assign \compare_lhs$31$next \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$31$next \compare_lhs$130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$31$next \compare_lhs$130 + end + sync init + update \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_lhs$31 \compare_lhs$31$next + end + process $group_131 + assign \compare_rhs$32$next \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$32$next \compare_rhs$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$32$next \compare_rhs$131 + end + sync init + update \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_rhs$32 \compare_rhs$32$next + end + process $group_132 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_133 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.p" +module \p$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.n" +module \n$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_2.core.trial0" +module \trial0$68 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000000 + connect \B 8'10101110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_2.core.trial1" +module \trial1$69 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000001 + connect \B 8'10101110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_2.core.trial2" +module \trial2$70 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000100 + connect \B 8'10101110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_2.core.trial3" +module \trial3$71 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'001001 + connect \B 8'10101110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_2.core.trial4" +module \trial4$72 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'010000 + connect \B 8'10101110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_2.core.trial5" +module \trial5$73 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'011001 + connect \B 8'10101110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_2.core.trial6" +module \trial6$74 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'100100 + connect \B 8'10101110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_2.core.trial7" +module \trial7$75 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1111000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'110001 + connect \B 8'10101110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'111000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_2.core.pe" +module \pe$76 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_2.core" +module \core$67 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$68 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$69 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$70 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$71 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$72 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$73 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$74 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$75 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$76 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 66 + connect \A \next_bits + connect \B 6'110111 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 66 + connect \A \quotient_root + connect \B $31 + connect \Y $33 + end + connect $30 $33 + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $30 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 130 $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 130 + connect \A $36 + connect \B 6'110111 + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 130 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B $38 + connect \Y $40 + end + connect $35 $40 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $35 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_2" +module \core_calculate_stage_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$67 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_3.core.trial0" +module \trial0$78 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000000 + connect \B 8'10101000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_3.core.trial1" +module \trial1$79 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000001 + connect \B 8'10101000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_3.core.trial2" +module \trial2$80 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000100 + connect \B 8'10101000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_3.core.trial3" +module \trial3$81 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'001001 + connect \B 8'10101000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_3.core.trial4" +module \trial4$82 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'010000 + connect \B 8'10101000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_3.core.trial5" +module \trial5$83 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'011001 + connect \B 8'10101000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_3.core.trial6" +module \trial6$84 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'100100 + connect \B 8'10101000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_3.core.trial7" +module \trial7$85 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'110001 + connect \B 8'10101000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1101000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_3.core.pe" +module \pe$86 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_3.core" +module \core$77 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$78 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$79 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$80 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$81 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$82 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$83 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$84 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$85 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$86 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 66 + connect \A \next_bits + connect \B 6'110100 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 66 + connect \A \quotient_root + connect \B $31 + connect \Y $33 + end + connect $30 $33 + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $30 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 130 $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 130 + connect \A $36 + connect \B 6'110100 + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 130 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B $38 + connect \Y $40 + end + connect $35 $40 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $35 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4.core_calculate_stage_3" +module \core_calculate_stage_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$77 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_2_to_4" +module \pipe_2_to_4 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 4 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 5 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 7 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 16 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 18 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 20 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 21 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 22 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 23 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 24 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 25 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 26 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 28 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 29 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 30 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 31 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 32 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 33 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 34 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 35 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 36 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 37 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 38 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$1$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 39 \op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 40 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 41 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 46 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 50 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 51 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 52 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 53 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 54 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 55 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 56 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 57 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 58 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 59 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 60 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 61 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 62 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 63 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$26$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 64 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 65 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 66 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 67 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 68 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 69 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$32$next + cell \p$65 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$66 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_2_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_2_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_2_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_2_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_2_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_2_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_2_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_2_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_2_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_2_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_2_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_2_muxid$33 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_2_op__insn_type$34 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_2_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_2_op__imm_data__imm$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__imm_data__imm_ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__lk$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__invert_a$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_2_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_2_op__write_cr__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__write_cr__ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__output_carry$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__is_32bit$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_2_op__is_signed$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_2_op__data_len$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_2_op__insn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_2_ra$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_2_rb$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_2_xer_so$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_2_divisor_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_2_dividend_neg$58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_2_divisor_radicand$59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_2_operation$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_2_quotient_root$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_2_root_times_radicand$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_2_compare_lhs$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_2_compare_rhs$64 + cell \core_calculate_stage_2 \core_calculate_stage_2 + connect \muxid \core_calculate_stage_2_muxid + connect \op__insn_type \core_calculate_stage_2_op__insn_type + connect \op__fn_unit \core_calculate_stage_2_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_2_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_2_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_2_op__lk + connect \op__rc__rc \core_calculate_stage_2_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_2_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_2_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_2_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_2_op__invert_a + connect \op__zero_a \core_calculate_stage_2_op__zero_a + connect \op__input_carry \core_calculate_stage_2_op__input_carry + connect \op__invert_out \core_calculate_stage_2_op__invert_out + connect \op__write_cr__data \core_calculate_stage_2_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_2_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_2_op__output_carry + connect \op__is_32bit \core_calculate_stage_2_op__is_32bit + connect \op__is_signed \core_calculate_stage_2_op__is_signed + connect \op__data_len \core_calculate_stage_2_op__data_len + connect \op__insn \core_calculate_stage_2_op__insn + connect \ra \core_calculate_stage_2_ra + connect \rb \core_calculate_stage_2_rb + connect \xer_so \core_calculate_stage_2_xer_so + connect \divisor_neg \core_calculate_stage_2_divisor_neg + connect \dividend_neg \core_calculate_stage_2_dividend_neg + connect \divisor_radicand \core_calculate_stage_2_divisor_radicand + connect \operation \core_calculate_stage_2_operation + connect \quotient_root \core_calculate_stage_2_quotient_root + connect \root_times_radicand \core_calculate_stage_2_root_times_radicand + connect \compare_lhs \core_calculate_stage_2_compare_lhs + connect \compare_rhs \core_calculate_stage_2_compare_rhs + connect \muxid$1 \core_calculate_stage_2_muxid$33 + connect \op__insn_type$2 \core_calculate_stage_2_op__insn_type$34 + connect \op__fn_unit$3 \core_calculate_stage_2_op__fn_unit$35 + connect \op__imm_data__imm$4 \core_calculate_stage_2_op__imm_data__imm$36 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_2_op__imm_data__imm_ok$37 + connect \op__lk$6 \core_calculate_stage_2_op__lk$38 + connect \op__rc__rc$7 \core_calculate_stage_2_op__rc__rc$39 + connect \op__rc__rc_ok$8 \core_calculate_stage_2_op__rc__rc_ok$40 + connect \op__oe__oe$9 \core_calculate_stage_2_op__oe__oe$41 + connect \op__oe__oe_ok$10 \core_calculate_stage_2_op__oe__oe_ok$42 + connect \op__invert_a$11 \core_calculate_stage_2_op__invert_a$43 + connect \op__zero_a$12 \core_calculate_stage_2_op__zero_a$44 + connect \op__input_carry$13 \core_calculate_stage_2_op__input_carry$45 + connect \op__invert_out$14 \core_calculate_stage_2_op__invert_out$46 + connect \op__write_cr__data$15 \core_calculate_stage_2_op__write_cr__data$47 + connect \op__write_cr__ok$16 \core_calculate_stage_2_op__write_cr__ok$48 + connect \op__output_carry$17 \core_calculate_stage_2_op__output_carry$49 + connect \op__is_32bit$18 \core_calculate_stage_2_op__is_32bit$50 + connect \op__is_signed$19 \core_calculate_stage_2_op__is_signed$51 + connect \op__data_len$20 \core_calculate_stage_2_op__data_len$52 + connect \op__insn$21 \core_calculate_stage_2_op__insn$53 + connect \ra$22 \core_calculate_stage_2_ra$54 + connect \rb$23 \core_calculate_stage_2_rb$55 + connect \xer_so$24 \core_calculate_stage_2_xer_so$56 + connect \divisor_neg$25 \core_calculate_stage_2_divisor_neg$57 + connect \dividend_neg$26 \core_calculate_stage_2_dividend_neg$58 + connect \divisor_radicand$27 \core_calculate_stage_2_divisor_radicand$59 + connect \operation$28 \core_calculate_stage_2_operation$60 + connect \quotient_root$29 \core_calculate_stage_2_quotient_root$61 + connect \root_times_radicand$30 \core_calculate_stage_2_root_times_radicand$62 + connect \compare_lhs$31 \core_calculate_stage_2_compare_lhs$63 + connect \compare_rhs$32 \core_calculate_stage_2_compare_rhs$64 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_3_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_3_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_3_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_3_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_3_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_3_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_3_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_3_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_3_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_3_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_3_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_3_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_3_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_3_muxid$65 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_3_op__insn_type$66 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_3_op__fn_unit$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_3_op__imm_data__imm$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__imm_data__imm_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__lk$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__rc__rc_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__oe__oe_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__invert_a$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__zero_a$76 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_3_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_3_op__write_cr__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__write_cr__ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_3_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_3_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_3_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_3_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_3_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_3_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_3_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_3_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_3_divisor_radicand$91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_3_operation$92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_3_quotient_root$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_3_root_times_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_3_compare_lhs$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_3_compare_rhs$96 + cell \core_calculate_stage_3 \core_calculate_stage_3 + connect \muxid \core_calculate_stage_3_muxid + connect \op__insn_type \core_calculate_stage_3_op__insn_type + connect \op__fn_unit \core_calculate_stage_3_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_3_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_3_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_3_op__lk + connect \op__rc__rc \core_calculate_stage_3_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_3_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_3_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_3_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_3_op__invert_a + connect \op__zero_a \core_calculate_stage_3_op__zero_a + connect \op__input_carry \core_calculate_stage_3_op__input_carry + connect \op__invert_out \core_calculate_stage_3_op__invert_out + connect \op__write_cr__data \core_calculate_stage_3_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_3_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_3_op__output_carry + connect \op__is_32bit \core_calculate_stage_3_op__is_32bit + connect \op__is_signed \core_calculate_stage_3_op__is_signed + connect \op__data_len \core_calculate_stage_3_op__data_len + connect \op__insn \core_calculate_stage_3_op__insn + connect \ra \core_calculate_stage_3_ra + connect \rb \core_calculate_stage_3_rb + connect \xer_so \core_calculate_stage_3_xer_so + connect \divisor_neg \core_calculate_stage_3_divisor_neg + connect \dividend_neg \core_calculate_stage_3_dividend_neg + connect \divisor_radicand \core_calculate_stage_3_divisor_radicand + connect \operation \core_calculate_stage_3_operation + connect \quotient_root \core_calculate_stage_3_quotient_root + connect \root_times_radicand \core_calculate_stage_3_root_times_radicand + connect \compare_lhs \core_calculate_stage_3_compare_lhs + connect \compare_rhs \core_calculate_stage_3_compare_rhs + connect \muxid$1 \core_calculate_stage_3_muxid$65 + connect \op__insn_type$2 \core_calculate_stage_3_op__insn_type$66 + connect \op__fn_unit$3 \core_calculate_stage_3_op__fn_unit$67 + connect \op__imm_data__imm$4 \core_calculate_stage_3_op__imm_data__imm$68 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_3_op__imm_data__imm_ok$69 + connect \op__lk$6 \core_calculate_stage_3_op__lk$70 + connect \op__rc__rc$7 \core_calculate_stage_3_op__rc__rc$71 + connect \op__rc__rc_ok$8 \core_calculate_stage_3_op__rc__rc_ok$72 + connect \op__oe__oe$9 \core_calculate_stage_3_op__oe__oe$73 + connect \op__oe__oe_ok$10 \core_calculate_stage_3_op__oe__oe_ok$74 + connect \op__invert_a$11 \core_calculate_stage_3_op__invert_a$75 + connect \op__zero_a$12 \core_calculate_stage_3_op__zero_a$76 + connect \op__input_carry$13 \core_calculate_stage_3_op__input_carry$77 + connect \op__invert_out$14 \core_calculate_stage_3_op__invert_out$78 + connect \op__write_cr__data$15 \core_calculate_stage_3_op__write_cr__data$79 + connect \op__write_cr__ok$16 \core_calculate_stage_3_op__write_cr__ok$80 + connect \op__output_carry$17 \core_calculate_stage_3_op__output_carry$81 + connect \op__is_32bit$18 \core_calculate_stage_3_op__is_32bit$82 + connect \op__is_signed$19 \core_calculate_stage_3_op__is_signed$83 + connect \op__data_len$20 \core_calculate_stage_3_op__data_len$84 + connect \op__insn$21 \core_calculate_stage_3_op__insn$85 + connect \ra$22 \core_calculate_stage_3_ra$86 + connect \rb$23 \core_calculate_stage_3_rb$87 + connect \xer_so$24 \core_calculate_stage_3_xer_so$88 + connect \divisor_neg$25 \core_calculate_stage_3_divisor_neg$89 + connect \dividend_neg$26 \core_calculate_stage_3_dividend_neg$90 + connect \divisor_radicand$27 \core_calculate_stage_3_divisor_radicand$91 + connect \operation$28 \core_calculate_stage_3_operation$92 + connect \quotient_root$29 \core_calculate_stage_3_quotient_root$93 + connect \root_times_radicand$30 \core_calculate_stage_3_root_times_radicand$94 + connect \compare_lhs$31 \core_calculate_stage_3_compare_lhs$95 + connect \compare_rhs$32 \core_calculate_stage_3_compare_rhs$96 + end + process $group_0 + assign \core_calculate_stage_2_muxid 2'00 + assign \core_calculate_stage_2_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_2_op__insn_type 7'0000000 + assign \core_calculate_stage_2_op__fn_unit 10'0000000000 + assign \core_calculate_stage_2_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_2_op__lk 1'0 + assign \core_calculate_stage_2_op__rc__rc 1'0 + assign \core_calculate_stage_2_op__rc__rc_ok 1'0 + assign \core_calculate_stage_2_op__oe__oe 1'0 + assign \core_calculate_stage_2_op__oe__oe_ok 1'0 + assign \core_calculate_stage_2_op__invert_a 1'0 + assign \core_calculate_stage_2_op__zero_a 1'0 + assign \core_calculate_stage_2_op__input_carry 2'00 + assign \core_calculate_stage_2_op__invert_out 1'0 + assign \core_calculate_stage_2_op__write_cr__data 3'000 + assign \core_calculate_stage_2_op__write_cr__ok 1'0 + assign \core_calculate_stage_2_op__output_carry 1'0 + assign \core_calculate_stage_2_op__is_32bit 1'0 + assign \core_calculate_stage_2_op__is_signed 1'0 + assign \core_calculate_stage_2_op__data_len 4'0000 + assign \core_calculate_stage_2_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_2_op__insn \core_calculate_stage_2_op__data_len \core_calculate_stage_2_op__is_signed \core_calculate_stage_2_op__is_32bit \core_calculate_stage_2_op__output_carry { \core_calculate_stage_2_op__write_cr__ok \core_calculate_stage_2_op__write_cr__data } \core_calculate_stage_2_op__invert_out \core_calculate_stage_2_op__input_carry \core_calculate_stage_2_op__zero_a \core_calculate_stage_2_op__invert_a { \core_calculate_stage_2_op__oe__oe_ok \core_calculate_stage_2_op__oe__oe } { \core_calculate_stage_2_op__rc__rc_ok \core_calculate_stage_2_op__rc__rc } \core_calculate_stage_2_op__lk { \core_calculate_stage_2_op__imm_data__imm_ok \core_calculate_stage_2_op__imm_data__imm } \core_calculate_stage_2_op__fn_unit \core_calculate_stage_2_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \core_calculate_stage_2_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_ra \ra + sync init + end + process $group_22 + assign \core_calculate_stage_2_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_rb \rb + sync init + end + process $group_23 + assign \core_calculate_stage_2_xer_so 1'0 + assign \core_calculate_stage_2_xer_so \xer_so + sync init + end + process $group_24 + assign \core_calculate_stage_2_divisor_neg 1'0 + assign \core_calculate_stage_2_divisor_neg \divisor_neg + sync init + end + process $group_25 + assign \core_calculate_stage_2_dividend_neg 1'0 + assign \core_calculate_stage_2_dividend_neg \dividend_neg + sync init + end + process $group_26 + assign \core_calculate_stage_2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_calculate_stage_2_operation 2'00 + assign \core_calculate_stage_2_operation \operation + sync init + end + process $group_28 + assign \core_calculate_stage_2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_calculate_stage_2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_calculate_stage_2_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_calculate_stage_2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_2_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \core_calculate_stage_3_muxid 2'00 + assign \core_calculate_stage_3_muxid \core_calculate_stage_2_muxid$33 + sync init + end + process $group_33 + assign \core_calculate_stage_3_op__insn_type 7'0000000 + assign \core_calculate_stage_3_op__fn_unit 10'0000000000 + assign \core_calculate_stage_3_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_3_op__lk 1'0 + assign \core_calculate_stage_3_op__rc__rc 1'0 + assign \core_calculate_stage_3_op__rc__rc_ok 1'0 + assign \core_calculate_stage_3_op__oe__oe 1'0 + assign \core_calculate_stage_3_op__oe__oe_ok 1'0 + assign \core_calculate_stage_3_op__invert_a 1'0 + assign \core_calculate_stage_3_op__zero_a 1'0 + assign \core_calculate_stage_3_op__input_carry 2'00 + assign \core_calculate_stage_3_op__invert_out 1'0 + assign \core_calculate_stage_3_op__write_cr__data 3'000 + assign \core_calculate_stage_3_op__write_cr__ok 1'0 + assign \core_calculate_stage_3_op__output_carry 1'0 + assign \core_calculate_stage_3_op__is_32bit 1'0 + assign \core_calculate_stage_3_op__is_signed 1'0 + assign \core_calculate_stage_3_op__data_len 4'0000 + assign \core_calculate_stage_3_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_3_op__insn \core_calculate_stage_3_op__data_len \core_calculate_stage_3_op__is_signed \core_calculate_stage_3_op__is_32bit \core_calculate_stage_3_op__output_carry { \core_calculate_stage_3_op__write_cr__ok \core_calculate_stage_3_op__write_cr__data } \core_calculate_stage_3_op__invert_out \core_calculate_stage_3_op__input_carry \core_calculate_stage_3_op__zero_a \core_calculate_stage_3_op__invert_a { \core_calculate_stage_3_op__oe__oe_ok \core_calculate_stage_3_op__oe__oe } { \core_calculate_stage_3_op__rc__rc_ok \core_calculate_stage_3_op__rc__rc } \core_calculate_stage_3_op__lk { \core_calculate_stage_3_op__imm_data__imm_ok \core_calculate_stage_3_op__imm_data__imm } \core_calculate_stage_3_op__fn_unit \core_calculate_stage_3_op__insn_type } { \core_calculate_stage_2_op__insn$53 \core_calculate_stage_2_op__data_len$52 \core_calculate_stage_2_op__is_signed$51 \core_calculate_stage_2_op__is_32bit$50 \core_calculate_stage_2_op__output_carry$49 { \core_calculate_stage_2_op__write_cr__ok$48 \core_calculate_stage_2_op__write_cr__data$47 } \core_calculate_stage_2_op__invert_out$46 \core_calculate_stage_2_op__input_carry$45 \core_calculate_stage_2_op__zero_a$44 \core_calculate_stage_2_op__invert_a$43 { \core_calculate_stage_2_op__oe__oe_ok$42 \core_calculate_stage_2_op__oe__oe$41 } { \core_calculate_stage_2_op__rc__rc_ok$40 \core_calculate_stage_2_op__rc__rc$39 } \core_calculate_stage_2_op__lk$38 { \core_calculate_stage_2_op__imm_data__imm_ok$37 \core_calculate_stage_2_op__imm_data__imm$36 } \core_calculate_stage_2_op__fn_unit$35 \core_calculate_stage_2_op__insn_type$34 } + sync init + end + process $group_53 + assign \core_calculate_stage_3_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_ra \core_calculate_stage_2_ra$54 + sync init + end + process $group_54 + assign \core_calculate_stage_3_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_rb \core_calculate_stage_2_rb$55 + sync init + end + process $group_55 + assign \core_calculate_stage_3_xer_so 1'0 + assign \core_calculate_stage_3_xer_so \core_calculate_stage_2_xer_so$56 + sync init + end + process $group_56 + assign \core_calculate_stage_3_divisor_neg 1'0 + assign \core_calculate_stage_3_divisor_neg \core_calculate_stage_2_divisor_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_3_dividend_neg 1'0 + assign \core_calculate_stage_3_dividend_neg \core_calculate_stage_2_dividend_neg$58 + sync init + end + process $group_58 + assign \core_calculate_stage_3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_divisor_radicand \core_calculate_stage_2_divisor_radicand$59 + sync init + end + process $group_59 + assign \core_calculate_stage_3_operation 2'00 + assign \core_calculate_stage_3_operation \core_calculate_stage_2_operation$60 + sync init + end + process $group_60 + assign \core_calculate_stage_3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_quotient_root \core_calculate_stage_2_quotient_root$61 + sync init + end + process $group_61 + assign \core_calculate_stage_3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_root_times_radicand \core_calculate_stage_2_root_times_radicand$62 + sync init + end + process $group_62 + assign \core_calculate_stage_3_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_compare_lhs \core_calculate_stage_2_compare_lhs$63 + sync init + end + process $group_63 + assign \core_calculate_stage_3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_3_compare_rhs \core_calculate_stage_2_compare_rhs$64 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$97 + process $group_64 + assign \p_valid_i$97 1'0 + assign \p_valid_i$97 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_65 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $98 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$97 + connect \B \p_ready_o + connect \Y $98 + end + process $group_66 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $98 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$100 + process $group_67 + assign \muxid$100 2'00 + assign \muxid$100 \core_calculate_stage_3_muxid$65 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$111 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$120 + process $group_68 + assign \op__insn_type$101 7'0000000 + assign \op__fn_unit$102 10'0000000000 + assign \op__imm_data__imm$103 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$104 1'0 + assign \op__lk$105 1'0 + assign \op__rc__rc$106 1'0 + assign \op__rc__rc_ok$107 1'0 + assign \op__oe__oe$108 1'0 + assign \op__oe__oe_ok$109 1'0 + assign \op__invert_a$110 1'0 + assign \op__zero_a$111 1'0 + assign \op__input_carry$112 2'00 + assign \op__invert_out$113 1'0 + assign \op__write_cr__data$114 3'000 + assign \op__write_cr__ok$115 1'0 + assign \op__output_carry$116 1'0 + assign \op__is_32bit$117 1'0 + assign \op__is_signed$118 1'0 + assign \op__data_len$119 4'0000 + assign \op__insn$120 32'00000000000000000000000000000000 + assign { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } { \core_calculate_stage_3_op__insn$85 \core_calculate_stage_3_op__data_len$84 \core_calculate_stage_3_op__is_signed$83 \core_calculate_stage_3_op__is_32bit$82 \core_calculate_stage_3_op__output_carry$81 { \core_calculate_stage_3_op__write_cr__ok$80 \core_calculate_stage_3_op__write_cr__data$79 } \core_calculate_stage_3_op__invert_out$78 \core_calculate_stage_3_op__input_carry$77 \core_calculate_stage_3_op__zero_a$76 \core_calculate_stage_3_op__invert_a$75 { \core_calculate_stage_3_op__oe__oe_ok$74 \core_calculate_stage_3_op__oe__oe$73 } { \core_calculate_stage_3_op__rc__rc_ok$72 \core_calculate_stage_3_op__rc__rc$71 } \core_calculate_stage_3_op__lk$70 { \core_calculate_stage_3_op__imm_data__imm_ok$69 \core_calculate_stage_3_op__imm_data__imm$68 } \core_calculate_stage_3_op__fn_unit$67 \core_calculate_stage_3_op__insn_type$66 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$121 + process $group_88 + assign \ra$121 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$121 \core_calculate_stage_3_ra$86 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$122 + process $group_89 + assign \rb$122 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$122 \core_calculate_stage_3_rb$87 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$123 + process $group_90 + assign \xer_so$123 1'0 + assign \xer_so$123 \core_calculate_stage_3_xer_so$88 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$124 + process $group_91 + assign \divisor_neg$124 1'0 + assign \divisor_neg$124 \core_calculate_stage_3_divisor_neg$89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$125 + process $group_92 + assign \dividend_neg$125 1'0 + assign \dividend_neg$125 \core_calculate_stage_3_dividend_neg$90 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$126 + process $group_93 + assign \divisor_radicand$126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$126 \core_calculate_stage_3_divisor_radicand$91 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$127 + process $group_94 + assign \operation$127 2'00 + assign \operation$127 \core_calculate_stage_3_operation$92 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$128 + process $group_95 + assign \quotient_root$128 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$128 \core_calculate_stage_3_quotient_root$93 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$129 + process $group_96 + assign \root_times_radicand$129 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$129 \core_calculate_stage_3_root_times_radicand$94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$130 + process $group_97 + assign \compare_lhs$130 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$130 \core_calculate_stage_3_compare_lhs$95 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$131 + process $group_98 + assign \compare_rhs$131 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$131 \core_calculate_stage_3_compare_rhs$96 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_99 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_100 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$100 + end + sync init + update \muxid$1 2'00 + sync posedge \clk + update \muxid$1 \muxid$1$next + end + process $group_101 + assign \op__insn_type$2$next \op__insn_type$2 + assign \op__fn_unit$3$next \op__fn_unit$3 + assign \op__imm_data__imm$4$next \op__imm_data__imm$4 + assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5 + assign \op__lk$6$next \op__lk$6 + assign \op__rc__rc$7$next \op__rc__rc$7 + assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8 + assign \op__oe__oe$9$next \op__oe__oe$9 + assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10 + assign \op__invert_a$11$next \op__invert_a$11 + assign \op__zero_a$12$next \op__zero_a$12 + assign \op__input_carry$13$next \op__input_carry$13 + assign \op__invert_out$14$next \op__invert_out$14 + assign \op__write_cr__data$15$next \op__write_cr__data$15 + assign \op__write_cr__ok$16$next \op__write_cr__ok$16 + assign \op__output_carry$17$next \op__output_carry$17 + assign \op__is_32bit$18$next \op__is_32bit$18 + assign \op__is_signed$19$next \op__is_signed$19 + assign \op__data_len$20$next \op__data_len$20 + assign \op__insn$21$next \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5$next 1'0 + assign \op__rc__rc$7$next 1'0 + assign \op__rc__rc_ok$8$next 1'0 + assign \op__oe__oe$9$next 1'0 + assign \op__oe__oe_ok$10$next 1'0 + assign \op__write_cr__data$15$next 3'000 + assign \op__write_cr__ok$16$next 1'0 + assign \op__insn$21$next 32'00000000000000000000000000000000 + end + sync init + update \op__insn_type$2 7'0000000 + update \op__fn_unit$3 10'0000000000 + update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \op__imm_data__imm_ok$5 1'0 + update \op__lk$6 1'0 + update \op__rc__rc$7 1'0 + update \op__rc__rc_ok$8 1'0 + update \op__oe__oe$9 1'0 + update \op__oe__oe_ok$10 1'0 + update \op__invert_a$11 1'0 + update \op__zero_a$12 1'0 + update \op__input_carry$13 2'00 + update \op__invert_out$14 1'0 + update \op__write_cr__data$15 3'000 + update \op__write_cr__ok$16 1'0 + update \op__output_carry$17 1'0 + update \op__is_32bit$18 1'0 + update \op__is_signed$19 1'0 + update \op__data_len$20 4'0000 + update \op__insn$21 32'00000000000000000000000000000000 + sync posedge \clk + update \op__insn_type$2 \op__insn_type$2$next + update \op__fn_unit$3 \op__fn_unit$3$next + update \op__imm_data__imm$4 \op__imm_data__imm$4$next + update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next + update \op__lk$6 \op__lk$6$next + update \op__rc__rc$7 \op__rc__rc$7$next + update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next + update \op__oe__oe$9 \op__oe__oe$9$next + update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next + update \op__invert_a$11 \op__invert_a$11$next + update \op__zero_a$12 \op__zero_a$12$next + update \op__input_carry$13 \op__input_carry$13$next + update \op__invert_out$14 \op__invert_out$14$next + update \op__write_cr__data$15 \op__write_cr__data$15$next + update \op__write_cr__ok$16 \op__write_cr__ok$16$next + update \op__output_carry$17 \op__output_carry$17$next + update \op__is_32bit$18 \op__is_32bit$18$next + update \op__is_signed$19 \op__is_signed$19$next + update \op__data_len$20 \op__data_len$20$next + update \op__insn$21 \op__insn$21$next + end + process $group_121 + assign \ra$22$next \ra$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$22$next \ra$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$22$next \ra$121 + end + sync init + update \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \ra$22 \ra$22$next + end + process $group_122 + assign \rb$23$next \rb$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$23$next \rb$122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$23$next \rb$122 + end + sync init + update \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \rb$23 \rb$23$next + end + process $group_123 + assign \xer_so$24$next \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$24$next \xer_so$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$24$next \xer_so$123 + end + sync init + update \xer_so$24 1'0 + sync posedge \clk + update \xer_so$24 \xer_so$24$next + end + process $group_124 + assign \divisor_neg$25$next \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$25$next \divisor_neg$124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$25$next \divisor_neg$124 + end + sync init + update \divisor_neg$25 1'0 + sync posedge \clk + update \divisor_neg$25 \divisor_neg$25$next + end + process $group_125 + assign \dividend_neg$26$next \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$26$next \dividend_neg$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$26$next \dividend_neg$125 + end + sync init + update \dividend_neg$26 1'0 + sync posedge \clk + update \dividend_neg$26 \dividend_neg$26$next + end + process $group_126 + assign \divisor_radicand$27$next \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$27$next \divisor_radicand$126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$27$next \divisor_radicand$126 + end + sync init + update \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \divisor_radicand$27 \divisor_radicand$27$next + end + process $group_127 + assign \operation$28$next \operation$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$28$next \operation$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$28$next \operation$127 + end + sync init + update \operation$28 2'00 + sync posedge \clk + update \operation$28 \operation$28$next + end + process $group_128 + assign \quotient_root$29$next \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$29$next \quotient_root$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$29$next \quotient_root$128 + end + sync init + update \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \quotient_root$29 \quotient_root$29$next + end + process $group_129 + assign \root_times_radicand$30$next \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$30$next \root_times_radicand$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$30$next \root_times_radicand$129 + end + sync init + update \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \root_times_radicand$30 \root_times_radicand$30$next + end + process $group_130 + assign \compare_lhs$31$next \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$31$next \compare_lhs$130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$31$next \compare_lhs$130 + end + sync init + update \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_lhs$31 \compare_lhs$31$next + end + process $group_131 + assign \compare_rhs$32$next \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$32$next \compare_rhs$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$32$next \compare_rhs$131 + end + sync init + update \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_rhs$32 \compare_rhs$32$next + end + process $group_132 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_133 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.p" +module \p$87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.n" +module \n$88 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_4.core.trial0" +module \trial0$90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000000 + connect \B 8'10100010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1100010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_4.core.trial1" +module \trial1$91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000001 + connect \B 8'10100010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1100010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_4.core.trial2" +module \trial2$92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000100 + connect \B 8'10100010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1100010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_4.core.trial3" +module \trial3$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'001001 + connect \B 8'10100010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1100010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_4.core.trial4" +module \trial4$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'010000 + connect \B 8'10100010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1100010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_4.core.trial5" +module \trial5$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'011001 + connect \B 8'10100010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1100010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_4.core.trial6" +module \trial6$96 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'100100 + connect \B 8'10100010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1100010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_4.core.trial7" +module \trial7$97 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1110001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1110010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'110001 + connect \B 8'10100010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'110010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1100010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_4.core.pe" +module \pe$98 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_4.core" +module \core$89 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$90 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$91 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$92 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$93 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$94 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$95 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$96 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$97 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$98 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 66 + connect \A \next_bits + connect \B 6'110001 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 66 + connect \A \quotient_root + connect \B $31 + connect \Y $33 + end + connect $30 $33 + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $30 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 130 $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 130 + connect \A $36 + connect \B 6'110001 + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 130 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B $38 + connect \Y $40 + end + connect $35 $40 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $35 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_4" +module \core_calculate_stage_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$89 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_5.core.trial0" +module \trial0$100 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000000 + connect \B 8'10011100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1011100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_5.core.trial1" +module \trial1$101 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000001 + connect \B 8'10011100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1011100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_5.core.trial2" +module \trial2$102 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000100 + connect \B 8'10011100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1011100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_5.core.trial3" +module \trial3$103 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'001001 + connect \B 8'10011100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1011100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_5.core.trial4" +module \trial4$104 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'010000 + connect \B 8'10011100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1011100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_5.core.trial5" +module \trial5$105 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'011001 + connect \B 8'10011100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1011100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_5.core.trial6" +module \trial6$106 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'100100 + connect \B 8'10011100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1011100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_5.core.trial7" +module \trial7$107 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'110001 + connect \B 8'10011100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1011100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_5.core.pe" +module \pe$108 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_5.core" +module \core$99 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$100 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$101 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$102 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$103 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$104 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$105 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$106 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$107 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$108 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 66 + connect \A \next_bits + connect \B 6'101110 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 66 + connect \A \quotient_root + connect \B $31 + connect \Y $33 + end + connect $30 $33 + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $30 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 130 $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 130 + connect \A $36 + connect \B 6'101110 + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 130 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B $38 + connect \Y $40 + end + connect $35 $40 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $35 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6.core_calculate_stage_5" +module \core_calculate_stage_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$99 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_4_to_6" +module \pipe_4_to_6 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 4 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 5 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 7 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 16 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 18 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 20 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 21 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 22 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 23 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 24 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 25 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 26 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 28 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 29 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 30 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 31 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 32 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 33 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 34 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 35 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 36 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 37 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 38 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$1$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 39 \op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 40 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 41 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 46 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 50 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 51 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 52 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 53 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 54 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 55 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 56 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 57 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 58 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 59 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 60 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 61 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 62 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 63 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$26$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 64 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 65 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 66 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 67 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 68 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 69 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$32$next + cell \p$87 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$88 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_4_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_4_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_4_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_4_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_4_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_4_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_4_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_4_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_4_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_4_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_4_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_4_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_4_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_4_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_4_muxid$33 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_4_op__insn_type$34 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_4_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_4_op__imm_data__imm$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__imm_data__imm_ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__lk$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__invert_a$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_4_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_4_op__write_cr__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__write_cr__ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__output_carry$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__is_32bit$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_4_op__is_signed$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_4_op__data_len$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_4_op__insn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_4_ra$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_4_rb$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_4_xer_so$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_4_divisor_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_4_dividend_neg$58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_4_divisor_radicand$59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_4_operation$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_4_quotient_root$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_4_root_times_radicand$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_4_compare_lhs$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_4_compare_rhs$64 + cell \core_calculate_stage_4 \core_calculate_stage_4 + connect \muxid \core_calculate_stage_4_muxid + connect \op__insn_type \core_calculate_stage_4_op__insn_type + connect \op__fn_unit \core_calculate_stage_4_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_4_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_4_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_4_op__lk + connect \op__rc__rc \core_calculate_stage_4_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_4_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_4_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_4_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_4_op__invert_a + connect \op__zero_a \core_calculate_stage_4_op__zero_a + connect \op__input_carry \core_calculate_stage_4_op__input_carry + connect \op__invert_out \core_calculate_stage_4_op__invert_out + connect \op__write_cr__data \core_calculate_stage_4_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_4_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_4_op__output_carry + connect \op__is_32bit \core_calculate_stage_4_op__is_32bit + connect \op__is_signed \core_calculate_stage_4_op__is_signed + connect \op__data_len \core_calculate_stage_4_op__data_len + connect \op__insn \core_calculate_stage_4_op__insn + connect \ra \core_calculate_stage_4_ra + connect \rb \core_calculate_stage_4_rb + connect \xer_so \core_calculate_stage_4_xer_so + connect \divisor_neg \core_calculate_stage_4_divisor_neg + connect \dividend_neg \core_calculate_stage_4_dividend_neg + connect \divisor_radicand \core_calculate_stage_4_divisor_radicand + connect \operation \core_calculate_stage_4_operation + connect \quotient_root \core_calculate_stage_4_quotient_root + connect \root_times_radicand \core_calculate_stage_4_root_times_radicand + connect \compare_lhs \core_calculate_stage_4_compare_lhs + connect \compare_rhs \core_calculate_stage_4_compare_rhs + connect \muxid$1 \core_calculate_stage_4_muxid$33 + connect \op__insn_type$2 \core_calculate_stage_4_op__insn_type$34 + connect \op__fn_unit$3 \core_calculate_stage_4_op__fn_unit$35 + connect \op__imm_data__imm$4 \core_calculate_stage_4_op__imm_data__imm$36 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_4_op__imm_data__imm_ok$37 + connect \op__lk$6 \core_calculate_stage_4_op__lk$38 + connect \op__rc__rc$7 \core_calculate_stage_4_op__rc__rc$39 + connect \op__rc__rc_ok$8 \core_calculate_stage_4_op__rc__rc_ok$40 + connect \op__oe__oe$9 \core_calculate_stage_4_op__oe__oe$41 + connect \op__oe__oe_ok$10 \core_calculate_stage_4_op__oe__oe_ok$42 + connect \op__invert_a$11 \core_calculate_stage_4_op__invert_a$43 + connect \op__zero_a$12 \core_calculate_stage_4_op__zero_a$44 + connect \op__input_carry$13 \core_calculate_stage_4_op__input_carry$45 + connect \op__invert_out$14 \core_calculate_stage_4_op__invert_out$46 + connect \op__write_cr__data$15 \core_calculate_stage_4_op__write_cr__data$47 + connect \op__write_cr__ok$16 \core_calculate_stage_4_op__write_cr__ok$48 + connect \op__output_carry$17 \core_calculate_stage_4_op__output_carry$49 + connect \op__is_32bit$18 \core_calculate_stage_4_op__is_32bit$50 + connect \op__is_signed$19 \core_calculate_stage_4_op__is_signed$51 + connect \op__data_len$20 \core_calculate_stage_4_op__data_len$52 + connect \op__insn$21 \core_calculate_stage_4_op__insn$53 + connect \ra$22 \core_calculate_stage_4_ra$54 + connect \rb$23 \core_calculate_stage_4_rb$55 + connect \xer_so$24 \core_calculate_stage_4_xer_so$56 + connect \divisor_neg$25 \core_calculate_stage_4_divisor_neg$57 + connect \dividend_neg$26 \core_calculate_stage_4_dividend_neg$58 + connect \divisor_radicand$27 \core_calculate_stage_4_divisor_radicand$59 + connect \operation$28 \core_calculate_stage_4_operation$60 + connect \quotient_root$29 \core_calculate_stage_4_quotient_root$61 + connect \root_times_radicand$30 \core_calculate_stage_4_root_times_radicand$62 + connect \compare_lhs$31 \core_calculate_stage_4_compare_lhs$63 + connect \compare_rhs$32 \core_calculate_stage_4_compare_rhs$64 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_5_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_5_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_5_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_5_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_5_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_5_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_5_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_5_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_5_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_5_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_5_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_5_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_5_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_5_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_5_muxid$65 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_5_op__insn_type$66 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_5_op__fn_unit$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_5_op__imm_data__imm$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__imm_data__imm_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__lk$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__rc__rc_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__oe__oe_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__invert_a$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__zero_a$76 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_5_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_5_op__write_cr__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__write_cr__ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_5_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_5_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_5_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_5_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_5_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_5_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_5_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_5_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_5_divisor_radicand$91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_5_operation$92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_5_quotient_root$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_5_root_times_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_5_compare_lhs$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_5_compare_rhs$96 + cell \core_calculate_stage_5 \core_calculate_stage_5 + connect \muxid \core_calculate_stage_5_muxid + connect \op__insn_type \core_calculate_stage_5_op__insn_type + connect \op__fn_unit \core_calculate_stage_5_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_5_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_5_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_5_op__lk + connect \op__rc__rc \core_calculate_stage_5_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_5_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_5_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_5_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_5_op__invert_a + connect \op__zero_a \core_calculate_stage_5_op__zero_a + connect \op__input_carry \core_calculate_stage_5_op__input_carry + connect \op__invert_out \core_calculate_stage_5_op__invert_out + connect \op__write_cr__data \core_calculate_stage_5_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_5_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_5_op__output_carry + connect \op__is_32bit \core_calculate_stage_5_op__is_32bit + connect \op__is_signed \core_calculate_stage_5_op__is_signed + connect \op__data_len \core_calculate_stage_5_op__data_len + connect \op__insn \core_calculate_stage_5_op__insn + connect \ra \core_calculate_stage_5_ra + connect \rb \core_calculate_stage_5_rb + connect \xer_so \core_calculate_stage_5_xer_so + connect \divisor_neg \core_calculate_stage_5_divisor_neg + connect \dividend_neg \core_calculate_stage_5_dividend_neg + connect \divisor_radicand \core_calculate_stage_5_divisor_radicand + connect \operation \core_calculate_stage_5_operation + connect \quotient_root \core_calculate_stage_5_quotient_root + connect \root_times_radicand \core_calculate_stage_5_root_times_radicand + connect \compare_lhs \core_calculate_stage_5_compare_lhs + connect \compare_rhs \core_calculate_stage_5_compare_rhs + connect \muxid$1 \core_calculate_stage_5_muxid$65 + connect \op__insn_type$2 \core_calculate_stage_5_op__insn_type$66 + connect \op__fn_unit$3 \core_calculate_stage_5_op__fn_unit$67 + connect \op__imm_data__imm$4 \core_calculate_stage_5_op__imm_data__imm$68 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_5_op__imm_data__imm_ok$69 + connect \op__lk$6 \core_calculate_stage_5_op__lk$70 + connect \op__rc__rc$7 \core_calculate_stage_5_op__rc__rc$71 + connect \op__rc__rc_ok$8 \core_calculate_stage_5_op__rc__rc_ok$72 + connect \op__oe__oe$9 \core_calculate_stage_5_op__oe__oe$73 + connect \op__oe__oe_ok$10 \core_calculate_stage_5_op__oe__oe_ok$74 + connect \op__invert_a$11 \core_calculate_stage_5_op__invert_a$75 + connect \op__zero_a$12 \core_calculate_stage_5_op__zero_a$76 + connect \op__input_carry$13 \core_calculate_stage_5_op__input_carry$77 + connect \op__invert_out$14 \core_calculate_stage_5_op__invert_out$78 + connect \op__write_cr__data$15 \core_calculate_stage_5_op__write_cr__data$79 + connect \op__write_cr__ok$16 \core_calculate_stage_5_op__write_cr__ok$80 + connect \op__output_carry$17 \core_calculate_stage_5_op__output_carry$81 + connect \op__is_32bit$18 \core_calculate_stage_5_op__is_32bit$82 + connect \op__is_signed$19 \core_calculate_stage_5_op__is_signed$83 + connect \op__data_len$20 \core_calculate_stage_5_op__data_len$84 + connect \op__insn$21 \core_calculate_stage_5_op__insn$85 + connect \ra$22 \core_calculate_stage_5_ra$86 + connect \rb$23 \core_calculate_stage_5_rb$87 + connect \xer_so$24 \core_calculate_stage_5_xer_so$88 + connect \divisor_neg$25 \core_calculate_stage_5_divisor_neg$89 + connect \dividend_neg$26 \core_calculate_stage_5_dividend_neg$90 + connect \divisor_radicand$27 \core_calculate_stage_5_divisor_radicand$91 + connect \operation$28 \core_calculate_stage_5_operation$92 + connect \quotient_root$29 \core_calculate_stage_5_quotient_root$93 + connect \root_times_radicand$30 \core_calculate_stage_5_root_times_radicand$94 + connect \compare_lhs$31 \core_calculate_stage_5_compare_lhs$95 + connect \compare_rhs$32 \core_calculate_stage_5_compare_rhs$96 + end + process $group_0 + assign \core_calculate_stage_4_muxid 2'00 + assign \core_calculate_stage_4_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_4_op__insn_type 7'0000000 + assign \core_calculate_stage_4_op__fn_unit 10'0000000000 + assign \core_calculate_stage_4_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_4_op__lk 1'0 + assign \core_calculate_stage_4_op__rc__rc 1'0 + assign \core_calculate_stage_4_op__rc__rc_ok 1'0 + assign \core_calculate_stage_4_op__oe__oe 1'0 + assign \core_calculate_stage_4_op__oe__oe_ok 1'0 + assign \core_calculate_stage_4_op__invert_a 1'0 + assign \core_calculate_stage_4_op__zero_a 1'0 + assign \core_calculate_stage_4_op__input_carry 2'00 + assign \core_calculate_stage_4_op__invert_out 1'0 + assign \core_calculate_stage_4_op__write_cr__data 3'000 + assign \core_calculate_stage_4_op__write_cr__ok 1'0 + assign \core_calculate_stage_4_op__output_carry 1'0 + assign \core_calculate_stage_4_op__is_32bit 1'0 + assign \core_calculate_stage_4_op__is_signed 1'0 + assign \core_calculate_stage_4_op__data_len 4'0000 + assign \core_calculate_stage_4_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_4_op__insn \core_calculate_stage_4_op__data_len \core_calculate_stage_4_op__is_signed \core_calculate_stage_4_op__is_32bit \core_calculate_stage_4_op__output_carry { \core_calculate_stage_4_op__write_cr__ok \core_calculate_stage_4_op__write_cr__data } \core_calculate_stage_4_op__invert_out \core_calculate_stage_4_op__input_carry \core_calculate_stage_4_op__zero_a \core_calculate_stage_4_op__invert_a { \core_calculate_stage_4_op__oe__oe_ok \core_calculate_stage_4_op__oe__oe } { \core_calculate_stage_4_op__rc__rc_ok \core_calculate_stage_4_op__rc__rc } \core_calculate_stage_4_op__lk { \core_calculate_stage_4_op__imm_data__imm_ok \core_calculate_stage_4_op__imm_data__imm } \core_calculate_stage_4_op__fn_unit \core_calculate_stage_4_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \core_calculate_stage_4_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_ra \ra + sync init + end + process $group_22 + assign \core_calculate_stage_4_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_rb \rb + sync init + end + process $group_23 + assign \core_calculate_stage_4_xer_so 1'0 + assign \core_calculate_stage_4_xer_so \xer_so + sync init + end + process $group_24 + assign \core_calculate_stage_4_divisor_neg 1'0 + assign \core_calculate_stage_4_divisor_neg \divisor_neg + sync init + end + process $group_25 + assign \core_calculate_stage_4_dividend_neg 1'0 + assign \core_calculate_stage_4_dividend_neg \dividend_neg + sync init + end + process $group_26 + assign \core_calculate_stage_4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_calculate_stage_4_operation 2'00 + assign \core_calculate_stage_4_operation \operation + sync init + end + process $group_28 + assign \core_calculate_stage_4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_calculate_stage_4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_calculate_stage_4_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_calculate_stage_4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_4_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \core_calculate_stage_5_muxid 2'00 + assign \core_calculate_stage_5_muxid \core_calculate_stage_4_muxid$33 + sync init + end + process $group_33 + assign \core_calculate_stage_5_op__insn_type 7'0000000 + assign \core_calculate_stage_5_op__fn_unit 10'0000000000 + assign \core_calculate_stage_5_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_5_op__lk 1'0 + assign \core_calculate_stage_5_op__rc__rc 1'0 + assign \core_calculate_stage_5_op__rc__rc_ok 1'0 + assign \core_calculate_stage_5_op__oe__oe 1'0 + assign \core_calculate_stage_5_op__oe__oe_ok 1'0 + assign \core_calculate_stage_5_op__invert_a 1'0 + assign \core_calculate_stage_5_op__zero_a 1'0 + assign \core_calculate_stage_5_op__input_carry 2'00 + assign \core_calculate_stage_5_op__invert_out 1'0 + assign \core_calculate_stage_5_op__write_cr__data 3'000 + assign \core_calculate_stage_5_op__write_cr__ok 1'0 + assign \core_calculate_stage_5_op__output_carry 1'0 + assign \core_calculate_stage_5_op__is_32bit 1'0 + assign \core_calculate_stage_5_op__is_signed 1'0 + assign \core_calculate_stage_5_op__data_len 4'0000 + assign \core_calculate_stage_5_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_5_op__insn \core_calculate_stage_5_op__data_len \core_calculate_stage_5_op__is_signed \core_calculate_stage_5_op__is_32bit \core_calculate_stage_5_op__output_carry { \core_calculate_stage_5_op__write_cr__ok \core_calculate_stage_5_op__write_cr__data } \core_calculate_stage_5_op__invert_out \core_calculate_stage_5_op__input_carry \core_calculate_stage_5_op__zero_a \core_calculate_stage_5_op__invert_a { \core_calculate_stage_5_op__oe__oe_ok \core_calculate_stage_5_op__oe__oe } { \core_calculate_stage_5_op__rc__rc_ok \core_calculate_stage_5_op__rc__rc } \core_calculate_stage_5_op__lk { \core_calculate_stage_5_op__imm_data__imm_ok \core_calculate_stage_5_op__imm_data__imm } \core_calculate_stage_5_op__fn_unit \core_calculate_stage_5_op__insn_type } { \core_calculate_stage_4_op__insn$53 \core_calculate_stage_4_op__data_len$52 \core_calculate_stage_4_op__is_signed$51 \core_calculate_stage_4_op__is_32bit$50 \core_calculate_stage_4_op__output_carry$49 { \core_calculate_stage_4_op__write_cr__ok$48 \core_calculate_stage_4_op__write_cr__data$47 } \core_calculate_stage_4_op__invert_out$46 \core_calculate_stage_4_op__input_carry$45 \core_calculate_stage_4_op__zero_a$44 \core_calculate_stage_4_op__invert_a$43 { \core_calculate_stage_4_op__oe__oe_ok$42 \core_calculate_stage_4_op__oe__oe$41 } { \core_calculate_stage_4_op__rc__rc_ok$40 \core_calculate_stage_4_op__rc__rc$39 } \core_calculate_stage_4_op__lk$38 { \core_calculate_stage_4_op__imm_data__imm_ok$37 \core_calculate_stage_4_op__imm_data__imm$36 } \core_calculate_stage_4_op__fn_unit$35 \core_calculate_stage_4_op__insn_type$34 } + sync init + end + process $group_53 + assign \core_calculate_stage_5_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_ra \core_calculate_stage_4_ra$54 + sync init + end + process $group_54 + assign \core_calculate_stage_5_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_rb \core_calculate_stage_4_rb$55 + sync init + end + process $group_55 + assign \core_calculate_stage_5_xer_so 1'0 + assign \core_calculate_stage_5_xer_so \core_calculate_stage_4_xer_so$56 + sync init + end + process $group_56 + assign \core_calculate_stage_5_divisor_neg 1'0 + assign \core_calculate_stage_5_divisor_neg \core_calculate_stage_4_divisor_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_5_dividend_neg 1'0 + assign \core_calculate_stage_5_dividend_neg \core_calculate_stage_4_dividend_neg$58 + sync init + end + process $group_58 + assign \core_calculate_stage_5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_divisor_radicand \core_calculate_stage_4_divisor_radicand$59 + sync init + end + process $group_59 + assign \core_calculate_stage_5_operation 2'00 + assign \core_calculate_stage_5_operation \core_calculate_stage_4_operation$60 + sync init + end + process $group_60 + assign \core_calculate_stage_5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_quotient_root \core_calculate_stage_4_quotient_root$61 + sync init + end + process $group_61 + assign \core_calculate_stage_5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_root_times_radicand \core_calculate_stage_4_root_times_radicand$62 + sync init + end + process $group_62 + assign \core_calculate_stage_5_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_compare_lhs \core_calculate_stage_4_compare_lhs$63 + sync init + end + process $group_63 + assign \core_calculate_stage_5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_5_compare_rhs \core_calculate_stage_4_compare_rhs$64 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$97 + process $group_64 + assign \p_valid_i$97 1'0 + assign \p_valid_i$97 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_65 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $98 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$97 + connect \B \p_ready_o + connect \Y $98 + end + process $group_66 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $98 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$100 + process $group_67 + assign \muxid$100 2'00 + assign \muxid$100 \core_calculate_stage_5_muxid$65 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$111 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$120 + process $group_68 + assign \op__insn_type$101 7'0000000 + assign \op__fn_unit$102 10'0000000000 + assign \op__imm_data__imm$103 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$104 1'0 + assign \op__lk$105 1'0 + assign \op__rc__rc$106 1'0 + assign \op__rc__rc_ok$107 1'0 + assign \op__oe__oe$108 1'0 + assign \op__oe__oe_ok$109 1'0 + assign \op__invert_a$110 1'0 + assign \op__zero_a$111 1'0 + assign \op__input_carry$112 2'00 + assign \op__invert_out$113 1'0 + assign \op__write_cr__data$114 3'000 + assign \op__write_cr__ok$115 1'0 + assign \op__output_carry$116 1'0 + assign \op__is_32bit$117 1'0 + assign \op__is_signed$118 1'0 + assign \op__data_len$119 4'0000 + assign \op__insn$120 32'00000000000000000000000000000000 + assign { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } { \core_calculate_stage_5_op__insn$85 \core_calculate_stage_5_op__data_len$84 \core_calculate_stage_5_op__is_signed$83 \core_calculate_stage_5_op__is_32bit$82 \core_calculate_stage_5_op__output_carry$81 { \core_calculate_stage_5_op__write_cr__ok$80 \core_calculate_stage_5_op__write_cr__data$79 } \core_calculate_stage_5_op__invert_out$78 \core_calculate_stage_5_op__input_carry$77 \core_calculate_stage_5_op__zero_a$76 \core_calculate_stage_5_op__invert_a$75 { \core_calculate_stage_5_op__oe__oe_ok$74 \core_calculate_stage_5_op__oe__oe$73 } { \core_calculate_stage_5_op__rc__rc_ok$72 \core_calculate_stage_5_op__rc__rc$71 } \core_calculate_stage_5_op__lk$70 { \core_calculate_stage_5_op__imm_data__imm_ok$69 \core_calculate_stage_5_op__imm_data__imm$68 } \core_calculate_stage_5_op__fn_unit$67 \core_calculate_stage_5_op__insn_type$66 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$121 + process $group_88 + assign \ra$121 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$121 \core_calculate_stage_5_ra$86 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$122 + process $group_89 + assign \rb$122 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$122 \core_calculate_stage_5_rb$87 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$123 + process $group_90 + assign \xer_so$123 1'0 + assign \xer_so$123 \core_calculate_stage_5_xer_so$88 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$124 + process $group_91 + assign \divisor_neg$124 1'0 + assign \divisor_neg$124 \core_calculate_stage_5_divisor_neg$89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$125 + process $group_92 + assign \dividend_neg$125 1'0 + assign \dividend_neg$125 \core_calculate_stage_5_dividend_neg$90 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$126 + process $group_93 + assign \divisor_radicand$126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$126 \core_calculate_stage_5_divisor_radicand$91 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$127 + process $group_94 + assign \operation$127 2'00 + assign \operation$127 \core_calculate_stage_5_operation$92 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$128 + process $group_95 + assign \quotient_root$128 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$128 \core_calculate_stage_5_quotient_root$93 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$129 + process $group_96 + assign \root_times_radicand$129 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$129 \core_calculate_stage_5_root_times_radicand$94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$130 + process $group_97 + assign \compare_lhs$130 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$130 \core_calculate_stage_5_compare_lhs$95 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$131 + process $group_98 + assign \compare_rhs$131 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$131 \core_calculate_stage_5_compare_rhs$96 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_99 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_100 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$100 + end + sync init + update \muxid$1 2'00 + sync posedge \clk + update \muxid$1 \muxid$1$next + end + process $group_101 + assign \op__insn_type$2$next \op__insn_type$2 + assign \op__fn_unit$3$next \op__fn_unit$3 + assign \op__imm_data__imm$4$next \op__imm_data__imm$4 + assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5 + assign \op__lk$6$next \op__lk$6 + assign \op__rc__rc$7$next \op__rc__rc$7 + assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8 + assign \op__oe__oe$9$next \op__oe__oe$9 + assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10 + assign \op__invert_a$11$next \op__invert_a$11 + assign \op__zero_a$12$next \op__zero_a$12 + assign \op__input_carry$13$next \op__input_carry$13 + assign \op__invert_out$14$next \op__invert_out$14 + assign \op__write_cr__data$15$next \op__write_cr__data$15 + assign \op__write_cr__ok$16$next \op__write_cr__ok$16 + assign \op__output_carry$17$next \op__output_carry$17 + assign \op__is_32bit$18$next \op__is_32bit$18 + assign \op__is_signed$19$next \op__is_signed$19 + assign \op__data_len$20$next \op__data_len$20 + assign \op__insn$21$next \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5$next 1'0 + assign \op__rc__rc$7$next 1'0 + assign \op__rc__rc_ok$8$next 1'0 + assign \op__oe__oe$9$next 1'0 + assign \op__oe__oe_ok$10$next 1'0 + assign \op__write_cr__data$15$next 3'000 + assign \op__write_cr__ok$16$next 1'0 + assign \op__insn$21$next 32'00000000000000000000000000000000 + end + sync init + update \op__insn_type$2 7'0000000 + update \op__fn_unit$3 10'0000000000 + update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \op__imm_data__imm_ok$5 1'0 + update \op__lk$6 1'0 + update \op__rc__rc$7 1'0 + update \op__rc__rc_ok$8 1'0 + update \op__oe__oe$9 1'0 + update \op__oe__oe_ok$10 1'0 + update \op__invert_a$11 1'0 + update \op__zero_a$12 1'0 + update \op__input_carry$13 2'00 + update \op__invert_out$14 1'0 + update \op__write_cr__data$15 3'000 + update \op__write_cr__ok$16 1'0 + update \op__output_carry$17 1'0 + update \op__is_32bit$18 1'0 + update \op__is_signed$19 1'0 + update \op__data_len$20 4'0000 + update \op__insn$21 32'00000000000000000000000000000000 + sync posedge \clk + update \op__insn_type$2 \op__insn_type$2$next + update \op__fn_unit$3 \op__fn_unit$3$next + update \op__imm_data__imm$4 \op__imm_data__imm$4$next + update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next + update \op__lk$6 \op__lk$6$next + update \op__rc__rc$7 \op__rc__rc$7$next + update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next + update \op__oe__oe$9 \op__oe__oe$9$next + update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next + update \op__invert_a$11 \op__invert_a$11$next + update \op__zero_a$12 \op__zero_a$12$next + update \op__input_carry$13 \op__input_carry$13$next + update \op__invert_out$14 \op__invert_out$14$next + update \op__write_cr__data$15 \op__write_cr__data$15$next + update \op__write_cr__ok$16 \op__write_cr__ok$16$next + update \op__output_carry$17 \op__output_carry$17$next + update \op__is_32bit$18 \op__is_32bit$18$next + update \op__is_signed$19 \op__is_signed$19$next + update \op__data_len$20 \op__data_len$20$next + update \op__insn$21 \op__insn$21$next + end + process $group_121 + assign \ra$22$next \ra$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$22$next \ra$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$22$next \ra$121 + end + sync init + update \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \ra$22 \ra$22$next + end + process $group_122 + assign \rb$23$next \rb$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$23$next \rb$122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$23$next \rb$122 + end + sync init + update \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \rb$23 \rb$23$next + end + process $group_123 + assign \xer_so$24$next \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$24$next \xer_so$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$24$next \xer_so$123 + end + sync init + update \xer_so$24 1'0 + sync posedge \clk + update \xer_so$24 \xer_so$24$next + end + process $group_124 + assign \divisor_neg$25$next \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$25$next \divisor_neg$124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$25$next \divisor_neg$124 + end + sync init + update \divisor_neg$25 1'0 + sync posedge \clk + update \divisor_neg$25 \divisor_neg$25$next + end + process $group_125 + assign \dividend_neg$26$next \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$26$next \dividend_neg$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$26$next \dividend_neg$125 + end + sync init + update \dividend_neg$26 1'0 + sync posedge \clk + update \dividend_neg$26 \dividend_neg$26$next + end + process $group_126 + assign \divisor_radicand$27$next \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$27$next \divisor_radicand$126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$27$next \divisor_radicand$126 + end + sync init + update \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \divisor_radicand$27 \divisor_radicand$27$next + end + process $group_127 + assign \operation$28$next \operation$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$28$next \operation$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$28$next \operation$127 + end + sync init + update \operation$28 2'00 + sync posedge \clk + update \operation$28 \operation$28$next + end + process $group_128 + assign \quotient_root$29$next \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$29$next \quotient_root$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$29$next \quotient_root$128 + end + sync init + update \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \quotient_root$29 \quotient_root$29$next + end + process $group_129 + assign \root_times_radicand$30$next \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$30$next \root_times_radicand$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$30$next \root_times_radicand$129 + end + sync init + update \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \root_times_radicand$30 \root_times_radicand$30$next + end + process $group_130 + assign \compare_lhs$31$next \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$31$next \compare_lhs$130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$31$next \compare_lhs$130 + end + sync init + update \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_lhs$31 \compare_lhs$31$next + end + process $group_131 + assign \compare_rhs$32$next \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$32$next \compare_rhs$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$32$next \compare_rhs$131 + end + sync init + update \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_rhs$32 \compare_rhs$32$next + end + process $group_132 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_133 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.p" +module \p$109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.n" +module \n$110 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_6.core.trial0" +module \trial0$112 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000000 + connect \B 8'10010110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_6.core.trial1" +module \trial1$113 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000001 + connect \B 8'10010110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_6.core.trial2" +module \trial2$114 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000100 + connect \B 8'10010110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_6.core.trial3" +module \trial3$115 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'001001 + connect \B 8'10010110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_6.core.trial4" +module \trial4$116 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'010000 + connect \B 8'10010110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_6.core.trial5" +module \trial5$117 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'011001 + connect \B 8'10010110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_6.core.trial6" +module \trial6$118 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'100100 + connect \B 8'10010110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_6.core.trial7" +module \trial7$119 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'110001 + connect \B 8'10010110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_6.core.pe" +module \pe$120 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_6.core" +module \core$111 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$112 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$113 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$114 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$115 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$116 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$117 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$118 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$119 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$120 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 66 + connect \A \next_bits + connect \B 6'101011 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 66 + connect \A \quotient_root + connect \B $31 + connect \Y $33 + end + connect $30 $33 + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $30 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 130 $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 130 + connect \A $36 + connect \B 6'101011 + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 130 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B $38 + connect \Y $40 + end + connect $35 $40 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $35 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_6" +module \core_calculate_stage_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$111 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_7.core.trial0" +module \trial0$122 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000000 + connect \B 8'10010000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_7.core.trial1" +module \trial1$123 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000001 + connect \B 8'10010000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_7.core.trial2" +module \trial2$124 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000100 + connect \B 8'10010000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_7.core.trial3" +module \trial3$125 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'001001 + connect \B 8'10010000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_7.core.trial4" +module \trial4$126 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'010000 + connect \B 8'10010000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_7.core.trial5" +module \trial5$127 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'011001 + connect \B 8'10010000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_7.core.trial6" +module \trial6$128 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'100100 + connect \B 8'10010000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_7.core.trial7" +module \trial7$129 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1101000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1101001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'110001 + connect \B 8'10010000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'101001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1010000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_7.core.pe" +module \pe$130 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_7.core" +module \core$121 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$122 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$123 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$124 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$125 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$126 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$127 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$128 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$129 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$130 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 66 + connect \A \next_bits + connect \B 6'101000 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 66 + connect \A \quotient_root + connect \B $31 + connect \Y $33 + end + connect $30 $33 + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $30 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 130 $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 130 + connect \A $36 + connect \B 6'101000 + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 130 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B $38 + connect \Y $40 + end + connect $35 $40 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $35 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8.core_calculate_stage_7" +module \core_calculate_stage_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$121 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_6_to_8" +module \pipe_6_to_8 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 4 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 5 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 7 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 16 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 18 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 20 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 21 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 22 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 23 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 24 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 25 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 26 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 28 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 29 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 30 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 31 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 32 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 33 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 34 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 35 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 36 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 37 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 38 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$1$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 39 \op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 40 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 41 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 46 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 50 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 51 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 52 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 53 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 54 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 55 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 56 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 57 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 58 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 59 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 60 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 61 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 62 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 63 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$26$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 64 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 65 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 66 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 67 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 68 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 69 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$32$next + cell \p$109 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$110 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_6_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_6_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_6_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_6_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_6_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_6_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_6_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_6_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_6_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_6_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_6_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_6_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_6_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_6_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_6_muxid$33 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_6_op__insn_type$34 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_6_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_6_op__imm_data__imm$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__imm_data__imm_ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__lk$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__invert_a$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_6_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_6_op__write_cr__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__write_cr__ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__output_carry$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__is_32bit$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_6_op__is_signed$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_6_op__data_len$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_6_op__insn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_6_ra$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_6_rb$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_6_xer_so$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_6_divisor_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_6_dividend_neg$58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_6_divisor_radicand$59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_6_operation$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_6_quotient_root$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_6_root_times_radicand$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_6_compare_lhs$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_6_compare_rhs$64 + cell \core_calculate_stage_6 \core_calculate_stage_6 + connect \muxid \core_calculate_stage_6_muxid + connect \op__insn_type \core_calculate_stage_6_op__insn_type + connect \op__fn_unit \core_calculate_stage_6_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_6_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_6_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_6_op__lk + connect \op__rc__rc \core_calculate_stage_6_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_6_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_6_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_6_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_6_op__invert_a + connect \op__zero_a \core_calculate_stage_6_op__zero_a + connect \op__input_carry \core_calculate_stage_6_op__input_carry + connect \op__invert_out \core_calculate_stage_6_op__invert_out + connect \op__write_cr__data \core_calculate_stage_6_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_6_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_6_op__output_carry + connect \op__is_32bit \core_calculate_stage_6_op__is_32bit + connect \op__is_signed \core_calculate_stage_6_op__is_signed + connect \op__data_len \core_calculate_stage_6_op__data_len + connect \op__insn \core_calculate_stage_6_op__insn + connect \ra \core_calculate_stage_6_ra + connect \rb \core_calculate_stage_6_rb + connect \xer_so \core_calculate_stage_6_xer_so + connect \divisor_neg \core_calculate_stage_6_divisor_neg + connect \dividend_neg \core_calculate_stage_6_dividend_neg + connect \divisor_radicand \core_calculate_stage_6_divisor_radicand + connect \operation \core_calculate_stage_6_operation + connect \quotient_root \core_calculate_stage_6_quotient_root + connect \root_times_radicand \core_calculate_stage_6_root_times_radicand + connect \compare_lhs \core_calculate_stage_6_compare_lhs + connect \compare_rhs \core_calculate_stage_6_compare_rhs + connect \muxid$1 \core_calculate_stage_6_muxid$33 + connect \op__insn_type$2 \core_calculate_stage_6_op__insn_type$34 + connect \op__fn_unit$3 \core_calculate_stage_6_op__fn_unit$35 + connect \op__imm_data__imm$4 \core_calculate_stage_6_op__imm_data__imm$36 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_6_op__imm_data__imm_ok$37 + connect \op__lk$6 \core_calculate_stage_6_op__lk$38 + connect \op__rc__rc$7 \core_calculate_stage_6_op__rc__rc$39 + connect \op__rc__rc_ok$8 \core_calculate_stage_6_op__rc__rc_ok$40 + connect \op__oe__oe$9 \core_calculate_stage_6_op__oe__oe$41 + connect \op__oe__oe_ok$10 \core_calculate_stage_6_op__oe__oe_ok$42 + connect \op__invert_a$11 \core_calculate_stage_6_op__invert_a$43 + connect \op__zero_a$12 \core_calculate_stage_6_op__zero_a$44 + connect \op__input_carry$13 \core_calculate_stage_6_op__input_carry$45 + connect \op__invert_out$14 \core_calculate_stage_6_op__invert_out$46 + connect \op__write_cr__data$15 \core_calculate_stage_6_op__write_cr__data$47 + connect \op__write_cr__ok$16 \core_calculate_stage_6_op__write_cr__ok$48 + connect \op__output_carry$17 \core_calculate_stage_6_op__output_carry$49 + connect \op__is_32bit$18 \core_calculate_stage_6_op__is_32bit$50 + connect \op__is_signed$19 \core_calculate_stage_6_op__is_signed$51 + connect \op__data_len$20 \core_calculate_stage_6_op__data_len$52 + connect \op__insn$21 \core_calculate_stage_6_op__insn$53 + connect \ra$22 \core_calculate_stage_6_ra$54 + connect \rb$23 \core_calculate_stage_6_rb$55 + connect \xer_so$24 \core_calculate_stage_6_xer_so$56 + connect \divisor_neg$25 \core_calculate_stage_6_divisor_neg$57 + connect \dividend_neg$26 \core_calculate_stage_6_dividend_neg$58 + connect \divisor_radicand$27 \core_calculate_stage_6_divisor_radicand$59 + connect \operation$28 \core_calculate_stage_6_operation$60 + connect \quotient_root$29 \core_calculate_stage_6_quotient_root$61 + connect \root_times_radicand$30 \core_calculate_stage_6_root_times_radicand$62 + connect \compare_lhs$31 \core_calculate_stage_6_compare_lhs$63 + connect \compare_rhs$32 \core_calculate_stage_6_compare_rhs$64 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_7_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_7_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_7_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_7_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_7_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_7_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_7_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_7_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_7_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_7_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_7_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_7_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_7_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_7_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_7_muxid$65 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_7_op__insn_type$66 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_7_op__fn_unit$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_7_op__imm_data__imm$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__imm_data__imm_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__lk$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__rc__rc_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__oe__oe_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__invert_a$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__zero_a$76 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_7_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_7_op__write_cr__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__write_cr__ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_7_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_7_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_7_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_7_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_7_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_7_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_7_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_7_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_7_divisor_radicand$91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_7_operation$92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_7_quotient_root$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_7_root_times_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_7_compare_lhs$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_7_compare_rhs$96 + cell \core_calculate_stage_7 \core_calculate_stage_7 + connect \muxid \core_calculate_stage_7_muxid + connect \op__insn_type \core_calculate_stage_7_op__insn_type + connect \op__fn_unit \core_calculate_stage_7_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_7_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_7_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_7_op__lk + connect \op__rc__rc \core_calculate_stage_7_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_7_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_7_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_7_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_7_op__invert_a + connect \op__zero_a \core_calculate_stage_7_op__zero_a + connect \op__input_carry \core_calculate_stage_7_op__input_carry + connect \op__invert_out \core_calculate_stage_7_op__invert_out + connect \op__write_cr__data \core_calculate_stage_7_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_7_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_7_op__output_carry + connect \op__is_32bit \core_calculate_stage_7_op__is_32bit + connect \op__is_signed \core_calculate_stage_7_op__is_signed + connect \op__data_len \core_calculate_stage_7_op__data_len + connect \op__insn \core_calculate_stage_7_op__insn + connect \ra \core_calculate_stage_7_ra + connect \rb \core_calculate_stage_7_rb + connect \xer_so \core_calculate_stage_7_xer_so + connect \divisor_neg \core_calculate_stage_7_divisor_neg + connect \dividend_neg \core_calculate_stage_7_dividend_neg + connect \divisor_radicand \core_calculate_stage_7_divisor_radicand + connect \operation \core_calculate_stage_7_operation + connect \quotient_root \core_calculate_stage_7_quotient_root + connect \root_times_radicand \core_calculate_stage_7_root_times_radicand + connect \compare_lhs \core_calculate_stage_7_compare_lhs + connect \compare_rhs \core_calculate_stage_7_compare_rhs + connect \muxid$1 \core_calculate_stage_7_muxid$65 + connect \op__insn_type$2 \core_calculate_stage_7_op__insn_type$66 + connect \op__fn_unit$3 \core_calculate_stage_7_op__fn_unit$67 + connect \op__imm_data__imm$4 \core_calculate_stage_7_op__imm_data__imm$68 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_7_op__imm_data__imm_ok$69 + connect \op__lk$6 \core_calculate_stage_7_op__lk$70 + connect \op__rc__rc$7 \core_calculate_stage_7_op__rc__rc$71 + connect \op__rc__rc_ok$8 \core_calculate_stage_7_op__rc__rc_ok$72 + connect \op__oe__oe$9 \core_calculate_stage_7_op__oe__oe$73 + connect \op__oe__oe_ok$10 \core_calculate_stage_7_op__oe__oe_ok$74 + connect \op__invert_a$11 \core_calculate_stage_7_op__invert_a$75 + connect \op__zero_a$12 \core_calculate_stage_7_op__zero_a$76 + connect \op__input_carry$13 \core_calculate_stage_7_op__input_carry$77 + connect \op__invert_out$14 \core_calculate_stage_7_op__invert_out$78 + connect \op__write_cr__data$15 \core_calculate_stage_7_op__write_cr__data$79 + connect \op__write_cr__ok$16 \core_calculate_stage_7_op__write_cr__ok$80 + connect \op__output_carry$17 \core_calculate_stage_7_op__output_carry$81 + connect \op__is_32bit$18 \core_calculate_stage_7_op__is_32bit$82 + connect \op__is_signed$19 \core_calculate_stage_7_op__is_signed$83 + connect \op__data_len$20 \core_calculate_stage_7_op__data_len$84 + connect \op__insn$21 \core_calculate_stage_7_op__insn$85 + connect \ra$22 \core_calculate_stage_7_ra$86 + connect \rb$23 \core_calculate_stage_7_rb$87 + connect \xer_so$24 \core_calculate_stage_7_xer_so$88 + connect \divisor_neg$25 \core_calculate_stage_7_divisor_neg$89 + connect \dividend_neg$26 \core_calculate_stage_7_dividend_neg$90 + connect \divisor_radicand$27 \core_calculate_stage_7_divisor_radicand$91 + connect \operation$28 \core_calculate_stage_7_operation$92 + connect \quotient_root$29 \core_calculate_stage_7_quotient_root$93 + connect \root_times_radicand$30 \core_calculate_stage_7_root_times_radicand$94 + connect \compare_lhs$31 \core_calculate_stage_7_compare_lhs$95 + connect \compare_rhs$32 \core_calculate_stage_7_compare_rhs$96 + end + process $group_0 + assign \core_calculate_stage_6_muxid 2'00 + assign \core_calculate_stage_6_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_6_op__insn_type 7'0000000 + assign \core_calculate_stage_6_op__fn_unit 10'0000000000 + assign \core_calculate_stage_6_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_6_op__lk 1'0 + assign \core_calculate_stage_6_op__rc__rc 1'0 + assign \core_calculate_stage_6_op__rc__rc_ok 1'0 + assign \core_calculate_stage_6_op__oe__oe 1'0 + assign \core_calculate_stage_6_op__oe__oe_ok 1'0 + assign \core_calculate_stage_6_op__invert_a 1'0 + assign \core_calculate_stage_6_op__zero_a 1'0 + assign \core_calculate_stage_6_op__input_carry 2'00 + assign \core_calculate_stage_6_op__invert_out 1'0 + assign \core_calculate_stage_6_op__write_cr__data 3'000 + assign \core_calculate_stage_6_op__write_cr__ok 1'0 + assign \core_calculate_stage_6_op__output_carry 1'0 + assign \core_calculate_stage_6_op__is_32bit 1'0 + assign \core_calculate_stage_6_op__is_signed 1'0 + assign \core_calculate_stage_6_op__data_len 4'0000 + assign \core_calculate_stage_6_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_6_op__insn \core_calculate_stage_6_op__data_len \core_calculate_stage_6_op__is_signed \core_calculate_stage_6_op__is_32bit \core_calculate_stage_6_op__output_carry { \core_calculate_stage_6_op__write_cr__ok \core_calculate_stage_6_op__write_cr__data } \core_calculate_stage_6_op__invert_out \core_calculate_stage_6_op__input_carry \core_calculate_stage_6_op__zero_a \core_calculate_stage_6_op__invert_a { \core_calculate_stage_6_op__oe__oe_ok \core_calculate_stage_6_op__oe__oe } { \core_calculate_stage_6_op__rc__rc_ok \core_calculate_stage_6_op__rc__rc } \core_calculate_stage_6_op__lk { \core_calculate_stage_6_op__imm_data__imm_ok \core_calculate_stage_6_op__imm_data__imm } \core_calculate_stage_6_op__fn_unit \core_calculate_stage_6_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \core_calculate_stage_6_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_ra \ra + sync init + end + process $group_22 + assign \core_calculate_stage_6_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_rb \rb + sync init + end + process $group_23 + assign \core_calculate_stage_6_xer_so 1'0 + assign \core_calculate_stage_6_xer_so \xer_so + sync init + end + process $group_24 + assign \core_calculate_stage_6_divisor_neg 1'0 + assign \core_calculate_stage_6_divisor_neg \divisor_neg + sync init + end + process $group_25 + assign \core_calculate_stage_6_dividend_neg 1'0 + assign \core_calculate_stage_6_dividend_neg \dividend_neg + sync init + end + process $group_26 + assign \core_calculate_stage_6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_calculate_stage_6_operation 2'00 + assign \core_calculate_stage_6_operation \operation + sync init + end + process $group_28 + assign \core_calculate_stage_6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_calculate_stage_6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_calculate_stage_6_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_calculate_stage_6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_6_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \core_calculate_stage_7_muxid 2'00 + assign \core_calculate_stage_7_muxid \core_calculate_stage_6_muxid$33 + sync init + end + process $group_33 + assign \core_calculate_stage_7_op__insn_type 7'0000000 + assign \core_calculate_stage_7_op__fn_unit 10'0000000000 + assign \core_calculate_stage_7_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_7_op__lk 1'0 + assign \core_calculate_stage_7_op__rc__rc 1'0 + assign \core_calculate_stage_7_op__rc__rc_ok 1'0 + assign \core_calculate_stage_7_op__oe__oe 1'0 + assign \core_calculate_stage_7_op__oe__oe_ok 1'0 + assign \core_calculate_stage_7_op__invert_a 1'0 + assign \core_calculate_stage_7_op__zero_a 1'0 + assign \core_calculate_stage_7_op__input_carry 2'00 + assign \core_calculate_stage_7_op__invert_out 1'0 + assign \core_calculate_stage_7_op__write_cr__data 3'000 + assign \core_calculate_stage_7_op__write_cr__ok 1'0 + assign \core_calculate_stage_7_op__output_carry 1'0 + assign \core_calculate_stage_7_op__is_32bit 1'0 + assign \core_calculate_stage_7_op__is_signed 1'0 + assign \core_calculate_stage_7_op__data_len 4'0000 + assign \core_calculate_stage_7_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_7_op__insn \core_calculate_stage_7_op__data_len \core_calculate_stage_7_op__is_signed \core_calculate_stage_7_op__is_32bit \core_calculate_stage_7_op__output_carry { \core_calculate_stage_7_op__write_cr__ok \core_calculate_stage_7_op__write_cr__data } \core_calculate_stage_7_op__invert_out \core_calculate_stage_7_op__input_carry \core_calculate_stage_7_op__zero_a \core_calculate_stage_7_op__invert_a { \core_calculate_stage_7_op__oe__oe_ok \core_calculate_stage_7_op__oe__oe } { \core_calculate_stage_7_op__rc__rc_ok \core_calculate_stage_7_op__rc__rc } \core_calculate_stage_7_op__lk { \core_calculate_stage_7_op__imm_data__imm_ok \core_calculate_stage_7_op__imm_data__imm } \core_calculate_stage_7_op__fn_unit \core_calculate_stage_7_op__insn_type } { \core_calculate_stage_6_op__insn$53 \core_calculate_stage_6_op__data_len$52 \core_calculate_stage_6_op__is_signed$51 \core_calculate_stage_6_op__is_32bit$50 \core_calculate_stage_6_op__output_carry$49 { \core_calculate_stage_6_op__write_cr__ok$48 \core_calculate_stage_6_op__write_cr__data$47 } \core_calculate_stage_6_op__invert_out$46 \core_calculate_stage_6_op__input_carry$45 \core_calculate_stage_6_op__zero_a$44 \core_calculate_stage_6_op__invert_a$43 { \core_calculate_stage_6_op__oe__oe_ok$42 \core_calculate_stage_6_op__oe__oe$41 } { \core_calculate_stage_6_op__rc__rc_ok$40 \core_calculate_stage_6_op__rc__rc$39 } \core_calculate_stage_6_op__lk$38 { \core_calculate_stage_6_op__imm_data__imm_ok$37 \core_calculate_stage_6_op__imm_data__imm$36 } \core_calculate_stage_6_op__fn_unit$35 \core_calculate_stage_6_op__insn_type$34 } + sync init + end + process $group_53 + assign \core_calculate_stage_7_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_ra \core_calculate_stage_6_ra$54 + sync init + end + process $group_54 + assign \core_calculate_stage_7_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_rb \core_calculate_stage_6_rb$55 + sync init + end + process $group_55 + assign \core_calculate_stage_7_xer_so 1'0 + assign \core_calculate_stage_7_xer_so \core_calculate_stage_6_xer_so$56 + sync init + end + process $group_56 + assign \core_calculate_stage_7_divisor_neg 1'0 + assign \core_calculate_stage_7_divisor_neg \core_calculate_stage_6_divisor_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_7_dividend_neg 1'0 + assign \core_calculate_stage_7_dividend_neg \core_calculate_stage_6_dividend_neg$58 + sync init + end + process $group_58 + assign \core_calculate_stage_7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_divisor_radicand \core_calculate_stage_6_divisor_radicand$59 + sync init + end + process $group_59 + assign \core_calculate_stage_7_operation 2'00 + assign \core_calculate_stage_7_operation \core_calculate_stage_6_operation$60 + sync init + end + process $group_60 + assign \core_calculate_stage_7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_quotient_root \core_calculate_stage_6_quotient_root$61 + sync init + end + process $group_61 + assign \core_calculate_stage_7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_root_times_radicand \core_calculate_stage_6_root_times_radicand$62 + sync init + end + process $group_62 + assign \core_calculate_stage_7_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_compare_lhs \core_calculate_stage_6_compare_lhs$63 + sync init + end + process $group_63 + assign \core_calculate_stage_7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_7_compare_rhs \core_calculate_stage_6_compare_rhs$64 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$97 + process $group_64 + assign \p_valid_i$97 1'0 + assign \p_valid_i$97 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_65 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $98 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$97 + connect \B \p_ready_o + connect \Y $98 + end + process $group_66 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $98 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$100 + process $group_67 + assign \muxid$100 2'00 + assign \muxid$100 \core_calculate_stage_7_muxid$65 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$111 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$120 + process $group_68 + assign \op__insn_type$101 7'0000000 + assign \op__fn_unit$102 10'0000000000 + assign \op__imm_data__imm$103 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$104 1'0 + assign \op__lk$105 1'0 + assign \op__rc__rc$106 1'0 + assign \op__rc__rc_ok$107 1'0 + assign \op__oe__oe$108 1'0 + assign \op__oe__oe_ok$109 1'0 + assign \op__invert_a$110 1'0 + assign \op__zero_a$111 1'0 + assign \op__input_carry$112 2'00 + assign \op__invert_out$113 1'0 + assign \op__write_cr__data$114 3'000 + assign \op__write_cr__ok$115 1'0 + assign \op__output_carry$116 1'0 + assign \op__is_32bit$117 1'0 + assign \op__is_signed$118 1'0 + assign \op__data_len$119 4'0000 + assign \op__insn$120 32'00000000000000000000000000000000 + assign { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } { \core_calculate_stage_7_op__insn$85 \core_calculate_stage_7_op__data_len$84 \core_calculate_stage_7_op__is_signed$83 \core_calculate_stage_7_op__is_32bit$82 \core_calculate_stage_7_op__output_carry$81 { \core_calculate_stage_7_op__write_cr__ok$80 \core_calculate_stage_7_op__write_cr__data$79 } \core_calculate_stage_7_op__invert_out$78 \core_calculate_stage_7_op__input_carry$77 \core_calculate_stage_7_op__zero_a$76 \core_calculate_stage_7_op__invert_a$75 { \core_calculate_stage_7_op__oe__oe_ok$74 \core_calculate_stage_7_op__oe__oe$73 } { \core_calculate_stage_7_op__rc__rc_ok$72 \core_calculate_stage_7_op__rc__rc$71 } \core_calculate_stage_7_op__lk$70 { \core_calculate_stage_7_op__imm_data__imm_ok$69 \core_calculate_stage_7_op__imm_data__imm$68 } \core_calculate_stage_7_op__fn_unit$67 \core_calculate_stage_7_op__insn_type$66 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$121 + process $group_88 + assign \ra$121 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$121 \core_calculate_stage_7_ra$86 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$122 + process $group_89 + assign \rb$122 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$122 \core_calculate_stage_7_rb$87 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$123 + process $group_90 + assign \xer_so$123 1'0 + assign \xer_so$123 \core_calculate_stage_7_xer_so$88 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$124 + process $group_91 + assign \divisor_neg$124 1'0 + assign \divisor_neg$124 \core_calculate_stage_7_divisor_neg$89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$125 + process $group_92 + assign \dividend_neg$125 1'0 + assign \dividend_neg$125 \core_calculate_stage_7_dividend_neg$90 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$126 + process $group_93 + assign \divisor_radicand$126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$126 \core_calculate_stage_7_divisor_radicand$91 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$127 + process $group_94 + assign \operation$127 2'00 + assign \operation$127 \core_calculate_stage_7_operation$92 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$128 + process $group_95 + assign \quotient_root$128 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$128 \core_calculate_stage_7_quotient_root$93 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$129 + process $group_96 + assign \root_times_radicand$129 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$129 \core_calculate_stage_7_root_times_radicand$94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$130 + process $group_97 + assign \compare_lhs$130 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$130 \core_calculate_stage_7_compare_lhs$95 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$131 + process $group_98 + assign \compare_rhs$131 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$131 \core_calculate_stage_7_compare_rhs$96 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_99 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_100 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$100 + end + sync init + update \muxid$1 2'00 + sync posedge \clk + update \muxid$1 \muxid$1$next + end + process $group_101 + assign \op__insn_type$2$next \op__insn_type$2 + assign \op__fn_unit$3$next \op__fn_unit$3 + assign \op__imm_data__imm$4$next \op__imm_data__imm$4 + assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5 + assign \op__lk$6$next \op__lk$6 + assign \op__rc__rc$7$next \op__rc__rc$7 + assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8 + assign \op__oe__oe$9$next \op__oe__oe$9 + assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10 + assign \op__invert_a$11$next \op__invert_a$11 + assign \op__zero_a$12$next \op__zero_a$12 + assign \op__input_carry$13$next \op__input_carry$13 + assign \op__invert_out$14$next \op__invert_out$14 + assign \op__write_cr__data$15$next \op__write_cr__data$15 + assign \op__write_cr__ok$16$next \op__write_cr__ok$16 + assign \op__output_carry$17$next \op__output_carry$17 + assign \op__is_32bit$18$next \op__is_32bit$18 + assign \op__is_signed$19$next \op__is_signed$19 + assign \op__data_len$20$next \op__data_len$20 + assign \op__insn$21$next \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5$next 1'0 + assign \op__rc__rc$7$next 1'0 + assign \op__rc__rc_ok$8$next 1'0 + assign \op__oe__oe$9$next 1'0 + assign \op__oe__oe_ok$10$next 1'0 + assign \op__write_cr__data$15$next 3'000 + assign \op__write_cr__ok$16$next 1'0 + assign \op__insn$21$next 32'00000000000000000000000000000000 + end + sync init + update \op__insn_type$2 7'0000000 + update \op__fn_unit$3 10'0000000000 + update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \op__imm_data__imm_ok$5 1'0 + update \op__lk$6 1'0 + update \op__rc__rc$7 1'0 + update \op__rc__rc_ok$8 1'0 + update \op__oe__oe$9 1'0 + update \op__oe__oe_ok$10 1'0 + update \op__invert_a$11 1'0 + update \op__zero_a$12 1'0 + update \op__input_carry$13 2'00 + update \op__invert_out$14 1'0 + update \op__write_cr__data$15 3'000 + update \op__write_cr__ok$16 1'0 + update \op__output_carry$17 1'0 + update \op__is_32bit$18 1'0 + update \op__is_signed$19 1'0 + update \op__data_len$20 4'0000 + update \op__insn$21 32'00000000000000000000000000000000 + sync posedge \clk + update \op__insn_type$2 \op__insn_type$2$next + update \op__fn_unit$3 \op__fn_unit$3$next + update \op__imm_data__imm$4 \op__imm_data__imm$4$next + update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next + update \op__lk$6 \op__lk$6$next + update \op__rc__rc$7 \op__rc__rc$7$next + update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next + update \op__oe__oe$9 \op__oe__oe$9$next + update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next + update \op__invert_a$11 \op__invert_a$11$next + update \op__zero_a$12 \op__zero_a$12$next + update \op__input_carry$13 \op__input_carry$13$next + update \op__invert_out$14 \op__invert_out$14$next + update \op__write_cr__data$15 \op__write_cr__data$15$next + update \op__write_cr__ok$16 \op__write_cr__ok$16$next + update \op__output_carry$17 \op__output_carry$17$next + update \op__is_32bit$18 \op__is_32bit$18$next + update \op__is_signed$19 \op__is_signed$19$next + update \op__data_len$20 \op__data_len$20$next + update \op__insn$21 \op__insn$21$next + end + process $group_121 + assign \ra$22$next \ra$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$22$next \ra$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$22$next \ra$121 + end + sync init + update \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \ra$22 \ra$22$next + end + process $group_122 + assign \rb$23$next \rb$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$23$next \rb$122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$23$next \rb$122 + end + sync init + update \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \rb$23 \rb$23$next + end + process $group_123 + assign \xer_so$24$next \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$24$next \xer_so$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$24$next \xer_so$123 + end + sync init + update \xer_so$24 1'0 + sync posedge \clk + update \xer_so$24 \xer_so$24$next + end + process $group_124 + assign \divisor_neg$25$next \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$25$next \divisor_neg$124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$25$next \divisor_neg$124 + end + sync init + update \divisor_neg$25 1'0 + sync posedge \clk + update \divisor_neg$25 \divisor_neg$25$next + end + process $group_125 + assign \dividend_neg$26$next \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$26$next \dividend_neg$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$26$next \dividend_neg$125 + end + sync init + update \dividend_neg$26 1'0 + sync posedge \clk + update \dividend_neg$26 \dividend_neg$26$next + end + process $group_126 + assign \divisor_radicand$27$next \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$27$next \divisor_radicand$126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$27$next \divisor_radicand$126 + end + sync init + update \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \divisor_radicand$27 \divisor_radicand$27$next + end + process $group_127 + assign \operation$28$next \operation$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$28$next \operation$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$28$next \operation$127 + end + sync init + update \operation$28 2'00 + sync posedge \clk + update \operation$28 \operation$28$next + end + process $group_128 + assign \quotient_root$29$next \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$29$next \quotient_root$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$29$next \quotient_root$128 + end + sync init + update \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \quotient_root$29 \quotient_root$29$next + end + process $group_129 + assign \root_times_radicand$30$next \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$30$next \root_times_radicand$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$30$next \root_times_radicand$129 + end + sync init + update \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \root_times_radicand$30 \root_times_radicand$30$next + end + process $group_130 + assign \compare_lhs$31$next \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$31$next \compare_lhs$130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$31$next \compare_lhs$130 + end + sync init + update \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_lhs$31 \compare_lhs$31$next + end + process $group_131 + assign \compare_rhs$32$next \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$32$next \compare_rhs$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$32$next \compare_rhs$131 + end + sync init + update \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_rhs$32 \compare_rhs$32$next + end + process $group_132 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_133 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.p" +module \p$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.n" +module \n$132 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_8.core.trial0" +module \trial0$134 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000000 + connect \B 8'10001010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1001010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_8.core.trial1" +module \trial1$135 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000001 + connect \B 8'10001010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1001010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_8.core.trial2" +module \trial2$136 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000100 + connect \B 8'10001010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1001010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_8.core.trial3" +module \trial3$137 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'001001 + connect \B 8'10001010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1001010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_8.core.trial4" +module \trial4$138 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'010000 + connect \B 8'10001010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1001010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_8.core.trial5" +module \trial5$139 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'011001 + connect \B 8'10001010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1001010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_8.core.trial6" +module \trial6$140 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'100100 + connect \B 8'10001010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1001010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_8.core.trial7" +module \trial7$141 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'110001 + connect \B 8'10001010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1001010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_8.core.pe" +module \pe$142 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_8.core" +module \core$133 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$134 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$135 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$136 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$137 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$138 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$139 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$140 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$141 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$142 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 66 + connect \A \next_bits + connect \B 6'100101 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 66 + connect \A \quotient_root + connect \B $31 + connect \Y $33 + end + connect $30 $33 + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $30 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 130 $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 130 + connect \A $36 + connect \B 6'100101 + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 130 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B $38 + connect \Y $40 + end + connect $35 $40 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $35 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_8" +module \core_calculate_stage_8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$133 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_9.core.trial0" +module \trial0$144 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000000 + connect \B 8'10000100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1000100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_9.core.trial1" +module \trial1$145 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000001 + connect \B 8'10000100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1000100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_9.core.trial2" +module \trial2$146 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'000100 + connect \B 8'10000100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1000100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_9.core.trial3" +module \trial3$147 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'001001 + connect \B 8'10000100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1000100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_9.core.trial4" +module \trial4$148 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'010000 + connect \B 8'10000100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1000100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_9.core.trial5" +module \trial5$149 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'011001 + connect \B 8'10000100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1000100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_9.core.trial6" +module \trial6$150 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'100100 + connect \B 8'10000100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1000100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_9.core.trial7" +module \trial7$151 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1100010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 261 + connect \A 6'110001 + connect \B 8'10000100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 261 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 197 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 197 + connect \A \dr_times_trial_bits_sqrd + connect \B 7'1000100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 197 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_9.core.pe" +module \pe$152 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_9.core" +module \core$143 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$144 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$145 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$146 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$147 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$148 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$149 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$150 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$151 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$152 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 66 + connect \A \next_bits + connect \B 6'100010 + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 66 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 66 + connect \A \quotient_root + connect \B $31 + connect \Y $33 + end + connect $30 $33 + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $30 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 130 $38 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 130 + connect \A $36 + connect \B 6'100010 + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 131 $40 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 130 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B $38 + connect \Y $40 + end + connect $35 $40 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $35 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10.core_calculate_stage_9" +module \core_calculate_stage_9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$143 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_8_to_10" +module \pipe_8_to_10 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 4 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 5 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 7 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 16 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 18 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 20 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 21 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 22 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 23 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 24 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 25 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 26 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 28 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 29 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 30 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 31 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 32 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 33 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 34 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 35 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 36 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 37 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 38 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$1$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 39 \op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 40 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 41 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 46 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 50 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 51 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 52 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 53 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 54 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 55 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 56 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 57 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 58 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 59 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 60 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 61 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 62 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 63 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$26$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 64 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 65 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 66 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 67 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 68 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 69 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$32$next + cell \p$131 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$132 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_8_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_8_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_8_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_8_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_8_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_8_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_8_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_8_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_8_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_8_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_8_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_8_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_8_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_8_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_8_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_8_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_8_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_8_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_8_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_8_muxid$33 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_8_op__insn_type$34 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_8_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_8_op__imm_data__imm$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__imm_data__imm_ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__lk$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__invert_a$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_8_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_8_op__write_cr__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__write_cr__ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__output_carry$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__is_32bit$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_8_op__is_signed$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_8_op__data_len$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_8_op__insn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_8_ra$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_8_rb$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_8_xer_so$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_8_divisor_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_8_dividend_neg$58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_8_divisor_radicand$59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_8_operation$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_8_quotient_root$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_8_root_times_radicand$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_8_compare_lhs$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_8_compare_rhs$64 + cell \core_calculate_stage_8 \core_calculate_stage_8 + connect \muxid \core_calculate_stage_8_muxid + connect \op__insn_type \core_calculate_stage_8_op__insn_type + connect \op__fn_unit \core_calculate_stage_8_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_8_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_8_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_8_op__lk + connect \op__rc__rc \core_calculate_stage_8_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_8_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_8_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_8_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_8_op__invert_a + connect \op__zero_a \core_calculate_stage_8_op__zero_a + connect \op__input_carry \core_calculate_stage_8_op__input_carry + connect \op__invert_out \core_calculate_stage_8_op__invert_out + connect \op__write_cr__data \core_calculate_stage_8_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_8_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_8_op__output_carry + connect \op__is_32bit \core_calculate_stage_8_op__is_32bit + connect \op__is_signed \core_calculate_stage_8_op__is_signed + connect \op__data_len \core_calculate_stage_8_op__data_len + connect \op__insn \core_calculate_stage_8_op__insn + connect \ra \core_calculate_stage_8_ra + connect \rb \core_calculate_stage_8_rb + connect \xer_so \core_calculate_stage_8_xer_so + connect \divisor_neg \core_calculate_stage_8_divisor_neg + connect \dividend_neg \core_calculate_stage_8_dividend_neg + connect \divisor_radicand \core_calculate_stage_8_divisor_radicand + connect \operation \core_calculate_stage_8_operation + connect \quotient_root \core_calculate_stage_8_quotient_root + connect \root_times_radicand \core_calculate_stage_8_root_times_radicand + connect \compare_lhs \core_calculate_stage_8_compare_lhs + connect \compare_rhs \core_calculate_stage_8_compare_rhs + connect \muxid$1 \core_calculate_stage_8_muxid$33 + connect \op__insn_type$2 \core_calculate_stage_8_op__insn_type$34 + connect \op__fn_unit$3 \core_calculate_stage_8_op__fn_unit$35 + connect \op__imm_data__imm$4 \core_calculate_stage_8_op__imm_data__imm$36 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_8_op__imm_data__imm_ok$37 + connect \op__lk$6 \core_calculate_stage_8_op__lk$38 + connect \op__rc__rc$7 \core_calculate_stage_8_op__rc__rc$39 + connect \op__rc__rc_ok$8 \core_calculate_stage_8_op__rc__rc_ok$40 + connect \op__oe__oe$9 \core_calculate_stage_8_op__oe__oe$41 + connect \op__oe__oe_ok$10 \core_calculate_stage_8_op__oe__oe_ok$42 + connect \op__invert_a$11 \core_calculate_stage_8_op__invert_a$43 + connect \op__zero_a$12 \core_calculate_stage_8_op__zero_a$44 + connect \op__input_carry$13 \core_calculate_stage_8_op__input_carry$45 + connect \op__invert_out$14 \core_calculate_stage_8_op__invert_out$46 + connect \op__write_cr__data$15 \core_calculate_stage_8_op__write_cr__data$47 + connect \op__write_cr__ok$16 \core_calculate_stage_8_op__write_cr__ok$48 + connect \op__output_carry$17 \core_calculate_stage_8_op__output_carry$49 + connect \op__is_32bit$18 \core_calculate_stage_8_op__is_32bit$50 + connect \op__is_signed$19 \core_calculate_stage_8_op__is_signed$51 + connect \op__data_len$20 \core_calculate_stage_8_op__data_len$52 + connect \op__insn$21 \core_calculate_stage_8_op__insn$53 + connect \ra$22 \core_calculate_stage_8_ra$54 + connect \rb$23 \core_calculate_stage_8_rb$55 + connect \xer_so$24 \core_calculate_stage_8_xer_so$56 + connect \divisor_neg$25 \core_calculate_stage_8_divisor_neg$57 + connect \dividend_neg$26 \core_calculate_stage_8_dividend_neg$58 + connect \divisor_radicand$27 \core_calculate_stage_8_divisor_radicand$59 + connect \operation$28 \core_calculate_stage_8_operation$60 + connect \quotient_root$29 \core_calculate_stage_8_quotient_root$61 + connect \root_times_radicand$30 \core_calculate_stage_8_root_times_radicand$62 + connect \compare_lhs$31 \core_calculate_stage_8_compare_lhs$63 + connect \compare_rhs$32 \core_calculate_stage_8_compare_rhs$64 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_9_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_9_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_9_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_9_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_9_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_9_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_9_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_9_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_9_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_9_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_9_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_9_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_9_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_9_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_9_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_9_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_9_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_9_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_9_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_9_muxid$65 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_9_op__insn_type$66 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_9_op__fn_unit$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_9_op__imm_data__imm$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__imm_data__imm_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__lk$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__rc__rc_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__oe__oe_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__invert_a$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__zero_a$76 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_9_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_9_op__write_cr__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__write_cr__ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_9_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_9_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_9_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_9_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_9_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_9_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_9_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_9_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_9_divisor_radicand$91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_9_operation$92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_9_quotient_root$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_9_root_times_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_9_compare_lhs$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_9_compare_rhs$96 + cell \core_calculate_stage_9 \core_calculate_stage_9 + connect \muxid \core_calculate_stage_9_muxid + connect \op__insn_type \core_calculate_stage_9_op__insn_type + connect \op__fn_unit \core_calculate_stage_9_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_9_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_9_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_9_op__lk + connect \op__rc__rc \core_calculate_stage_9_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_9_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_9_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_9_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_9_op__invert_a + connect \op__zero_a \core_calculate_stage_9_op__zero_a + connect \op__input_carry \core_calculate_stage_9_op__input_carry + connect \op__invert_out \core_calculate_stage_9_op__invert_out + connect \op__write_cr__data \core_calculate_stage_9_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_9_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_9_op__output_carry + connect \op__is_32bit \core_calculate_stage_9_op__is_32bit + connect \op__is_signed \core_calculate_stage_9_op__is_signed + connect \op__data_len \core_calculate_stage_9_op__data_len + connect \op__insn \core_calculate_stage_9_op__insn + connect \ra \core_calculate_stage_9_ra + connect \rb \core_calculate_stage_9_rb + connect \xer_so \core_calculate_stage_9_xer_so + connect \divisor_neg \core_calculate_stage_9_divisor_neg + connect \dividend_neg \core_calculate_stage_9_dividend_neg + connect \divisor_radicand \core_calculate_stage_9_divisor_radicand + connect \operation \core_calculate_stage_9_operation + connect \quotient_root \core_calculate_stage_9_quotient_root + connect \root_times_radicand \core_calculate_stage_9_root_times_radicand + connect \compare_lhs \core_calculate_stage_9_compare_lhs + connect \compare_rhs \core_calculate_stage_9_compare_rhs + connect \muxid$1 \core_calculate_stage_9_muxid$65 + connect \op__insn_type$2 \core_calculate_stage_9_op__insn_type$66 + connect \op__fn_unit$3 \core_calculate_stage_9_op__fn_unit$67 + connect \op__imm_data__imm$4 \core_calculate_stage_9_op__imm_data__imm$68 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_9_op__imm_data__imm_ok$69 + connect \op__lk$6 \core_calculate_stage_9_op__lk$70 + connect \op__rc__rc$7 \core_calculate_stage_9_op__rc__rc$71 + connect \op__rc__rc_ok$8 \core_calculate_stage_9_op__rc__rc_ok$72 + connect \op__oe__oe$9 \core_calculate_stage_9_op__oe__oe$73 + connect \op__oe__oe_ok$10 \core_calculate_stage_9_op__oe__oe_ok$74 + connect \op__invert_a$11 \core_calculate_stage_9_op__invert_a$75 + connect \op__zero_a$12 \core_calculate_stage_9_op__zero_a$76 + connect \op__input_carry$13 \core_calculate_stage_9_op__input_carry$77 + connect \op__invert_out$14 \core_calculate_stage_9_op__invert_out$78 + connect \op__write_cr__data$15 \core_calculate_stage_9_op__write_cr__data$79 + connect \op__write_cr__ok$16 \core_calculate_stage_9_op__write_cr__ok$80 + connect \op__output_carry$17 \core_calculate_stage_9_op__output_carry$81 + connect \op__is_32bit$18 \core_calculate_stage_9_op__is_32bit$82 + connect \op__is_signed$19 \core_calculate_stage_9_op__is_signed$83 + connect \op__data_len$20 \core_calculate_stage_9_op__data_len$84 + connect \op__insn$21 \core_calculate_stage_9_op__insn$85 + connect \ra$22 \core_calculate_stage_9_ra$86 + connect \rb$23 \core_calculate_stage_9_rb$87 + connect \xer_so$24 \core_calculate_stage_9_xer_so$88 + connect \divisor_neg$25 \core_calculate_stage_9_divisor_neg$89 + connect \dividend_neg$26 \core_calculate_stage_9_dividend_neg$90 + connect \divisor_radicand$27 \core_calculate_stage_9_divisor_radicand$91 + connect \operation$28 \core_calculate_stage_9_operation$92 + connect \quotient_root$29 \core_calculate_stage_9_quotient_root$93 + connect \root_times_radicand$30 \core_calculate_stage_9_root_times_radicand$94 + connect \compare_lhs$31 \core_calculate_stage_9_compare_lhs$95 + connect \compare_rhs$32 \core_calculate_stage_9_compare_rhs$96 + end + process $group_0 + assign \core_calculate_stage_8_muxid 2'00 + assign \core_calculate_stage_8_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_8_op__insn_type 7'0000000 + assign \core_calculate_stage_8_op__fn_unit 10'0000000000 + assign \core_calculate_stage_8_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_8_op__lk 1'0 + assign \core_calculate_stage_8_op__rc__rc 1'0 + assign \core_calculate_stage_8_op__rc__rc_ok 1'0 + assign \core_calculate_stage_8_op__oe__oe 1'0 + assign \core_calculate_stage_8_op__oe__oe_ok 1'0 + assign \core_calculate_stage_8_op__invert_a 1'0 + assign \core_calculate_stage_8_op__zero_a 1'0 + assign \core_calculate_stage_8_op__input_carry 2'00 + assign \core_calculate_stage_8_op__invert_out 1'0 + assign \core_calculate_stage_8_op__write_cr__data 3'000 + assign \core_calculate_stage_8_op__write_cr__ok 1'0 + assign \core_calculate_stage_8_op__output_carry 1'0 + assign \core_calculate_stage_8_op__is_32bit 1'0 + assign \core_calculate_stage_8_op__is_signed 1'0 + assign \core_calculate_stage_8_op__data_len 4'0000 + assign \core_calculate_stage_8_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_8_op__insn \core_calculate_stage_8_op__data_len \core_calculate_stage_8_op__is_signed \core_calculate_stage_8_op__is_32bit \core_calculate_stage_8_op__output_carry { \core_calculate_stage_8_op__write_cr__ok \core_calculate_stage_8_op__write_cr__data } \core_calculate_stage_8_op__invert_out \core_calculate_stage_8_op__input_carry \core_calculate_stage_8_op__zero_a \core_calculate_stage_8_op__invert_a { \core_calculate_stage_8_op__oe__oe_ok \core_calculate_stage_8_op__oe__oe } { \core_calculate_stage_8_op__rc__rc_ok \core_calculate_stage_8_op__rc__rc } \core_calculate_stage_8_op__lk { \core_calculate_stage_8_op__imm_data__imm_ok \core_calculate_stage_8_op__imm_data__imm } \core_calculate_stage_8_op__fn_unit \core_calculate_stage_8_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \core_calculate_stage_8_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_ra \ra + sync init + end + process $group_22 + assign \core_calculate_stage_8_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_rb \rb + sync init + end + process $group_23 + assign \core_calculate_stage_8_xer_so 1'0 + assign \core_calculate_stage_8_xer_so \xer_so + sync init + end + process $group_24 + assign \core_calculate_stage_8_divisor_neg 1'0 + assign \core_calculate_stage_8_divisor_neg \divisor_neg + sync init + end + process $group_25 + assign \core_calculate_stage_8_dividend_neg 1'0 + assign \core_calculate_stage_8_dividend_neg \dividend_neg + sync init + end + process $group_26 + assign \core_calculate_stage_8_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_calculate_stage_8_operation 2'00 + assign \core_calculate_stage_8_operation \operation + sync init + end + process $group_28 + assign \core_calculate_stage_8_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_calculate_stage_8_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_calculate_stage_8_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_calculate_stage_8_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_8_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \core_calculate_stage_9_muxid 2'00 + assign \core_calculate_stage_9_muxid \core_calculate_stage_8_muxid$33 + sync init + end + process $group_33 + assign \core_calculate_stage_9_op__insn_type 7'0000000 + assign \core_calculate_stage_9_op__fn_unit 10'0000000000 + assign \core_calculate_stage_9_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_9_op__lk 1'0 + assign \core_calculate_stage_9_op__rc__rc 1'0 + assign \core_calculate_stage_9_op__rc__rc_ok 1'0 + assign \core_calculate_stage_9_op__oe__oe 1'0 + assign \core_calculate_stage_9_op__oe__oe_ok 1'0 + assign \core_calculate_stage_9_op__invert_a 1'0 + assign \core_calculate_stage_9_op__zero_a 1'0 + assign \core_calculate_stage_9_op__input_carry 2'00 + assign \core_calculate_stage_9_op__invert_out 1'0 + assign \core_calculate_stage_9_op__write_cr__data 3'000 + assign \core_calculate_stage_9_op__write_cr__ok 1'0 + assign \core_calculate_stage_9_op__output_carry 1'0 + assign \core_calculate_stage_9_op__is_32bit 1'0 + assign \core_calculate_stage_9_op__is_signed 1'0 + assign \core_calculate_stage_9_op__data_len 4'0000 + assign \core_calculate_stage_9_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_9_op__insn \core_calculate_stage_9_op__data_len \core_calculate_stage_9_op__is_signed \core_calculate_stage_9_op__is_32bit \core_calculate_stage_9_op__output_carry { \core_calculate_stage_9_op__write_cr__ok \core_calculate_stage_9_op__write_cr__data } \core_calculate_stage_9_op__invert_out \core_calculate_stage_9_op__input_carry \core_calculate_stage_9_op__zero_a \core_calculate_stage_9_op__invert_a { \core_calculate_stage_9_op__oe__oe_ok \core_calculate_stage_9_op__oe__oe } { \core_calculate_stage_9_op__rc__rc_ok \core_calculate_stage_9_op__rc__rc } \core_calculate_stage_9_op__lk { \core_calculate_stage_9_op__imm_data__imm_ok \core_calculate_stage_9_op__imm_data__imm } \core_calculate_stage_9_op__fn_unit \core_calculate_stage_9_op__insn_type } { \core_calculate_stage_8_op__insn$53 \core_calculate_stage_8_op__data_len$52 \core_calculate_stage_8_op__is_signed$51 \core_calculate_stage_8_op__is_32bit$50 \core_calculate_stage_8_op__output_carry$49 { \core_calculate_stage_8_op__write_cr__ok$48 \core_calculate_stage_8_op__write_cr__data$47 } \core_calculate_stage_8_op__invert_out$46 \core_calculate_stage_8_op__input_carry$45 \core_calculate_stage_8_op__zero_a$44 \core_calculate_stage_8_op__invert_a$43 { \core_calculate_stage_8_op__oe__oe_ok$42 \core_calculate_stage_8_op__oe__oe$41 } { \core_calculate_stage_8_op__rc__rc_ok$40 \core_calculate_stage_8_op__rc__rc$39 } \core_calculate_stage_8_op__lk$38 { \core_calculate_stage_8_op__imm_data__imm_ok$37 \core_calculate_stage_8_op__imm_data__imm$36 } \core_calculate_stage_8_op__fn_unit$35 \core_calculate_stage_8_op__insn_type$34 } + sync init + end + process $group_53 + assign \core_calculate_stage_9_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_ra \core_calculate_stage_8_ra$54 + sync init + end + process $group_54 + assign \core_calculate_stage_9_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_rb \core_calculate_stage_8_rb$55 + sync init + end + process $group_55 + assign \core_calculate_stage_9_xer_so 1'0 + assign \core_calculate_stage_9_xer_so \core_calculate_stage_8_xer_so$56 + sync init + end + process $group_56 + assign \core_calculate_stage_9_divisor_neg 1'0 + assign \core_calculate_stage_9_divisor_neg \core_calculate_stage_8_divisor_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_9_dividend_neg 1'0 + assign \core_calculate_stage_9_dividend_neg \core_calculate_stage_8_dividend_neg$58 + sync init + end + process $group_58 + assign \core_calculate_stage_9_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_divisor_radicand \core_calculate_stage_8_divisor_radicand$59 + sync init + end + process $group_59 + assign \core_calculate_stage_9_operation 2'00 + assign \core_calculate_stage_9_operation \core_calculate_stage_8_operation$60 + sync init + end + process $group_60 + assign \core_calculate_stage_9_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_quotient_root \core_calculate_stage_8_quotient_root$61 + sync init + end + process $group_61 + assign \core_calculate_stage_9_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_root_times_radicand \core_calculate_stage_8_root_times_radicand$62 + sync init + end + process $group_62 + assign \core_calculate_stage_9_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_compare_lhs \core_calculate_stage_8_compare_lhs$63 + sync init + end + process $group_63 + assign \core_calculate_stage_9_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_9_compare_rhs \core_calculate_stage_8_compare_rhs$64 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$97 + process $group_64 + assign \p_valid_i$97 1'0 + assign \p_valid_i$97 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_65 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $98 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$97 + connect \B \p_ready_o + connect \Y $98 + end + process $group_66 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $98 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$100 + process $group_67 + assign \muxid$100 2'00 + assign \muxid$100 \core_calculate_stage_9_muxid$65 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$111 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$120 + process $group_68 + assign \op__insn_type$101 7'0000000 + assign \op__fn_unit$102 10'0000000000 + assign \op__imm_data__imm$103 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$104 1'0 + assign \op__lk$105 1'0 + assign \op__rc__rc$106 1'0 + assign \op__rc__rc_ok$107 1'0 + assign \op__oe__oe$108 1'0 + assign \op__oe__oe_ok$109 1'0 + assign \op__invert_a$110 1'0 + assign \op__zero_a$111 1'0 + assign \op__input_carry$112 2'00 + assign \op__invert_out$113 1'0 + assign \op__write_cr__data$114 3'000 + assign \op__write_cr__ok$115 1'0 + assign \op__output_carry$116 1'0 + assign \op__is_32bit$117 1'0 + assign \op__is_signed$118 1'0 + assign \op__data_len$119 4'0000 + assign \op__insn$120 32'00000000000000000000000000000000 + assign { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } { \core_calculate_stage_9_op__insn$85 \core_calculate_stage_9_op__data_len$84 \core_calculate_stage_9_op__is_signed$83 \core_calculate_stage_9_op__is_32bit$82 \core_calculate_stage_9_op__output_carry$81 { \core_calculate_stage_9_op__write_cr__ok$80 \core_calculate_stage_9_op__write_cr__data$79 } \core_calculate_stage_9_op__invert_out$78 \core_calculate_stage_9_op__input_carry$77 \core_calculate_stage_9_op__zero_a$76 \core_calculate_stage_9_op__invert_a$75 { \core_calculate_stage_9_op__oe__oe_ok$74 \core_calculate_stage_9_op__oe__oe$73 } { \core_calculate_stage_9_op__rc__rc_ok$72 \core_calculate_stage_9_op__rc__rc$71 } \core_calculate_stage_9_op__lk$70 { \core_calculate_stage_9_op__imm_data__imm_ok$69 \core_calculate_stage_9_op__imm_data__imm$68 } \core_calculate_stage_9_op__fn_unit$67 \core_calculate_stage_9_op__insn_type$66 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$121 + process $group_88 + assign \ra$121 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$121 \core_calculate_stage_9_ra$86 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$122 + process $group_89 + assign \rb$122 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$122 \core_calculate_stage_9_rb$87 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$123 + process $group_90 + assign \xer_so$123 1'0 + assign \xer_so$123 \core_calculate_stage_9_xer_so$88 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$124 + process $group_91 + assign \divisor_neg$124 1'0 + assign \divisor_neg$124 \core_calculate_stage_9_divisor_neg$89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$125 + process $group_92 + assign \dividend_neg$125 1'0 + assign \dividend_neg$125 \core_calculate_stage_9_dividend_neg$90 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$126 + process $group_93 + assign \divisor_radicand$126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$126 \core_calculate_stage_9_divisor_radicand$91 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$127 + process $group_94 + assign \operation$127 2'00 + assign \operation$127 \core_calculate_stage_9_operation$92 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$128 + process $group_95 + assign \quotient_root$128 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$128 \core_calculate_stage_9_quotient_root$93 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$129 + process $group_96 + assign \root_times_radicand$129 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$129 \core_calculate_stage_9_root_times_radicand$94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$130 + process $group_97 + assign \compare_lhs$130 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$130 \core_calculate_stage_9_compare_lhs$95 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$131 + process $group_98 + assign \compare_rhs$131 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$131 \core_calculate_stage_9_compare_rhs$96 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_99 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_100 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$100 + end + sync init + update \muxid$1 2'00 + sync posedge \clk + update \muxid$1 \muxid$1$next + end + process $group_101 + assign \op__insn_type$2$next \op__insn_type$2 + assign \op__fn_unit$3$next \op__fn_unit$3 + assign \op__imm_data__imm$4$next \op__imm_data__imm$4 + assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5 + assign \op__lk$6$next \op__lk$6 + assign \op__rc__rc$7$next \op__rc__rc$7 + assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8 + assign \op__oe__oe$9$next \op__oe__oe$9 + assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10 + assign \op__invert_a$11$next \op__invert_a$11 + assign \op__zero_a$12$next \op__zero_a$12 + assign \op__input_carry$13$next \op__input_carry$13 + assign \op__invert_out$14$next \op__invert_out$14 + assign \op__write_cr__data$15$next \op__write_cr__data$15 + assign \op__write_cr__ok$16$next \op__write_cr__ok$16 + assign \op__output_carry$17$next \op__output_carry$17 + assign \op__is_32bit$18$next \op__is_32bit$18 + assign \op__is_signed$19$next \op__is_signed$19 + assign \op__data_len$20$next \op__data_len$20 + assign \op__insn$21$next \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5$next 1'0 + assign \op__rc__rc$7$next 1'0 + assign \op__rc__rc_ok$8$next 1'0 + assign \op__oe__oe$9$next 1'0 + assign \op__oe__oe_ok$10$next 1'0 + assign \op__write_cr__data$15$next 3'000 + assign \op__write_cr__ok$16$next 1'0 + assign \op__insn$21$next 32'00000000000000000000000000000000 + end + sync init + update \op__insn_type$2 7'0000000 + update \op__fn_unit$3 10'0000000000 + update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \op__imm_data__imm_ok$5 1'0 + update \op__lk$6 1'0 + update \op__rc__rc$7 1'0 + update \op__rc__rc_ok$8 1'0 + update \op__oe__oe$9 1'0 + update \op__oe__oe_ok$10 1'0 + update \op__invert_a$11 1'0 + update \op__zero_a$12 1'0 + update \op__input_carry$13 2'00 + update \op__invert_out$14 1'0 + update \op__write_cr__data$15 3'000 + update \op__write_cr__ok$16 1'0 + update \op__output_carry$17 1'0 + update \op__is_32bit$18 1'0 + update \op__is_signed$19 1'0 + update \op__data_len$20 4'0000 + update \op__insn$21 32'00000000000000000000000000000000 + sync posedge \clk + update \op__insn_type$2 \op__insn_type$2$next + update \op__fn_unit$3 \op__fn_unit$3$next + update \op__imm_data__imm$4 \op__imm_data__imm$4$next + update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next + update \op__lk$6 \op__lk$6$next + update \op__rc__rc$7 \op__rc__rc$7$next + update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next + update \op__oe__oe$9 \op__oe__oe$9$next + update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next + update \op__invert_a$11 \op__invert_a$11$next + update \op__zero_a$12 \op__zero_a$12$next + update \op__input_carry$13 \op__input_carry$13$next + update \op__invert_out$14 \op__invert_out$14$next + update \op__write_cr__data$15 \op__write_cr__data$15$next + update \op__write_cr__ok$16 \op__write_cr__ok$16$next + update \op__output_carry$17 \op__output_carry$17$next + update \op__is_32bit$18 \op__is_32bit$18$next + update \op__is_signed$19 \op__is_signed$19$next + update \op__data_len$20 \op__data_len$20$next + update \op__insn$21 \op__insn$21$next + end + process $group_121 + assign \ra$22$next \ra$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$22$next \ra$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$22$next \ra$121 + end + sync init + update \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \ra$22 \ra$22$next + end + process $group_122 + assign \rb$23$next \rb$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$23$next \rb$122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$23$next \rb$122 + end + sync init + update \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \rb$23 \rb$23$next + end + process $group_123 + assign \xer_so$24$next \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$24$next \xer_so$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$24$next \xer_so$123 + end + sync init + update \xer_so$24 1'0 + sync posedge \clk + update \xer_so$24 \xer_so$24$next + end + process $group_124 + assign \divisor_neg$25$next \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$25$next \divisor_neg$124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$25$next \divisor_neg$124 + end + sync init + update \divisor_neg$25 1'0 + sync posedge \clk + update \divisor_neg$25 \divisor_neg$25$next + end + process $group_125 + assign \dividend_neg$26$next \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$26$next \dividend_neg$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$26$next \dividend_neg$125 + end + sync init + update \dividend_neg$26 1'0 + sync posedge \clk + update \dividend_neg$26 \dividend_neg$26$next + end + process $group_126 + assign \divisor_radicand$27$next \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$27$next \divisor_radicand$126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$27$next \divisor_radicand$126 + end + sync init + update \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \divisor_radicand$27 \divisor_radicand$27$next + end + process $group_127 + assign \operation$28$next \operation$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$28$next \operation$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$28$next \operation$127 + end + sync init + update \operation$28 2'00 + sync posedge \clk + update \operation$28 \operation$28$next + end + process $group_128 + assign \quotient_root$29$next \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$29$next \quotient_root$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$29$next \quotient_root$128 + end + sync init + update \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \quotient_root$29 \quotient_root$29$next + end + process $group_129 + assign \root_times_radicand$30$next \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$30$next \root_times_radicand$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$30$next \root_times_radicand$129 + end + sync init + update \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \root_times_radicand$30 \root_times_radicand$30$next + end + process $group_130 + assign \compare_lhs$31$next \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$31$next \compare_lhs$130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$31$next \compare_lhs$130 + end + sync init + update \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_lhs$31 \compare_lhs$31$next + end + process $group_131 + assign \compare_rhs$32$next \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$32$next \compare_rhs$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$32$next \compare_rhs$131 + end + sync init + update \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_rhs$32 \compare_rhs$32$next + end + process $group_132 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_133 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.p" +module \p$153 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.n" +module \n$154 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_10.core.trial0" +module \trial0$156 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000000 + connect \B 7'1111110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_10.core.trial1" +module \trial1$157 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000001 + connect \B 7'1111110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_10.core.trial2" +module \trial2$158 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000100 + connect \B 7'1111110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_10.core.trial3" +module \trial3$159 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'001001 + connect \B 7'1111110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_10.core.trial4" +module \trial4$160 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'010000 + connect \B 7'1111110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_10.core.trial5" +module \trial5$161 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'011001 + connect \B 7'1111110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_10.core.trial6" +module \trial6$162 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'100100 + connect \B 7'1111110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_10.core.trial7" +module \trial7$163 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1100000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'110001 + connect \B 7'1111110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 267 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 267 + connect \A \rr_times_trial_bits + connect \B 6'100000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 268 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 267 + parameter \Y_WIDTH 268 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 269 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 268 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 269 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_10.core.pe" +module \pe$164 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_10.core" +module \core$155 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$156 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$157 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$158 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$159 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$160 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$161 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$162 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$163 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$164 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 34 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 34 + connect \A \next_bits + connect \B 5'11111 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 34 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 98 $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 98 + connect \A $35 + connect \B 5'11111 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 98 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B $37 + connect \Y $39 + end + connect $34 $39 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $34 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_10" +module \core_calculate_stage_10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$155 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_11.core.trial0" +module \trial0$166 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000000 + connect \B 7'1111000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_11.core.trial1" +module \trial1$167 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000001 + connect \B 7'1111000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_11.core.trial2" +module \trial2$168 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000100 + connect \B 7'1111000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_11.core.trial3" +module \trial3$169 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'001001 + connect \B 7'1111000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_11.core.trial4" +module \trial4$170 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'010000 + connect \B 7'1111000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_11.core.trial5" +module \trial5$171 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'011001 + connect \B 7'1111000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_11.core.trial6" +module \trial6$172 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'100100 + connect \B 7'1111000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_11.core.trial7" +module \trial7$173 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'110001 + connect \B 7'1111000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'111000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_11.core.pe" +module \pe$174 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_11.core" +module \core$165 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$166 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$167 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$168 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$169 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$170 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$171 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$172 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$173 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$174 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 34 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 34 + connect \A \next_bits + connect \B 5'11100 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 34 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 98 $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 98 + connect \A $35 + connect \B 5'11100 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 98 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B $37 + connect \Y $39 + end + connect $34 $39 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $34 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12.core_calculate_stage_11" +module \core_calculate_stage_11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$165 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_10_to_12" +module \pipe_10_to_12 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 4 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 5 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 7 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 16 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 18 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 20 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 21 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 22 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 23 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 24 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 25 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 26 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 28 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 29 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 30 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 31 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 32 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 33 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 34 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 35 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 36 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 37 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 38 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$1$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 39 \op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 40 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 41 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 46 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 50 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 51 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 52 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 53 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 54 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 55 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 56 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 57 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 58 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 59 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 60 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 61 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 62 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 63 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$26$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 64 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 65 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 66 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 67 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 68 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 69 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$32$next + cell \p$153 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$154 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_10_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_10_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_10_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_10_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_10_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_10_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_10_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_10_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_10_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_10_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_10_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_10_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_10_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_10_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_10_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_10_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_10_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_10_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_10_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_10_muxid$33 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_10_op__insn_type$34 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_10_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_10_op__imm_data__imm$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__imm_data__imm_ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__lk$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__invert_a$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_10_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_10_op__write_cr__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__write_cr__ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__output_carry$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__is_32bit$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_10_op__is_signed$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_10_op__data_len$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_10_op__insn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_10_ra$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_10_rb$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_10_xer_so$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_10_divisor_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_10_dividend_neg$58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_10_divisor_radicand$59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_10_operation$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_10_quotient_root$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_10_root_times_radicand$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_10_compare_lhs$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_10_compare_rhs$64 + cell \core_calculate_stage_10 \core_calculate_stage_10 + connect \muxid \core_calculate_stage_10_muxid + connect \op__insn_type \core_calculate_stage_10_op__insn_type + connect \op__fn_unit \core_calculate_stage_10_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_10_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_10_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_10_op__lk + connect \op__rc__rc \core_calculate_stage_10_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_10_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_10_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_10_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_10_op__invert_a + connect \op__zero_a \core_calculate_stage_10_op__zero_a + connect \op__input_carry \core_calculate_stage_10_op__input_carry + connect \op__invert_out \core_calculate_stage_10_op__invert_out + connect \op__write_cr__data \core_calculate_stage_10_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_10_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_10_op__output_carry + connect \op__is_32bit \core_calculate_stage_10_op__is_32bit + connect \op__is_signed \core_calculate_stage_10_op__is_signed + connect \op__data_len \core_calculate_stage_10_op__data_len + connect \op__insn \core_calculate_stage_10_op__insn + connect \ra \core_calculate_stage_10_ra + connect \rb \core_calculate_stage_10_rb + connect \xer_so \core_calculate_stage_10_xer_so + connect \divisor_neg \core_calculate_stage_10_divisor_neg + connect \dividend_neg \core_calculate_stage_10_dividend_neg + connect \divisor_radicand \core_calculate_stage_10_divisor_radicand + connect \operation \core_calculate_stage_10_operation + connect \quotient_root \core_calculate_stage_10_quotient_root + connect \root_times_radicand \core_calculate_stage_10_root_times_radicand + connect \compare_lhs \core_calculate_stage_10_compare_lhs + connect \compare_rhs \core_calculate_stage_10_compare_rhs + connect \muxid$1 \core_calculate_stage_10_muxid$33 + connect \op__insn_type$2 \core_calculate_stage_10_op__insn_type$34 + connect \op__fn_unit$3 \core_calculate_stage_10_op__fn_unit$35 + connect \op__imm_data__imm$4 \core_calculate_stage_10_op__imm_data__imm$36 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_10_op__imm_data__imm_ok$37 + connect \op__lk$6 \core_calculate_stage_10_op__lk$38 + connect \op__rc__rc$7 \core_calculate_stage_10_op__rc__rc$39 + connect \op__rc__rc_ok$8 \core_calculate_stage_10_op__rc__rc_ok$40 + connect \op__oe__oe$9 \core_calculate_stage_10_op__oe__oe$41 + connect \op__oe__oe_ok$10 \core_calculate_stage_10_op__oe__oe_ok$42 + connect \op__invert_a$11 \core_calculate_stage_10_op__invert_a$43 + connect \op__zero_a$12 \core_calculate_stage_10_op__zero_a$44 + connect \op__input_carry$13 \core_calculate_stage_10_op__input_carry$45 + connect \op__invert_out$14 \core_calculate_stage_10_op__invert_out$46 + connect \op__write_cr__data$15 \core_calculate_stage_10_op__write_cr__data$47 + connect \op__write_cr__ok$16 \core_calculate_stage_10_op__write_cr__ok$48 + connect \op__output_carry$17 \core_calculate_stage_10_op__output_carry$49 + connect \op__is_32bit$18 \core_calculate_stage_10_op__is_32bit$50 + connect \op__is_signed$19 \core_calculate_stage_10_op__is_signed$51 + connect \op__data_len$20 \core_calculate_stage_10_op__data_len$52 + connect \op__insn$21 \core_calculate_stage_10_op__insn$53 + connect \ra$22 \core_calculate_stage_10_ra$54 + connect \rb$23 \core_calculate_stage_10_rb$55 + connect \xer_so$24 \core_calculate_stage_10_xer_so$56 + connect \divisor_neg$25 \core_calculate_stage_10_divisor_neg$57 + connect \dividend_neg$26 \core_calculate_stage_10_dividend_neg$58 + connect \divisor_radicand$27 \core_calculate_stage_10_divisor_radicand$59 + connect \operation$28 \core_calculate_stage_10_operation$60 + connect \quotient_root$29 \core_calculate_stage_10_quotient_root$61 + connect \root_times_radicand$30 \core_calculate_stage_10_root_times_radicand$62 + connect \compare_lhs$31 \core_calculate_stage_10_compare_lhs$63 + connect \compare_rhs$32 \core_calculate_stage_10_compare_rhs$64 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_11_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_11_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_11_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_11_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_11_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_11_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_11_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_11_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_11_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_11_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_11_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_11_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_11_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_11_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_11_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_11_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_11_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_11_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_11_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_11_muxid$65 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_11_op__insn_type$66 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_11_op__fn_unit$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_11_op__imm_data__imm$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__imm_data__imm_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__lk$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__rc__rc_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__oe__oe_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__invert_a$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__zero_a$76 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_11_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_11_op__write_cr__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__write_cr__ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_11_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_11_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_11_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_11_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_11_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_11_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_11_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_11_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_11_divisor_radicand$91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_11_operation$92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_11_quotient_root$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_11_root_times_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_11_compare_lhs$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_11_compare_rhs$96 + cell \core_calculate_stage_11 \core_calculate_stage_11 + connect \muxid \core_calculate_stage_11_muxid + connect \op__insn_type \core_calculate_stage_11_op__insn_type + connect \op__fn_unit \core_calculate_stage_11_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_11_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_11_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_11_op__lk + connect \op__rc__rc \core_calculate_stage_11_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_11_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_11_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_11_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_11_op__invert_a + connect \op__zero_a \core_calculate_stage_11_op__zero_a + connect \op__input_carry \core_calculate_stage_11_op__input_carry + connect \op__invert_out \core_calculate_stage_11_op__invert_out + connect \op__write_cr__data \core_calculate_stage_11_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_11_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_11_op__output_carry + connect \op__is_32bit \core_calculate_stage_11_op__is_32bit + connect \op__is_signed \core_calculate_stage_11_op__is_signed + connect \op__data_len \core_calculate_stage_11_op__data_len + connect \op__insn \core_calculate_stage_11_op__insn + connect \ra \core_calculate_stage_11_ra + connect \rb \core_calculate_stage_11_rb + connect \xer_so \core_calculate_stage_11_xer_so + connect \divisor_neg \core_calculate_stage_11_divisor_neg + connect \dividend_neg \core_calculate_stage_11_dividend_neg + connect \divisor_radicand \core_calculate_stage_11_divisor_radicand + connect \operation \core_calculate_stage_11_operation + connect \quotient_root \core_calculate_stage_11_quotient_root + connect \root_times_radicand \core_calculate_stage_11_root_times_radicand + connect \compare_lhs \core_calculate_stage_11_compare_lhs + connect \compare_rhs \core_calculate_stage_11_compare_rhs + connect \muxid$1 \core_calculate_stage_11_muxid$65 + connect \op__insn_type$2 \core_calculate_stage_11_op__insn_type$66 + connect \op__fn_unit$3 \core_calculate_stage_11_op__fn_unit$67 + connect \op__imm_data__imm$4 \core_calculate_stage_11_op__imm_data__imm$68 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_11_op__imm_data__imm_ok$69 + connect \op__lk$6 \core_calculate_stage_11_op__lk$70 + connect \op__rc__rc$7 \core_calculate_stage_11_op__rc__rc$71 + connect \op__rc__rc_ok$8 \core_calculate_stage_11_op__rc__rc_ok$72 + connect \op__oe__oe$9 \core_calculate_stage_11_op__oe__oe$73 + connect \op__oe__oe_ok$10 \core_calculate_stage_11_op__oe__oe_ok$74 + connect \op__invert_a$11 \core_calculate_stage_11_op__invert_a$75 + connect \op__zero_a$12 \core_calculate_stage_11_op__zero_a$76 + connect \op__input_carry$13 \core_calculate_stage_11_op__input_carry$77 + connect \op__invert_out$14 \core_calculate_stage_11_op__invert_out$78 + connect \op__write_cr__data$15 \core_calculate_stage_11_op__write_cr__data$79 + connect \op__write_cr__ok$16 \core_calculate_stage_11_op__write_cr__ok$80 + connect \op__output_carry$17 \core_calculate_stage_11_op__output_carry$81 + connect \op__is_32bit$18 \core_calculate_stage_11_op__is_32bit$82 + connect \op__is_signed$19 \core_calculate_stage_11_op__is_signed$83 + connect \op__data_len$20 \core_calculate_stage_11_op__data_len$84 + connect \op__insn$21 \core_calculate_stage_11_op__insn$85 + connect \ra$22 \core_calculate_stage_11_ra$86 + connect \rb$23 \core_calculate_stage_11_rb$87 + connect \xer_so$24 \core_calculate_stage_11_xer_so$88 + connect \divisor_neg$25 \core_calculate_stage_11_divisor_neg$89 + connect \dividend_neg$26 \core_calculate_stage_11_dividend_neg$90 + connect \divisor_radicand$27 \core_calculate_stage_11_divisor_radicand$91 + connect \operation$28 \core_calculate_stage_11_operation$92 + connect \quotient_root$29 \core_calculate_stage_11_quotient_root$93 + connect \root_times_radicand$30 \core_calculate_stage_11_root_times_radicand$94 + connect \compare_lhs$31 \core_calculate_stage_11_compare_lhs$95 + connect \compare_rhs$32 \core_calculate_stage_11_compare_rhs$96 + end + process $group_0 + assign \core_calculate_stage_10_muxid 2'00 + assign \core_calculate_stage_10_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_10_op__insn_type 7'0000000 + assign \core_calculate_stage_10_op__fn_unit 10'0000000000 + assign \core_calculate_stage_10_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_10_op__lk 1'0 + assign \core_calculate_stage_10_op__rc__rc 1'0 + assign \core_calculate_stage_10_op__rc__rc_ok 1'0 + assign \core_calculate_stage_10_op__oe__oe 1'0 + assign \core_calculate_stage_10_op__oe__oe_ok 1'0 + assign \core_calculate_stage_10_op__invert_a 1'0 + assign \core_calculate_stage_10_op__zero_a 1'0 + assign \core_calculate_stage_10_op__input_carry 2'00 + assign \core_calculate_stage_10_op__invert_out 1'0 + assign \core_calculate_stage_10_op__write_cr__data 3'000 + assign \core_calculate_stage_10_op__write_cr__ok 1'0 + assign \core_calculate_stage_10_op__output_carry 1'0 + assign \core_calculate_stage_10_op__is_32bit 1'0 + assign \core_calculate_stage_10_op__is_signed 1'0 + assign \core_calculate_stage_10_op__data_len 4'0000 + assign \core_calculate_stage_10_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_10_op__insn \core_calculate_stage_10_op__data_len \core_calculate_stage_10_op__is_signed \core_calculate_stage_10_op__is_32bit \core_calculate_stage_10_op__output_carry { \core_calculate_stage_10_op__write_cr__ok \core_calculate_stage_10_op__write_cr__data } \core_calculate_stage_10_op__invert_out \core_calculate_stage_10_op__input_carry \core_calculate_stage_10_op__zero_a \core_calculate_stage_10_op__invert_a { \core_calculate_stage_10_op__oe__oe_ok \core_calculate_stage_10_op__oe__oe } { \core_calculate_stage_10_op__rc__rc_ok \core_calculate_stage_10_op__rc__rc } \core_calculate_stage_10_op__lk { \core_calculate_stage_10_op__imm_data__imm_ok \core_calculate_stage_10_op__imm_data__imm } \core_calculate_stage_10_op__fn_unit \core_calculate_stage_10_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \core_calculate_stage_10_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_ra \ra + sync init + end + process $group_22 + assign \core_calculate_stage_10_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_rb \rb + sync init + end + process $group_23 + assign \core_calculate_stage_10_xer_so 1'0 + assign \core_calculate_stage_10_xer_so \xer_so + sync init + end + process $group_24 + assign \core_calculate_stage_10_divisor_neg 1'0 + assign \core_calculate_stage_10_divisor_neg \divisor_neg + sync init + end + process $group_25 + assign \core_calculate_stage_10_dividend_neg 1'0 + assign \core_calculate_stage_10_dividend_neg \dividend_neg + sync init + end + process $group_26 + assign \core_calculate_stage_10_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_calculate_stage_10_operation 2'00 + assign \core_calculate_stage_10_operation \operation + sync init + end + process $group_28 + assign \core_calculate_stage_10_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_calculate_stage_10_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_calculate_stage_10_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_calculate_stage_10_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_10_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \core_calculate_stage_11_muxid 2'00 + assign \core_calculate_stage_11_muxid \core_calculate_stage_10_muxid$33 + sync init + end + process $group_33 + assign \core_calculate_stage_11_op__insn_type 7'0000000 + assign \core_calculate_stage_11_op__fn_unit 10'0000000000 + assign \core_calculate_stage_11_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_11_op__lk 1'0 + assign \core_calculate_stage_11_op__rc__rc 1'0 + assign \core_calculate_stage_11_op__rc__rc_ok 1'0 + assign \core_calculate_stage_11_op__oe__oe 1'0 + assign \core_calculate_stage_11_op__oe__oe_ok 1'0 + assign \core_calculate_stage_11_op__invert_a 1'0 + assign \core_calculate_stage_11_op__zero_a 1'0 + assign \core_calculate_stage_11_op__input_carry 2'00 + assign \core_calculate_stage_11_op__invert_out 1'0 + assign \core_calculate_stage_11_op__write_cr__data 3'000 + assign \core_calculate_stage_11_op__write_cr__ok 1'0 + assign \core_calculate_stage_11_op__output_carry 1'0 + assign \core_calculate_stage_11_op__is_32bit 1'0 + assign \core_calculate_stage_11_op__is_signed 1'0 + assign \core_calculate_stage_11_op__data_len 4'0000 + assign \core_calculate_stage_11_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_11_op__insn \core_calculate_stage_11_op__data_len \core_calculate_stage_11_op__is_signed \core_calculate_stage_11_op__is_32bit \core_calculate_stage_11_op__output_carry { \core_calculate_stage_11_op__write_cr__ok \core_calculate_stage_11_op__write_cr__data } \core_calculate_stage_11_op__invert_out \core_calculate_stage_11_op__input_carry \core_calculate_stage_11_op__zero_a \core_calculate_stage_11_op__invert_a { \core_calculate_stage_11_op__oe__oe_ok \core_calculate_stage_11_op__oe__oe } { \core_calculate_stage_11_op__rc__rc_ok \core_calculate_stage_11_op__rc__rc } \core_calculate_stage_11_op__lk { \core_calculate_stage_11_op__imm_data__imm_ok \core_calculate_stage_11_op__imm_data__imm } \core_calculate_stage_11_op__fn_unit \core_calculate_stage_11_op__insn_type } { \core_calculate_stage_10_op__insn$53 \core_calculate_stage_10_op__data_len$52 \core_calculate_stage_10_op__is_signed$51 \core_calculate_stage_10_op__is_32bit$50 \core_calculate_stage_10_op__output_carry$49 { \core_calculate_stage_10_op__write_cr__ok$48 \core_calculate_stage_10_op__write_cr__data$47 } \core_calculate_stage_10_op__invert_out$46 \core_calculate_stage_10_op__input_carry$45 \core_calculate_stage_10_op__zero_a$44 \core_calculate_stage_10_op__invert_a$43 { \core_calculate_stage_10_op__oe__oe_ok$42 \core_calculate_stage_10_op__oe__oe$41 } { \core_calculate_stage_10_op__rc__rc_ok$40 \core_calculate_stage_10_op__rc__rc$39 } \core_calculate_stage_10_op__lk$38 { \core_calculate_stage_10_op__imm_data__imm_ok$37 \core_calculate_stage_10_op__imm_data__imm$36 } \core_calculate_stage_10_op__fn_unit$35 \core_calculate_stage_10_op__insn_type$34 } + sync init + end + process $group_53 + assign \core_calculate_stage_11_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_ra \core_calculate_stage_10_ra$54 + sync init + end + process $group_54 + assign \core_calculate_stage_11_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_rb \core_calculate_stage_10_rb$55 + sync init + end + process $group_55 + assign \core_calculate_stage_11_xer_so 1'0 + assign \core_calculate_stage_11_xer_so \core_calculate_stage_10_xer_so$56 + sync init + end + process $group_56 + assign \core_calculate_stage_11_divisor_neg 1'0 + assign \core_calculate_stage_11_divisor_neg \core_calculate_stage_10_divisor_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_11_dividend_neg 1'0 + assign \core_calculate_stage_11_dividend_neg \core_calculate_stage_10_dividend_neg$58 + sync init + end + process $group_58 + assign \core_calculate_stage_11_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_divisor_radicand \core_calculate_stage_10_divisor_radicand$59 + sync init + end + process $group_59 + assign \core_calculate_stage_11_operation 2'00 + assign \core_calculate_stage_11_operation \core_calculate_stage_10_operation$60 + sync init + end + process $group_60 + assign \core_calculate_stage_11_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_quotient_root \core_calculate_stage_10_quotient_root$61 + sync init + end + process $group_61 + assign \core_calculate_stage_11_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_root_times_radicand \core_calculate_stage_10_root_times_radicand$62 + sync init + end + process $group_62 + assign \core_calculate_stage_11_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_compare_lhs \core_calculate_stage_10_compare_lhs$63 + sync init + end + process $group_63 + assign \core_calculate_stage_11_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_11_compare_rhs \core_calculate_stage_10_compare_rhs$64 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$97 + process $group_64 + assign \p_valid_i$97 1'0 + assign \p_valid_i$97 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_65 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $98 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$97 + connect \B \p_ready_o + connect \Y $98 + end + process $group_66 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $98 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$100 + process $group_67 + assign \muxid$100 2'00 + assign \muxid$100 \core_calculate_stage_11_muxid$65 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$111 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$120 + process $group_68 + assign \op__insn_type$101 7'0000000 + assign \op__fn_unit$102 10'0000000000 + assign \op__imm_data__imm$103 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$104 1'0 + assign \op__lk$105 1'0 + assign \op__rc__rc$106 1'0 + assign \op__rc__rc_ok$107 1'0 + assign \op__oe__oe$108 1'0 + assign \op__oe__oe_ok$109 1'0 + assign \op__invert_a$110 1'0 + assign \op__zero_a$111 1'0 + assign \op__input_carry$112 2'00 + assign \op__invert_out$113 1'0 + assign \op__write_cr__data$114 3'000 + assign \op__write_cr__ok$115 1'0 + assign \op__output_carry$116 1'0 + assign \op__is_32bit$117 1'0 + assign \op__is_signed$118 1'0 + assign \op__data_len$119 4'0000 + assign \op__insn$120 32'00000000000000000000000000000000 + assign { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } { \core_calculate_stage_11_op__insn$85 \core_calculate_stage_11_op__data_len$84 \core_calculate_stage_11_op__is_signed$83 \core_calculate_stage_11_op__is_32bit$82 \core_calculate_stage_11_op__output_carry$81 { \core_calculate_stage_11_op__write_cr__ok$80 \core_calculate_stage_11_op__write_cr__data$79 } \core_calculate_stage_11_op__invert_out$78 \core_calculate_stage_11_op__input_carry$77 \core_calculate_stage_11_op__zero_a$76 \core_calculate_stage_11_op__invert_a$75 { \core_calculate_stage_11_op__oe__oe_ok$74 \core_calculate_stage_11_op__oe__oe$73 } { \core_calculate_stage_11_op__rc__rc_ok$72 \core_calculate_stage_11_op__rc__rc$71 } \core_calculate_stage_11_op__lk$70 { \core_calculate_stage_11_op__imm_data__imm_ok$69 \core_calculate_stage_11_op__imm_data__imm$68 } \core_calculate_stage_11_op__fn_unit$67 \core_calculate_stage_11_op__insn_type$66 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$121 + process $group_88 + assign \ra$121 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$121 \core_calculate_stage_11_ra$86 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$122 + process $group_89 + assign \rb$122 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$122 \core_calculate_stage_11_rb$87 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$123 + process $group_90 + assign \xer_so$123 1'0 + assign \xer_so$123 \core_calculate_stage_11_xer_so$88 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$124 + process $group_91 + assign \divisor_neg$124 1'0 + assign \divisor_neg$124 \core_calculate_stage_11_divisor_neg$89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$125 + process $group_92 + assign \dividend_neg$125 1'0 + assign \dividend_neg$125 \core_calculate_stage_11_dividend_neg$90 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$126 + process $group_93 + assign \divisor_radicand$126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$126 \core_calculate_stage_11_divisor_radicand$91 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$127 + process $group_94 + assign \operation$127 2'00 + assign \operation$127 \core_calculate_stage_11_operation$92 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$128 + process $group_95 + assign \quotient_root$128 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$128 \core_calculate_stage_11_quotient_root$93 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$129 + process $group_96 + assign \root_times_radicand$129 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$129 \core_calculate_stage_11_root_times_radicand$94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$130 + process $group_97 + assign \compare_lhs$130 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$130 \core_calculate_stage_11_compare_lhs$95 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$131 + process $group_98 + assign \compare_rhs$131 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$131 \core_calculate_stage_11_compare_rhs$96 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_99 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_100 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$100 + end + sync init + update \muxid$1 2'00 + sync posedge \clk + update \muxid$1 \muxid$1$next + end + process $group_101 + assign \op__insn_type$2$next \op__insn_type$2 + assign \op__fn_unit$3$next \op__fn_unit$3 + assign \op__imm_data__imm$4$next \op__imm_data__imm$4 + assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5 + assign \op__lk$6$next \op__lk$6 + assign \op__rc__rc$7$next \op__rc__rc$7 + assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8 + assign \op__oe__oe$9$next \op__oe__oe$9 + assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10 + assign \op__invert_a$11$next \op__invert_a$11 + assign \op__zero_a$12$next \op__zero_a$12 + assign \op__input_carry$13$next \op__input_carry$13 + assign \op__invert_out$14$next \op__invert_out$14 + assign \op__write_cr__data$15$next \op__write_cr__data$15 + assign \op__write_cr__ok$16$next \op__write_cr__ok$16 + assign \op__output_carry$17$next \op__output_carry$17 + assign \op__is_32bit$18$next \op__is_32bit$18 + assign \op__is_signed$19$next \op__is_signed$19 + assign \op__data_len$20$next \op__data_len$20 + assign \op__insn$21$next \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5$next 1'0 + assign \op__rc__rc$7$next 1'0 + assign \op__rc__rc_ok$8$next 1'0 + assign \op__oe__oe$9$next 1'0 + assign \op__oe__oe_ok$10$next 1'0 + assign \op__write_cr__data$15$next 3'000 + assign \op__write_cr__ok$16$next 1'0 + assign \op__insn$21$next 32'00000000000000000000000000000000 + end + sync init + update \op__insn_type$2 7'0000000 + update \op__fn_unit$3 10'0000000000 + update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \op__imm_data__imm_ok$5 1'0 + update \op__lk$6 1'0 + update \op__rc__rc$7 1'0 + update \op__rc__rc_ok$8 1'0 + update \op__oe__oe$9 1'0 + update \op__oe__oe_ok$10 1'0 + update \op__invert_a$11 1'0 + update \op__zero_a$12 1'0 + update \op__input_carry$13 2'00 + update \op__invert_out$14 1'0 + update \op__write_cr__data$15 3'000 + update \op__write_cr__ok$16 1'0 + update \op__output_carry$17 1'0 + update \op__is_32bit$18 1'0 + update \op__is_signed$19 1'0 + update \op__data_len$20 4'0000 + update \op__insn$21 32'00000000000000000000000000000000 + sync posedge \clk + update \op__insn_type$2 \op__insn_type$2$next + update \op__fn_unit$3 \op__fn_unit$3$next + update \op__imm_data__imm$4 \op__imm_data__imm$4$next + update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next + update \op__lk$6 \op__lk$6$next + update \op__rc__rc$7 \op__rc__rc$7$next + update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next + update \op__oe__oe$9 \op__oe__oe$9$next + update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next + update \op__invert_a$11 \op__invert_a$11$next + update \op__zero_a$12 \op__zero_a$12$next + update \op__input_carry$13 \op__input_carry$13$next + update \op__invert_out$14 \op__invert_out$14$next + update \op__write_cr__data$15 \op__write_cr__data$15$next + update \op__write_cr__ok$16 \op__write_cr__ok$16$next + update \op__output_carry$17 \op__output_carry$17$next + update \op__is_32bit$18 \op__is_32bit$18$next + update \op__is_signed$19 \op__is_signed$19$next + update \op__data_len$20 \op__data_len$20$next + update \op__insn$21 \op__insn$21$next + end + process $group_121 + assign \ra$22$next \ra$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$22$next \ra$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$22$next \ra$121 + end + sync init + update \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \ra$22 \ra$22$next + end + process $group_122 + assign \rb$23$next \rb$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$23$next \rb$122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$23$next \rb$122 + end + sync init + update \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \rb$23 \rb$23$next + end + process $group_123 + assign \xer_so$24$next \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$24$next \xer_so$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$24$next \xer_so$123 + end + sync init + update \xer_so$24 1'0 + sync posedge \clk + update \xer_so$24 \xer_so$24$next + end + process $group_124 + assign \divisor_neg$25$next \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$25$next \divisor_neg$124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$25$next \divisor_neg$124 + end + sync init + update \divisor_neg$25 1'0 + sync posedge \clk + update \divisor_neg$25 \divisor_neg$25$next + end + process $group_125 + assign \dividend_neg$26$next \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$26$next \dividend_neg$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$26$next \dividend_neg$125 + end + sync init + update \dividend_neg$26 1'0 + sync posedge \clk + update \dividend_neg$26 \dividend_neg$26$next + end + process $group_126 + assign \divisor_radicand$27$next \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$27$next \divisor_radicand$126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$27$next \divisor_radicand$126 + end + sync init + update \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \divisor_radicand$27 \divisor_radicand$27$next + end + process $group_127 + assign \operation$28$next \operation$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$28$next \operation$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$28$next \operation$127 + end + sync init + update \operation$28 2'00 + sync posedge \clk + update \operation$28 \operation$28$next + end + process $group_128 + assign \quotient_root$29$next \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$29$next \quotient_root$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$29$next \quotient_root$128 + end + sync init + update \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \quotient_root$29 \quotient_root$29$next + end + process $group_129 + assign \root_times_radicand$30$next \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$30$next \root_times_radicand$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$30$next \root_times_radicand$129 + end + sync init + update \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \root_times_radicand$30 \root_times_radicand$30$next + end + process $group_130 + assign \compare_lhs$31$next \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$31$next \compare_lhs$130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$31$next \compare_lhs$130 + end + sync init + update \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_lhs$31 \compare_lhs$31$next + end + process $group_131 + assign \compare_rhs$32$next \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$32$next \compare_rhs$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$32$next \compare_rhs$131 + end + sync init + update \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_rhs$32 \compare_rhs$32$next + end + process $group_132 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_133 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.p" +module \p$175 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.n" +module \n$176 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_12.core.trial0" +module \trial0$178 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000000 + connect \B 7'1110010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'110010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_12.core.trial1" +module \trial1$179 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000001 + connect \B 7'1110010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'110010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_12.core.trial2" +module \trial2$180 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000100 + connect \B 7'1110010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'110010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_12.core.trial3" +module \trial3$181 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'001001 + connect \B 7'1110010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'110010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_12.core.trial4" +module \trial4$182 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'010000 + connect \B 7'1110010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'110010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_12.core.trial5" +module \trial5$183 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'011001 + connect \B 7'1110010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'110010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_12.core.trial6" +module \trial6$184 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'100100 + connect \B 7'1110010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'110010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_12.core.trial7" +module \trial7$185 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1011001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1011010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'110001 + connect \B 7'1110010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'11010 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'110010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_12.core.pe" +module \pe$186 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_12.core" +module \core$177 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$178 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$179 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$180 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$181 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$182 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$183 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$184 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$185 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$186 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 34 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 34 + connect \A \next_bits + connect \B 5'11001 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 34 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 98 $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 98 + connect \A $35 + connect \B 5'11001 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 98 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B $37 + connect \Y $39 + end + connect $34 $39 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $34 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_12" +module \core_calculate_stage_12 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$177 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_13.core.trial0" +module \trial0$188 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000000 + connect \B 7'1101100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'101100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_13.core.trial1" +module \trial1$189 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000001 + connect \B 7'1101100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'101100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_13.core.trial2" +module \trial2$190 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000100 + connect \B 7'1101100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'101100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_13.core.trial3" +module \trial3$191 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'001001 + connect \B 7'1101100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'101100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_13.core.trial4" +module \trial4$192 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'010000 + connect \B 7'1101100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'101100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_13.core.trial5" +module \trial5$193 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'011001 + connect \B 7'1101100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'101100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_13.core.trial6" +module \trial6$194 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'100100 + connect \B 7'1101100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'101100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_13.core.trial7" +module \trial7$195 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010110 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010111 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'110001 + connect \B 7'1101100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10111 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'101100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_13.core.pe" +module \pe$196 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_13.core" +module \core$187 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$188 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$189 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$190 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$191 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$192 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$193 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$194 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$195 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$196 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 34 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 34 + connect \A \next_bits + connect \B 5'10110 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 34 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 98 $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 98 + connect \A $35 + connect \B 5'10110 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 98 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B $37 + connect \Y $39 + end + connect $34 $39 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $34 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14.core_calculate_stage_13" +module \core_calculate_stage_13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$187 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_12_to_14" +module \pipe_12_to_14 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 4 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 5 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 7 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 16 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 18 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 20 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 21 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 22 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 23 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 24 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 25 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 26 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 28 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 29 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 30 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 31 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 32 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 33 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 34 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 35 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 36 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 37 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 38 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$1$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 39 \op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 40 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 41 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 46 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 50 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 51 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 52 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 53 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 54 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 55 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 56 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 57 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 58 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 59 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 60 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 61 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 62 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 63 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$26$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 64 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 65 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 66 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 67 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 68 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 69 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$32$next + cell \p$175 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$176 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_12_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_12_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_12_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_12_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_12_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_12_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_12_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_12_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_12_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_12_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_12_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_12_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_12_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_12_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_12_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_12_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_12_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_12_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_12_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_12_muxid$33 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_12_op__insn_type$34 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_12_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_12_op__imm_data__imm$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__imm_data__imm_ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__lk$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__invert_a$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_12_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_12_op__write_cr__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__write_cr__ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__output_carry$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__is_32bit$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_12_op__is_signed$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_12_op__data_len$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_12_op__insn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_12_ra$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_12_rb$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_12_xer_so$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_12_divisor_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_12_dividend_neg$58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_12_divisor_radicand$59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_12_operation$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_12_quotient_root$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_12_root_times_radicand$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_12_compare_lhs$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_12_compare_rhs$64 + cell \core_calculate_stage_12 \core_calculate_stage_12 + connect \muxid \core_calculate_stage_12_muxid + connect \op__insn_type \core_calculate_stage_12_op__insn_type + connect \op__fn_unit \core_calculate_stage_12_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_12_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_12_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_12_op__lk + connect \op__rc__rc \core_calculate_stage_12_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_12_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_12_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_12_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_12_op__invert_a + connect \op__zero_a \core_calculate_stage_12_op__zero_a + connect \op__input_carry \core_calculate_stage_12_op__input_carry + connect \op__invert_out \core_calculate_stage_12_op__invert_out + connect \op__write_cr__data \core_calculate_stage_12_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_12_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_12_op__output_carry + connect \op__is_32bit \core_calculate_stage_12_op__is_32bit + connect \op__is_signed \core_calculate_stage_12_op__is_signed + connect \op__data_len \core_calculate_stage_12_op__data_len + connect \op__insn \core_calculate_stage_12_op__insn + connect \ra \core_calculate_stage_12_ra + connect \rb \core_calculate_stage_12_rb + connect \xer_so \core_calculate_stage_12_xer_so + connect \divisor_neg \core_calculate_stage_12_divisor_neg + connect \dividend_neg \core_calculate_stage_12_dividend_neg + connect \divisor_radicand \core_calculate_stage_12_divisor_radicand + connect \operation \core_calculate_stage_12_operation + connect \quotient_root \core_calculate_stage_12_quotient_root + connect \root_times_radicand \core_calculate_stage_12_root_times_radicand + connect \compare_lhs \core_calculate_stage_12_compare_lhs + connect \compare_rhs \core_calculate_stage_12_compare_rhs + connect \muxid$1 \core_calculate_stage_12_muxid$33 + connect \op__insn_type$2 \core_calculate_stage_12_op__insn_type$34 + connect \op__fn_unit$3 \core_calculate_stage_12_op__fn_unit$35 + connect \op__imm_data__imm$4 \core_calculate_stage_12_op__imm_data__imm$36 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_12_op__imm_data__imm_ok$37 + connect \op__lk$6 \core_calculate_stage_12_op__lk$38 + connect \op__rc__rc$7 \core_calculate_stage_12_op__rc__rc$39 + connect \op__rc__rc_ok$8 \core_calculate_stage_12_op__rc__rc_ok$40 + connect \op__oe__oe$9 \core_calculate_stage_12_op__oe__oe$41 + connect \op__oe__oe_ok$10 \core_calculate_stage_12_op__oe__oe_ok$42 + connect \op__invert_a$11 \core_calculate_stage_12_op__invert_a$43 + connect \op__zero_a$12 \core_calculate_stage_12_op__zero_a$44 + connect \op__input_carry$13 \core_calculate_stage_12_op__input_carry$45 + connect \op__invert_out$14 \core_calculate_stage_12_op__invert_out$46 + connect \op__write_cr__data$15 \core_calculate_stage_12_op__write_cr__data$47 + connect \op__write_cr__ok$16 \core_calculate_stage_12_op__write_cr__ok$48 + connect \op__output_carry$17 \core_calculate_stage_12_op__output_carry$49 + connect \op__is_32bit$18 \core_calculate_stage_12_op__is_32bit$50 + connect \op__is_signed$19 \core_calculate_stage_12_op__is_signed$51 + connect \op__data_len$20 \core_calculate_stage_12_op__data_len$52 + connect \op__insn$21 \core_calculate_stage_12_op__insn$53 + connect \ra$22 \core_calculate_stage_12_ra$54 + connect \rb$23 \core_calculate_stage_12_rb$55 + connect \xer_so$24 \core_calculate_stage_12_xer_so$56 + connect \divisor_neg$25 \core_calculate_stage_12_divisor_neg$57 + connect \dividend_neg$26 \core_calculate_stage_12_dividend_neg$58 + connect \divisor_radicand$27 \core_calculate_stage_12_divisor_radicand$59 + connect \operation$28 \core_calculate_stage_12_operation$60 + connect \quotient_root$29 \core_calculate_stage_12_quotient_root$61 + connect \root_times_radicand$30 \core_calculate_stage_12_root_times_radicand$62 + connect \compare_lhs$31 \core_calculate_stage_12_compare_lhs$63 + connect \compare_rhs$32 \core_calculate_stage_12_compare_rhs$64 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_13_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_13_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_13_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_13_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_13_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_13_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_13_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_13_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_13_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_13_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_13_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_13_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_13_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_13_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_13_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_13_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_13_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_13_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_13_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_13_muxid$65 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_13_op__insn_type$66 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_13_op__fn_unit$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_13_op__imm_data__imm$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__imm_data__imm_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__lk$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__rc__rc_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__oe__oe_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__invert_a$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__zero_a$76 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_13_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_13_op__write_cr__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__write_cr__ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_13_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_13_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_13_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_13_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_13_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_13_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_13_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_13_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_13_divisor_radicand$91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_13_operation$92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_13_quotient_root$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_13_root_times_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_13_compare_lhs$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_13_compare_rhs$96 + cell \core_calculate_stage_13 \core_calculate_stage_13 + connect \muxid \core_calculate_stage_13_muxid + connect \op__insn_type \core_calculate_stage_13_op__insn_type + connect \op__fn_unit \core_calculate_stage_13_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_13_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_13_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_13_op__lk + connect \op__rc__rc \core_calculate_stage_13_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_13_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_13_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_13_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_13_op__invert_a + connect \op__zero_a \core_calculate_stage_13_op__zero_a + connect \op__input_carry \core_calculate_stage_13_op__input_carry + connect \op__invert_out \core_calculate_stage_13_op__invert_out + connect \op__write_cr__data \core_calculate_stage_13_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_13_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_13_op__output_carry + connect \op__is_32bit \core_calculate_stage_13_op__is_32bit + connect \op__is_signed \core_calculate_stage_13_op__is_signed + connect \op__data_len \core_calculate_stage_13_op__data_len + connect \op__insn \core_calculate_stage_13_op__insn + connect \ra \core_calculate_stage_13_ra + connect \rb \core_calculate_stage_13_rb + connect \xer_so \core_calculate_stage_13_xer_so + connect \divisor_neg \core_calculate_stage_13_divisor_neg + connect \dividend_neg \core_calculate_stage_13_dividend_neg + connect \divisor_radicand \core_calculate_stage_13_divisor_radicand + connect \operation \core_calculate_stage_13_operation + connect \quotient_root \core_calculate_stage_13_quotient_root + connect \root_times_radicand \core_calculate_stage_13_root_times_radicand + connect \compare_lhs \core_calculate_stage_13_compare_lhs + connect \compare_rhs \core_calculate_stage_13_compare_rhs + connect \muxid$1 \core_calculate_stage_13_muxid$65 + connect \op__insn_type$2 \core_calculate_stage_13_op__insn_type$66 + connect \op__fn_unit$3 \core_calculate_stage_13_op__fn_unit$67 + connect \op__imm_data__imm$4 \core_calculate_stage_13_op__imm_data__imm$68 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_13_op__imm_data__imm_ok$69 + connect \op__lk$6 \core_calculate_stage_13_op__lk$70 + connect \op__rc__rc$7 \core_calculate_stage_13_op__rc__rc$71 + connect \op__rc__rc_ok$8 \core_calculate_stage_13_op__rc__rc_ok$72 + connect \op__oe__oe$9 \core_calculate_stage_13_op__oe__oe$73 + connect \op__oe__oe_ok$10 \core_calculate_stage_13_op__oe__oe_ok$74 + connect \op__invert_a$11 \core_calculate_stage_13_op__invert_a$75 + connect \op__zero_a$12 \core_calculate_stage_13_op__zero_a$76 + connect \op__input_carry$13 \core_calculate_stage_13_op__input_carry$77 + connect \op__invert_out$14 \core_calculate_stage_13_op__invert_out$78 + connect \op__write_cr__data$15 \core_calculate_stage_13_op__write_cr__data$79 + connect \op__write_cr__ok$16 \core_calculate_stage_13_op__write_cr__ok$80 + connect \op__output_carry$17 \core_calculate_stage_13_op__output_carry$81 + connect \op__is_32bit$18 \core_calculate_stage_13_op__is_32bit$82 + connect \op__is_signed$19 \core_calculate_stage_13_op__is_signed$83 + connect \op__data_len$20 \core_calculate_stage_13_op__data_len$84 + connect \op__insn$21 \core_calculate_stage_13_op__insn$85 + connect \ra$22 \core_calculate_stage_13_ra$86 + connect \rb$23 \core_calculate_stage_13_rb$87 + connect \xer_so$24 \core_calculate_stage_13_xer_so$88 + connect \divisor_neg$25 \core_calculate_stage_13_divisor_neg$89 + connect \dividend_neg$26 \core_calculate_stage_13_dividend_neg$90 + connect \divisor_radicand$27 \core_calculate_stage_13_divisor_radicand$91 + connect \operation$28 \core_calculate_stage_13_operation$92 + connect \quotient_root$29 \core_calculate_stage_13_quotient_root$93 + connect \root_times_radicand$30 \core_calculate_stage_13_root_times_radicand$94 + connect \compare_lhs$31 \core_calculate_stage_13_compare_lhs$95 + connect \compare_rhs$32 \core_calculate_stage_13_compare_rhs$96 + end + process $group_0 + assign \core_calculate_stage_12_muxid 2'00 + assign \core_calculate_stage_12_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_12_op__insn_type 7'0000000 + assign \core_calculate_stage_12_op__fn_unit 10'0000000000 + assign \core_calculate_stage_12_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_12_op__lk 1'0 + assign \core_calculate_stage_12_op__rc__rc 1'0 + assign \core_calculate_stage_12_op__rc__rc_ok 1'0 + assign \core_calculate_stage_12_op__oe__oe 1'0 + assign \core_calculate_stage_12_op__oe__oe_ok 1'0 + assign \core_calculate_stage_12_op__invert_a 1'0 + assign \core_calculate_stage_12_op__zero_a 1'0 + assign \core_calculate_stage_12_op__input_carry 2'00 + assign \core_calculate_stage_12_op__invert_out 1'0 + assign \core_calculate_stage_12_op__write_cr__data 3'000 + assign \core_calculate_stage_12_op__write_cr__ok 1'0 + assign \core_calculate_stage_12_op__output_carry 1'0 + assign \core_calculate_stage_12_op__is_32bit 1'0 + assign \core_calculate_stage_12_op__is_signed 1'0 + assign \core_calculate_stage_12_op__data_len 4'0000 + assign \core_calculate_stage_12_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_12_op__insn \core_calculate_stage_12_op__data_len \core_calculate_stage_12_op__is_signed \core_calculate_stage_12_op__is_32bit \core_calculate_stage_12_op__output_carry { \core_calculate_stage_12_op__write_cr__ok \core_calculate_stage_12_op__write_cr__data } \core_calculate_stage_12_op__invert_out \core_calculate_stage_12_op__input_carry \core_calculate_stage_12_op__zero_a \core_calculate_stage_12_op__invert_a { \core_calculate_stage_12_op__oe__oe_ok \core_calculate_stage_12_op__oe__oe } { \core_calculate_stage_12_op__rc__rc_ok \core_calculate_stage_12_op__rc__rc } \core_calculate_stage_12_op__lk { \core_calculate_stage_12_op__imm_data__imm_ok \core_calculate_stage_12_op__imm_data__imm } \core_calculate_stage_12_op__fn_unit \core_calculate_stage_12_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \core_calculate_stage_12_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_ra \ra + sync init + end + process $group_22 + assign \core_calculate_stage_12_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_rb \rb + sync init + end + process $group_23 + assign \core_calculate_stage_12_xer_so 1'0 + assign \core_calculate_stage_12_xer_so \xer_so + sync init + end + process $group_24 + assign \core_calculate_stage_12_divisor_neg 1'0 + assign \core_calculate_stage_12_divisor_neg \divisor_neg + sync init + end + process $group_25 + assign \core_calculate_stage_12_dividend_neg 1'0 + assign \core_calculate_stage_12_dividend_neg \dividend_neg + sync init + end + process $group_26 + assign \core_calculate_stage_12_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_calculate_stage_12_operation 2'00 + assign \core_calculate_stage_12_operation \operation + sync init + end + process $group_28 + assign \core_calculate_stage_12_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_calculate_stage_12_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_calculate_stage_12_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_calculate_stage_12_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_12_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \core_calculate_stage_13_muxid 2'00 + assign \core_calculate_stage_13_muxid \core_calculate_stage_12_muxid$33 + sync init + end + process $group_33 + assign \core_calculate_stage_13_op__insn_type 7'0000000 + assign \core_calculate_stage_13_op__fn_unit 10'0000000000 + assign \core_calculate_stage_13_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_13_op__lk 1'0 + assign \core_calculate_stage_13_op__rc__rc 1'0 + assign \core_calculate_stage_13_op__rc__rc_ok 1'0 + assign \core_calculate_stage_13_op__oe__oe 1'0 + assign \core_calculate_stage_13_op__oe__oe_ok 1'0 + assign \core_calculate_stage_13_op__invert_a 1'0 + assign \core_calculate_stage_13_op__zero_a 1'0 + assign \core_calculate_stage_13_op__input_carry 2'00 + assign \core_calculate_stage_13_op__invert_out 1'0 + assign \core_calculate_stage_13_op__write_cr__data 3'000 + assign \core_calculate_stage_13_op__write_cr__ok 1'0 + assign \core_calculate_stage_13_op__output_carry 1'0 + assign \core_calculate_stage_13_op__is_32bit 1'0 + assign \core_calculate_stage_13_op__is_signed 1'0 + assign \core_calculate_stage_13_op__data_len 4'0000 + assign \core_calculate_stage_13_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_13_op__insn \core_calculate_stage_13_op__data_len \core_calculate_stage_13_op__is_signed \core_calculate_stage_13_op__is_32bit \core_calculate_stage_13_op__output_carry { \core_calculate_stage_13_op__write_cr__ok \core_calculate_stage_13_op__write_cr__data } \core_calculate_stage_13_op__invert_out \core_calculate_stage_13_op__input_carry \core_calculate_stage_13_op__zero_a \core_calculate_stage_13_op__invert_a { \core_calculate_stage_13_op__oe__oe_ok \core_calculate_stage_13_op__oe__oe } { \core_calculate_stage_13_op__rc__rc_ok \core_calculate_stage_13_op__rc__rc } \core_calculate_stage_13_op__lk { \core_calculate_stage_13_op__imm_data__imm_ok \core_calculate_stage_13_op__imm_data__imm } \core_calculate_stage_13_op__fn_unit \core_calculate_stage_13_op__insn_type } { \core_calculate_stage_12_op__insn$53 \core_calculate_stage_12_op__data_len$52 \core_calculate_stage_12_op__is_signed$51 \core_calculate_stage_12_op__is_32bit$50 \core_calculate_stage_12_op__output_carry$49 { \core_calculate_stage_12_op__write_cr__ok$48 \core_calculate_stage_12_op__write_cr__data$47 } \core_calculate_stage_12_op__invert_out$46 \core_calculate_stage_12_op__input_carry$45 \core_calculate_stage_12_op__zero_a$44 \core_calculate_stage_12_op__invert_a$43 { \core_calculate_stage_12_op__oe__oe_ok$42 \core_calculate_stage_12_op__oe__oe$41 } { \core_calculate_stage_12_op__rc__rc_ok$40 \core_calculate_stage_12_op__rc__rc$39 } \core_calculate_stage_12_op__lk$38 { \core_calculate_stage_12_op__imm_data__imm_ok$37 \core_calculate_stage_12_op__imm_data__imm$36 } \core_calculate_stage_12_op__fn_unit$35 \core_calculate_stage_12_op__insn_type$34 } + sync init + end + process $group_53 + assign \core_calculate_stage_13_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_ra \core_calculate_stage_12_ra$54 + sync init + end + process $group_54 + assign \core_calculate_stage_13_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_rb \core_calculate_stage_12_rb$55 + sync init + end + process $group_55 + assign \core_calculate_stage_13_xer_so 1'0 + assign \core_calculate_stage_13_xer_so \core_calculate_stage_12_xer_so$56 + sync init + end + process $group_56 + assign \core_calculate_stage_13_divisor_neg 1'0 + assign \core_calculate_stage_13_divisor_neg \core_calculate_stage_12_divisor_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_13_dividend_neg 1'0 + assign \core_calculate_stage_13_dividend_neg \core_calculate_stage_12_dividend_neg$58 + sync init + end + process $group_58 + assign \core_calculate_stage_13_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_divisor_radicand \core_calculate_stage_12_divisor_radicand$59 + sync init + end + process $group_59 + assign \core_calculate_stage_13_operation 2'00 + assign \core_calculate_stage_13_operation \core_calculate_stage_12_operation$60 + sync init + end + process $group_60 + assign \core_calculate_stage_13_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_quotient_root \core_calculate_stage_12_quotient_root$61 + sync init + end + process $group_61 + assign \core_calculate_stage_13_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_root_times_radicand \core_calculate_stage_12_root_times_radicand$62 + sync init + end + process $group_62 + assign \core_calculate_stage_13_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_compare_lhs \core_calculate_stage_12_compare_lhs$63 + sync init + end + process $group_63 + assign \core_calculate_stage_13_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_13_compare_rhs \core_calculate_stage_12_compare_rhs$64 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$97 + process $group_64 + assign \p_valid_i$97 1'0 + assign \p_valid_i$97 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_65 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $98 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$97 + connect \B \p_ready_o + connect \Y $98 + end + process $group_66 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $98 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$100 + process $group_67 + assign \muxid$100 2'00 + assign \muxid$100 \core_calculate_stage_13_muxid$65 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$111 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$120 + process $group_68 + assign \op__insn_type$101 7'0000000 + assign \op__fn_unit$102 10'0000000000 + assign \op__imm_data__imm$103 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$104 1'0 + assign \op__lk$105 1'0 + assign \op__rc__rc$106 1'0 + assign \op__rc__rc_ok$107 1'0 + assign \op__oe__oe$108 1'0 + assign \op__oe__oe_ok$109 1'0 + assign \op__invert_a$110 1'0 + assign \op__zero_a$111 1'0 + assign \op__input_carry$112 2'00 + assign \op__invert_out$113 1'0 + assign \op__write_cr__data$114 3'000 + assign \op__write_cr__ok$115 1'0 + assign \op__output_carry$116 1'0 + assign \op__is_32bit$117 1'0 + assign \op__is_signed$118 1'0 + assign \op__data_len$119 4'0000 + assign \op__insn$120 32'00000000000000000000000000000000 + assign { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } { \core_calculate_stage_13_op__insn$85 \core_calculate_stage_13_op__data_len$84 \core_calculate_stage_13_op__is_signed$83 \core_calculate_stage_13_op__is_32bit$82 \core_calculate_stage_13_op__output_carry$81 { \core_calculate_stage_13_op__write_cr__ok$80 \core_calculate_stage_13_op__write_cr__data$79 } \core_calculate_stage_13_op__invert_out$78 \core_calculate_stage_13_op__input_carry$77 \core_calculate_stage_13_op__zero_a$76 \core_calculate_stage_13_op__invert_a$75 { \core_calculate_stage_13_op__oe__oe_ok$74 \core_calculate_stage_13_op__oe__oe$73 } { \core_calculate_stage_13_op__rc__rc_ok$72 \core_calculate_stage_13_op__rc__rc$71 } \core_calculate_stage_13_op__lk$70 { \core_calculate_stage_13_op__imm_data__imm_ok$69 \core_calculate_stage_13_op__imm_data__imm$68 } \core_calculate_stage_13_op__fn_unit$67 \core_calculate_stage_13_op__insn_type$66 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$121 + process $group_88 + assign \ra$121 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$121 \core_calculate_stage_13_ra$86 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$122 + process $group_89 + assign \rb$122 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$122 \core_calculate_stage_13_rb$87 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$123 + process $group_90 + assign \xer_so$123 1'0 + assign \xer_so$123 \core_calculate_stage_13_xer_so$88 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$124 + process $group_91 + assign \divisor_neg$124 1'0 + assign \divisor_neg$124 \core_calculate_stage_13_divisor_neg$89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$125 + process $group_92 + assign \dividend_neg$125 1'0 + assign \dividend_neg$125 \core_calculate_stage_13_dividend_neg$90 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$126 + process $group_93 + assign \divisor_radicand$126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$126 \core_calculate_stage_13_divisor_radicand$91 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$127 + process $group_94 + assign \operation$127 2'00 + assign \operation$127 \core_calculate_stage_13_operation$92 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$128 + process $group_95 + assign \quotient_root$128 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$128 \core_calculate_stage_13_quotient_root$93 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$129 + process $group_96 + assign \root_times_radicand$129 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$129 \core_calculate_stage_13_root_times_radicand$94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$130 + process $group_97 + assign \compare_lhs$130 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$130 \core_calculate_stage_13_compare_lhs$95 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$131 + process $group_98 + assign \compare_rhs$131 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$131 \core_calculate_stage_13_compare_rhs$96 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_99 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_100 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$100 + end + sync init + update \muxid$1 2'00 + sync posedge \clk + update \muxid$1 \muxid$1$next + end + process $group_101 + assign \op__insn_type$2$next \op__insn_type$2 + assign \op__fn_unit$3$next \op__fn_unit$3 + assign \op__imm_data__imm$4$next \op__imm_data__imm$4 + assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5 + assign \op__lk$6$next \op__lk$6 + assign \op__rc__rc$7$next \op__rc__rc$7 + assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8 + assign \op__oe__oe$9$next \op__oe__oe$9 + assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10 + assign \op__invert_a$11$next \op__invert_a$11 + assign \op__zero_a$12$next \op__zero_a$12 + assign \op__input_carry$13$next \op__input_carry$13 + assign \op__invert_out$14$next \op__invert_out$14 + assign \op__write_cr__data$15$next \op__write_cr__data$15 + assign \op__write_cr__ok$16$next \op__write_cr__ok$16 + assign \op__output_carry$17$next \op__output_carry$17 + assign \op__is_32bit$18$next \op__is_32bit$18 + assign \op__is_signed$19$next \op__is_signed$19 + assign \op__data_len$20$next \op__data_len$20 + assign \op__insn$21$next \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5$next 1'0 + assign \op__rc__rc$7$next 1'0 + assign \op__rc__rc_ok$8$next 1'0 + assign \op__oe__oe$9$next 1'0 + assign \op__oe__oe_ok$10$next 1'0 + assign \op__write_cr__data$15$next 3'000 + assign \op__write_cr__ok$16$next 1'0 + assign \op__insn$21$next 32'00000000000000000000000000000000 + end + sync init + update \op__insn_type$2 7'0000000 + update \op__fn_unit$3 10'0000000000 + update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \op__imm_data__imm_ok$5 1'0 + update \op__lk$6 1'0 + update \op__rc__rc$7 1'0 + update \op__rc__rc_ok$8 1'0 + update \op__oe__oe$9 1'0 + update \op__oe__oe_ok$10 1'0 + update \op__invert_a$11 1'0 + update \op__zero_a$12 1'0 + update \op__input_carry$13 2'00 + update \op__invert_out$14 1'0 + update \op__write_cr__data$15 3'000 + update \op__write_cr__ok$16 1'0 + update \op__output_carry$17 1'0 + update \op__is_32bit$18 1'0 + update \op__is_signed$19 1'0 + update \op__data_len$20 4'0000 + update \op__insn$21 32'00000000000000000000000000000000 + sync posedge \clk + update \op__insn_type$2 \op__insn_type$2$next + update \op__fn_unit$3 \op__fn_unit$3$next + update \op__imm_data__imm$4 \op__imm_data__imm$4$next + update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next + update \op__lk$6 \op__lk$6$next + update \op__rc__rc$7 \op__rc__rc$7$next + update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next + update \op__oe__oe$9 \op__oe__oe$9$next + update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next + update \op__invert_a$11 \op__invert_a$11$next + update \op__zero_a$12 \op__zero_a$12$next + update \op__input_carry$13 \op__input_carry$13$next + update \op__invert_out$14 \op__invert_out$14$next + update \op__write_cr__data$15 \op__write_cr__data$15$next + update \op__write_cr__ok$16 \op__write_cr__ok$16$next + update \op__output_carry$17 \op__output_carry$17$next + update \op__is_32bit$18 \op__is_32bit$18$next + update \op__is_signed$19 \op__is_signed$19$next + update \op__data_len$20 \op__data_len$20$next + update \op__insn$21 \op__insn$21$next + end + process $group_121 + assign \ra$22$next \ra$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$22$next \ra$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$22$next \ra$121 + end + sync init + update \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \ra$22 \ra$22$next + end + process $group_122 + assign \rb$23$next \rb$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$23$next \rb$122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$23$next \rb$122 + end + sync init + update \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \rb$23 \rb$23$next + end + process $group_123 + assign \xer_so$24$next \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$24$next \xer_so$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$24$next \xer_so$123 + end + sync init + update \xer_so$24 1'0 + sync posedge \clk + update \xer_so$24 \xer_so$24$next + end + process $group_124 + assign \divisor_neg$25$next \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$25$next \divisor_neg$124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$25$next \divisor_neg$124 + end + sync init + update \divisor_neg$25 1'0 + sync posedge \clk + update \divisor_neg$25 \divisor_neg$25$next + end + process $group_125 + assign \dividend_neg$26$next \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$26$next \dividend_neg$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$26$next \dividend_neg$125 + end + sync init + update \dividend_neg$26 1'0 + sync posedge \clk + update \dividend_neg$26 \dividend_neg$26$next + end + process $group_126 + assign \divisor_radicand$27$next \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$27$next \divisor_radicand$126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$27$next \divisor_radicand$126 + end + sync init + update \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \divisor_radicand$27 \divisor_radicand$27$next + end + process $group_127 + assign \operation$28$next \operation$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$28$next \operation$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$28$next \operation$127 + end + sync init + update \operation$28 2'00 + sync posedge \clk + update \operation$28 \operation$28$next + end + process $group_128 + assign \quotient_root$29$next \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$29$next \quotient_root$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$29$next \quotient_root$128 + end + sync init + update \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \quotient_root$29 \quotient_root$29$next + end + process $group_129 + assign \root_times_radicand$30$next \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$30$next \root_times_radicand$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$30$next \root_times_radicand$129 + end + sync init + update \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \root_times_radicand$30 \root_times_radicand$30$next + end + process $group_130 + assign \compare_lhs$31$next \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$31$next \compare_lhs$130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$31$next \compare_lhs$130 + end + sync init + update \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_lhs$31 \compare_lhs$31$next + end + process $group_131 + assign \compare_rhs$32$next \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$32$next \compare_rhs$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$32$next \compare_rhs$131 + end + sync init + update \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_rhs$32 \compare_rhs$32$next + end + process $group_132 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_133 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.p" +module \p$197 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.n" +module \n$198 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_14.core.trial0" +module \trial0$200 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000000 + connect \B 7'1100110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_14.core.trial1" +module \trial1$201 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000001 + connect \B 7'1100110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_14.core.trial2" +module \trial2$202 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000100 + connect \B 7'1100110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_14.core.trial3" +module \trial3$203 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'001001 + connect \B 7'1100110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_14.core.trial4" +module \trial4$204 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'010000 + connect \B 7'1100110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_14.core.trial5" +module \trial5$205 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'011001 + connect \B 7'1100110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_14.core.trial6" +module \trial6$206 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'100100 + connect \B 7'1100110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_14.core.trial7" +module \trial7$207 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010011 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010100 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'110001 + connect \B 7'1100110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10100 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_14.core.pe" +module \pe$208 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_14.core" +module \core$199 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$200 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$201 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$202 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$203 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$204 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$205 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$206 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$207 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$208 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 34 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 34 + connect \A \next_bits + connect \B 5'10011 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 34 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 98 $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 98 + connect \A $35 + connect \B 5'10011 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 98 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B $37 + connect \Y $39 + end + connect $34 $39 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $34 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_14" +module \core_calculate_stage_14 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$199 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_15.core.trial0" +module \trial0$210 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000000 + connect \B 7'1100000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_15.core.trial1" +module \trial1$211 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000001 + connect \B 7'1100000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_15.core.trial2" +module \trial2$212 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000100 + connect \B 7'1100000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_15.core.trial3" +module \trial3$213 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'001001 + connect \B 7'1100000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_15.core.trial4" +module \trial4$214 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'010000 + connect \B 7'1100000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_15.core.trial5" +module \trial5$215 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'011001 + connect \B 7'1100000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_15.core.trial6" +module \trial6$216 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'100100 + connect \B 7'1100000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_15.core.trial7" +module \trial7$217 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1010000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1010001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'110001 + connect \B 7'1100000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 235 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 235 + connect \A \rr_times_trial_bits + connect \B 5'10001 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 236 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 235 + parameter \Y_WIDTH 236 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 133 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 133 + connect \A \dr_times_trial_bits_sqrd + connect \B 6'100000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 237 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 236 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 237 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_15.core.pe" +module \pe$218 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_15.core" +module \core$209 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$210 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$211 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$212 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$213 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$214 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$215 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$216 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$217 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$218 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 34 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 34 + connect \A \next_bits + connect \B 5'10000 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 34 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 98 $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 98 + connect \A $35 + connect \B 5'10000 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 98 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B $37 + connect \Y $39 + end + connect $34 $39 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $34 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16.core_calculate_stage_15" +module \core_calculate_stage_15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$209 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_14_to_16" +module \pipe_14_to_16 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 4 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 5 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 7 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 16 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 18 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 20 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 21 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 22 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 23 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 24 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 25 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 26 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 28 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 29 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 30 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 31 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 32 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 33 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 34 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 35 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 36 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 37 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 38 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$1$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 39 \op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 40 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 41 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 46 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 50 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 51 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 52 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 53 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 54 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 55 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 56 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 57 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 58 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 59 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 60 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 61 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 62 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 63 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$26$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 64 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 65 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 66 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 67 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 68 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 69 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$32$next + cell \p$197 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$198 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_14_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_14_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_14_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_14_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_14_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_14_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_14_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_14_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_14_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_14_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_14_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_14_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_14_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_14_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_14_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_14_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_14_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_14_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_14_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_14_muxid$33 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_14_op__insn_type$34 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_14_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_14_op__imm_data__imm$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__imm_data__imm_ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__lk$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__invert_a$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_14_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_14_op__write_cr__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__write_cr__ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__output_carry$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__is_32bit$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_14_op__is_signed$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_14_op__data_len$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_14_op__insn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_14_ra$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_14_rb$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_14_xer_so$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_14_divisor_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_14_dividend_neg$58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_14_divisor_radicand$59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_14_operation$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_14_quotient_root$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_14_root_times_radicand$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_14_compare_lhs$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_14_compare_rhs$64 + cell \core_calculate_stage_14 \core_calculate_stage_14 + connect \muxid \core_calculate_stage_14_muxid + connect \op__insn_type \core_calculate_stage_14_op__insn_type + connect \op__fn_unit \core_calculate_stage_14_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_14_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_14_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_14_op__lk + connect \op__rc__rc \core_calculate_stage_14_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_14_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_14_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_14_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_14_op__invert_a + connect \op__zero_a \core_calculate_stage_14_op__zero_a + connect \op__input_carry \core_calculate_stage_14_op__input_carry + connect \op__invert_out \core_calculate_stage_14_op__invert_out + connect \op__write_cr__data \core_calculate_stage_14_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_14_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_14_op__output_carry + connect \op__is_32bit \core_calculate_stage_14_op__is_32bit + connect \op__is_signed \core_calculate_stage_14_op__is_signed + connect \op__data_len \core_calculate_stage_14_op__data_len + connect \op__insn \core_calculate_stage_14_op__insn + connect \ra \core_calculate_stage_14_ra + connect \rb \core_calculate_stage_14_rb + connect \xer_so \core_calculate_stage_14_xer_so + connect \divisor_neg \core_calculate_stage_14_divisor_neg + connect \dividend_neg \core_calculate_stage_14_dividend_neg + connect \divisor_radicand \core_calculate_stage_14_divisor_radicand + connect \operation \core_calculate_stage_14_operation + connect \quotient_root \core_calculate_stage_14_quotient_root + connect \root_times_radicand \core_calculate_stage_14_root_times_radicand + connect \compare_lhs \core_calculate_stage_14_compare_lhs + connect \compare_rhs \core_calculate_stage_14_compare_rhs + connect \muxid$1 \core_calculate_stage_14_muxid$33 + connect \op__insn_type$2 \core_calculate_stage_14_op__insn_type$34 + connect \op__fn_unit$3 \core_calculate_stage_14_op__fn_unit$35 + connect \op__imm_data__imm$4 \core_calculate_stage_14_op__imm_data__imm$36 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_14_op__imm_data__imm_ok$37 + connect \op__lk$6 \core_calculate_stage_14_op__lk$38 + connect \op__rc__rc$7 \core_calculate_stage_14_op__rc__rc$39 + connect \op__rc__rc_ok$8 \core_calculate_stage_14_op__rc__rc_ok$40 + connect \op__oe__oe$9 \core_calculate_stage_14_op__oe__oe$41 + connect \op__oe__oe_ok$10 \core_calculate_stage_14_op__oe__oe_ok$42 + connect \op__invert_a$11 \core_calculate_stage_14_op__invert_a$43 + connect \op__zero_a$12 \core_calculate_stage_14_op__zero_a$44 + connect \op__input_carry$13 \core_calculate_stage_14_op__input_carry$45 + connect \op__invert_out$14 \core_calculate_stage_14_op__invert_out$46 + connect \op__write_cr__data$15 \core_calculate_stage_14_op__write_cr__data$47 + connect \op__write_cr__ok$16 \core_calculate_stage_14_op__write_cr__ok$48 + connect \op__output_carry$17 \core_calculate_stage_14_op__output_carry$49 + connect \op__is_32bit$18 \core_calculate_stage_14_op__is_32bit$50 + connect \op__is_signed$19 \core_calculate_stage_14_op__is_signed$51 + connect \op__data_len$20 \core_calculate_stage_14_op__data_len$52 + connect \op__insn$21 \core_calculate_stage_14_op__insn$53 + connect \ra$22 \core_calculate_stage_14_ra$54 + connect \rb$23 \core_calculate_stage_14_rb$55 + connect \xer_so$24 \core_calculate_stage_14_xer_so$56 + connect \divisor_neg$25 \core_calculate_stage_14_divisor_neg$57 + connect \dividend_neg$26 \core_calculate_stage_14_dividend_neg$58 + connect \divisor_radicand$27 \core_calculate_stage_14_divisor_radicand$59 + connect \operation$28 \core_calculate_stage_14_operation$60 + connect \quotient_root$29 \core_calculate_stage_14_quotient_root$61 + connect \root_times_radicand$30 \core_calculate_stage_14_root_times_radicand$62 + connect \compare_lhs$31 \core_calculate_stage_14_compare_lhs$63 + connect \compare_rhs$32 \core_calculate_stage_14_compare_rhs$64 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_15_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_15_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_15_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_15_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_15_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_15_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_15_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_15_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_15_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_15_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_15_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_15_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_15_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_15_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_15_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_15_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_15_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_15_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_15_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_15_muxid$65 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_15_op__insn_type$66 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_15_op__fn_unit$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_15_op__imm_data__imm$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__imm_data__imm_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__lk$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__rc__rc_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__oe__oe_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__invert_a$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__zero_a$76 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_15_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_15_op__write_cr__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__write_cr__ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_15_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_15_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_15_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_15_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_15_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_15_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_15_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_15_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_15_divisor_radicand$91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_15_operation$92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_15_quotient_root$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_15_root_times_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_15_compare_lhs$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_15_compare_rhs$96 + cell \core_calculate_stage_15 \core_calculate_stage_15 + connect \muxid \core_calculate_stage_15_muxid + connect \op__insn_type \core_calculate_stage_15_op__insn_type + connect \op__fn_unit \core_calculate_stage_15_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_15_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_15_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_15_op__lk + connect \op__rc__rc \core_calculate_stage_15_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_15_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_15_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_15_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_15_op__invert_a + connect \op__zero_a \core_calculate_stage_15_op__zero_a + connect \op__input_carry \core_calculate_stage_15_op__input_carry + connect \op__invert_out \core_calculate_stage_15_op__invert_out + connect \op__write_cr__data \core_calculate_stage_15_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_15_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_15_op__output_carry + connect \op__is_32bit \core_calculate_stage_15_op__is_32bit + connect \op__is_signed \core_calculate_stage_15_op__is_signed + connect \op__data_len \core_calculate_stage_15_op__data_len + connect \op__insn \core_calculate_stage_15_op__insn + connect \ra \core_calculate_stage_15_ra + connect \rb \core_calculate_stage_15_rb + connect \xer_so \core_calculate_stage_15_xer_so + connect \divisor_neg \core_calculate_stage_15_divisor_neg + connect \dividend_neg \core_calculate_stage_15_dividend_neg + connect \divisor_radicand \core_calculate_stage_15_divisor_radicand + connect \operation \core_calculate_stage_15_operation + connect \quotient_root \core_calculate_stage_15_quotient_root + connect \root_times_radicand \core_calculate_stage_15_root_times_radicand + connect \compare_lhs \core_calculate_stage_15_compare_lhs + connect \compare_rhs \core_calculate_stage_15_compare_rhs + connect \muxid$1 \core_calculate_stage_15_muxid$65 + connect \op__insn_type$2 \core_calculate_stage_15_op__insn_type$66 + connect \op__fn_unit$3 \core_calculate_stage_15_op__fn_unit$67 + connect \op__imm_data__imm$4 \core_calculate_stage_15_op__imm_data__imm$68 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_15_op__imm_data__imm_ok$69 + connect \op__lk$6 \core_calculate_stage_15_op__lk$70 + connect \op__rc__rc$7 \core_calculate_stage_15_op__rc__rc$71 + connect \op__rc__rc_ok$8 \core_calculate_stage_15_op__rc__rc_ok$72 + connect \op__oe__oe$9 \core_calculate_stage_15_op__oe__oe$73 + connect \op__oe__oe_ok$10 \core_calculate_stage_15_op__oe__oe_ok$74 + connect \op__invert_a$11 \core_calculate_stage_15_op__invert_a$75 + connect \op__zero_a$12 \core_calculate_stage_15_op__zero_a$76 + connect \op__input_carry$13 \core_calculate_stage_15_op__input_carry$77 + connect \op__invert_out$14 \core_calculate_stage_15_op__invert_out$78 + connect \op__write_cr__data$15 \core_calculate_stage_15_op__write_cr__data$79 + connect \op__write_cr__ok$16 \core_calculate_stage_15_op__write_cr__ok$80 + connect \op__output_carry$17 \core_calculate_stage_15_op__output_carry$81 + connect \op__is_32bit$18 \core_calculate_stage_15_op__is_32bit$82 + connect \op__is_signed$19 \core_calculate_stage_15_op__is_signed$83 + connect \op__data_len$20 \core_calculate_stage_15_op__data_len$84 + connect \op__insn$21 \core_calculate_stage_15_op__insn$85 + connect \ra$22 \core_calculate_stage_15_ra$86 + connect \rb$23 \core_calculate_stage_15_rb$87 + connect \xer_so$24 \core_calculate_stage_15_xer_so$88 + connect \divisor_neg$25 \core_calculate_stage_15_divisor_neg$89 + connect \dividend_neg$26 \core_calculate_stage_15_dividend_neg$90 + connect \divisor_radicand$27 \core_calculate_stage_15_divisor_radicand$91 + connect \operation$28 \core_calculate_stage_15_operation$92 + connect \quotient_root$29 \core_calculate_stage_15_quotient_root$93 + connect \root_times_radicand$30 \core_calculate_stage_15_root_times_radicand$94 + connect \compare_lhs$31 \core_calculate_stage_15_compare_lhs$95 + connect \compare_rhs$32 \core_calculate_stage_15_compare_rhs$96 + end + process $group_0 + assign \core_calculate_stage_14_muxid 2'00 + assign \core_calculate_stage_14_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_14_op__insn_type 7'0000000 + assign \core_calculate_stage_14_op__fn_unit 10'0000000000 + assign \core_calculate_stage_14_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_14_op__lk 1'0 + assign \core_calculate_stage_14_op__rc__rc 1'0 + assign \core_calculate_stage_14_op__rc__rc_ok 1'0 + assign \core_calculate_stage_14_op__oe__oe 1'0 + assign \core_calculate_stage_14_op__oe__oe_ok 1'0 + assign \core_calculate_stage_14_op__invert_a 1'0 + assign \core_calculate_stage_14_op__zero_a 1'0 + assign \core_calculate_stage_14_op__input_carry 2'00 + assign \core_calculate_stage_14_op__invert_out 1'0 + assign \core_calculate_stage_14_op__write_cr__data 3'000 + assign \core_calculate_stage_14_op__write_cr__ok 1'0 + assign \core_calculate_stage_14_op__output_carry 1'0 + assign \core_calculate_stage_14_op__is_32bit 1'0 + assign \core_calculate_stage_14_op__is_signed 1'0 + assign \core_calculate_stage_14_op__data_len 4'0000 + assign \core_calculate_stage_14_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_14_op__insn \core_calculate_stage_14_op__data_len \core_calculate_stage_14_op__is_signed \core_calculate_stage_14_op__is_32bit \core_calculate_stage_14_op__output_carry { \core_calculate_stage_14_op__write_cr__ok \core_calculate_stage_14_op__write_cr__data } \core_calculate_stage_14_op__invert_out \core_calculate_stage_14_op__input_carry \core_calculate_stage_14_op__zero_a \core_calculate_stage_14_op__invert_a { \core_calculate_stage_14_op__oe__oe_ok \core_calculate_stage_14_op__oe__oe } { \core_calculate_stage_14_op__rc__rc_ok \core_calculate_stage_14_op__rc__rc } \core_calculate_stage_14_op__lk { \core_calculate_stage_14_op__imm_data__imm_ok \core_calculate_stage_14_op__imm_data__imm } \core_calculate_stage_14_op__fn_unit \core_calculate_stage_14_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \core_calculate_stage_14_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_ra \ra + sync init + end + process $group_22 + assign \core_calculate_stage_14_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_rb \rb + sync init + end + process $group_23 + assign \core_calculate_stage_14_xer_so 1'0 + assign \core_calculate_stage_14_xer_so \xer_so + sync init + end + process $group_24 + assign \core_calculate_stage_14_divisor_neg 1'0 + assign \core_calculate_stage_14_divisor_neg \divisor_neg + sync init + end + process $group_25 + assign \core_calculate_stage_14_dividend_neg 1'0 + assign \core_calculate_stage_14_dividend_neg \dividend_neg + sync init + end + process $group_26 + assign \core_calculate_stage_14_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_calculate_stage_14_operation 2'00 + assign \core_calculate_stage_14_operation \operation + sync init + end + process $group_28 + assign \core_calculate_stage_14_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_calculate_stage_14_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_calculate_stage_14_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_calculate_stage_14_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_14_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \core_calculate_stage_15_muxid 2'00 + assign \core_calculate_stage_15_muxid \core_calculate_stage_14_muxid$33 + sync init + end + process $group_33 + assign \core_calculate_stage_15_op__insn_type 7'0000000 + assign \core_calculate_stage_15_op__fn_unit 10'0000000000 + assign \core_calculate_stage_15_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_15_op__lk 1'0 + assign \core_calculate_stage_15_op__rc__rc 1'0 + assign \core_calculate_stage_15_op__rc__rc_ok 1'0 + assign \core_calculate_stage_15_op__oe__oe 1'0 + assign \core_calculate_stage_15_op__oe__oe_ok 1'0 + assign \core_calculate_stage_15_op__invert_a 1'0 + assign \core_calculate_stage_15_op__zero_a 1'0 + assign \core_calculate_stage_15_op__input_carry 2'00 + assign \core_calculate_stage_15_op__invert_out 1'0 + assign \core_calculate_stage_15_op__write_cr__data 3'000 + assign \core_calculate_stage_15_op__write_cr__ok 1'0 + assign \core_calculate_stage_15_op__output_carry 1'0 + assign \core_calculate_stage_15_op__is_32bit 1'0 + assign \core_calculate_stage_15_op__is_signed 1'0 + assign \core_calculate_stage_15_op__data_len 4'0000 + assign \core_calculate_stage_15_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_15_op__insn \core_calculate_stage_15_op__data_len \core_calculate_stage_15_op__is_signed \core_calculate_stage_15_op__is_32bit \core_calculate_stage_15_op__output_carry { \core_calculate_stage_15_op__write_cr__ok \core_calculate_stage_15_op__write_cr__data } \core_calculate_stage_15_op__invert_out \core_calculate_stage_15_op__input_carry \core_calculate_stage_15_op__zero_a \core_calculate_stage_15_op__invert_a { \core_calculate_stage_15_op__oe__oe_ok \core_calculate_stage_15_op__oe__oe } { \core_calculate_stage_15_op__rc__rc_ok \core_calculate_stage_15_op__rc__rc } \core_calculate_stage_15_op__lk { \core_calculate_stage_15_op__imm_data__imm_ok \core_calculate_stage_15_op__imm_data__imm } \core_calculate_stage_15_op__fn_unit \core_calculate_stage_15_op__insn_type } { \core_calculate_stage_14_op__insn$53 \core_calculate_stage_14_op__data_len$52 \core_calculate_stage_14_op__is_signed$51 \core_calculate_stage_14_op__is_32bit$50 \core_calculate_stage_14_op__output_carry$49 { \core_calculate_stage_14_op__write_cr__ok$48 \core_calculate_stage_14_op__write_cr__data$47 } \core_calculate_stage_14_op__invert_out$46 \core_calculate_stage_14_op__input_carry$45 \core_calculate_stage_14_op__zero_a$44 \core_calculate_stage_14_op__invert_a$43 { \core_calculate_stage_14_op__oe__oe_ok$42 \core_calculate_stage_14_op__oe__oe$41 } { \core_calculate_stage_14_op__rc__rc_ok$40 \core_calculate_stage_14_op__rc__rc$39 } \core_calculate_stage_14_op__lk$38 { \core_calculate_stage_14_op__imm_data__imm_ok$37 \core_calculate_stage_14_op__imm_data__imm$36 } \core_calculate_stage_14_op__fn_unit$35 \core_calculate_stage_14_op__insn_type$34 } + sync init + end + process $group_53 + assign \core_calculate_stage_15_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_ra \core_calculate_stage_14_ra$54 + sync init + end + process $group_54 + assign \core_calculate_stage_15_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_rb \core_calculate_stage_14_rb$55 + sync init + end + process $group_55 + assign \core_calculate_stage_15_xer_so 1'0 + assign \core_calculate_stage_15_xer_so \core_calculate_stage_14_xer_so$56 + sync init + end + process $group_56 + assign \core_calculate_stage_15_divisor_neg 1'0 + assign \core_calculate_stage_15_divisor_neg \core_calculate_stage_14_divisor_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_15_dividend_neg 1'0 + assign \core_calculate_stage_15_dividend_neg \core_calculate_stage_14_dividend_neg$58 + sync init + end + process $group_58 + assign \core_calculate_stage_15_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_divisor_radicand \core_calculate_stage_14_divisor_radicand$59 + sync init + end + process $group_59 + assign \core_calculate_stage_15_operation 2'00 + assign \core_calculate_stage_15_operation \core_calculate_stage_14_operation$60 + sync init + end + process $group_60 + assign \core_calculate_stage_15_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_quotient_root \core_calculate_stage_14_quotient_root$61 + sync init + end + process $group_61 + assign \core_calculate_stage_15_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_root_times_radicand \core_calculate_stage_14_root_times_radicand$62 + sync init + end + process $group_62 + assign \core_calculate_stage_15_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_compare_lhs \core_calculate_stage_14_compare_lhs$63 + sync init + end + process $group_63 + assign \core_calculate_stage_15_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_15_compare_rhs \core_calculate_stage_14_compare_rhs$64 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$97 + process $group_64 + assign \p_valid_i$97 1'0 + assign \p_valid_i$97 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_65 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $98 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$97 + connect \B \p_ready_o + connect \Y $98 + end + process $group_66 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $98 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$100 + process $group_67 + assign \muxid$100 2'00 + assign \muxid$100 \core_calculate_stage_15_muxid$65 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$111 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$120 + process $group_68 + assign \op__insn_type$101 7'0000000 + assign \op__fn_unit$102 10'0000000000 + assign \op__imm_data__imm$103 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$104 1'0 + assign \op__lk$105 1'0 + assign \op__rc__rc$106 1'0 + assign \op__rc__rc_ok$107 1'0 + assign \op__oe__oe$108 1'0 + assign \op__oe__oe_ok$109 1'0 + assign \op__invert_a$110 1'0 + assign \op__zero_a$111 1'0 + assign \op__input_carry$112 2'00 + assign \op__invert_out$113 1'0 + assign \op__write_cr__data$114 3'000 + assign \op__write_cr__ok$115 1'0 + assign \op__output_carry$116 1'0 + assign \op__is_32bit$117 1'0 + assign \op__is_signed$118 1'0 + assign \op__data_len$119 4'0000 + assign \op__insn$120 32'00000000000000000000000000000000 + assign { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } { \core_calculate_stage_15_op__insn$85 \core_calculate_stage_15_op__data_len$84 \core_calculate_stage_15_op__is_signed$83 \core_calculate_stage_15_op__is_32bit$82 \core_calculate_stage_15_op__output_carry$81 { \core_calculate_stage_15_op__write_cr__ok$80 \core_calculate_stage_15_op__write_cr__data$79 } \core_calculate_stage_15_op__invert_out$78 \core_calculate_stage_15_op__input_carry$77 \core_calculate_stage_15_op__zero_a$76 \core_calculate_stage_15_op__invert_a$75 { \core_calculate_stage_15_op__oe__oe_ok$74 \core_calculate_stage_15_op__oe__oe$73 } { \core_calculate_stage_15_op__rc__rc_ok$72 \core_calculate_stage_15_op__rc__rc$71 } \core_calculate_stage_15_op__lk$70 { \core_calculate_stage_15_op__imm_data__imm_ok$69 \core_calculate_stage_15_op__imm_data__imm$68 } \core_calculate_stage_15_op__fn_unit$67 \core_calculate_stage_15_op__insn_type$66 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$121 + process $group_88 + assign \ra$121 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$121 \core_calculate_stage_15_ra$86 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$122 + process $group_89 + assign \rb$122 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$122 \core_calculate_stage_15_rb$87 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$123 + process $group_90 + assign \xer_so$123 1'0 + assign \xer_so$123 \core_calculate_stage_15_xer_so$88 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$124 + process $group_91 + assign \divisor_neg$124 1'0 + assign \divisor_neg$124 \core_calculate_stage_15_divisor_neg$89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$125 + process $group_92 + assign \dividend_neg$125 1'0 + assign \dividend_neg$125 \core_calculate_stage_15_dividend_neg$90 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$126 + process $group_93 + assign \divisor_radicand$126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$126 \core_calculate_stage_15_divisor_radicand$91 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$127 + process $group_94 + assign \operation$127 2'00 + assign \operation$127 \core_calculate_stage_15_operation$92 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$128 + process $group_95 + assign \quotient_root$128 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$128 \core_calculate_stage_15_quotient_root$93 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$129 + process $group_96 + assign \root_times_radicand$129 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$129 \core_calculate_stage_15_root_times_radicand$94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$130 + process $group_97 + assign \compare_lhs$130 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$130 \core_calculate_stage_15_compare_lhs$95 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$131 + process $group_98 + assign \compare_rhs$131 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$131 \core_calculate_stage_15_compare_rhs$96 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_99 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_100 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$100 + end + sync init + update \muxid$1 2'00 + sync posedge \clk + update \muxid$1 \muxid$1$next + end + process $group_101 + assign \op__insn_type$2$next \op__insn_type$2 + assign \op__fn_unit$3$next \op__fn_unit$3 + assign \op__imm_data__imm$4$next \op__imm_data__imm$4 + assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5 + assign \op__lk$6$next \op__lk$6 + assign \op__rc__rc$7$next \op__rc__rc$7 + assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8 + assign \op__oe__oe$9$next \op__oe__oe$9 + assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10 + assign \op__invert_a$11$next \op__invert_a$11 + assign \op__zero_a$12$next \op__zero_a$12 + assign \op__input_carry$13$next \op__input_carry$13 + assign \op__invert_out$14$next \op__invert_out$14 + assign \op__write_cr__data$15$next \op__write_cr__data$15 + assign \op__write_cr__ok$16$next \op__write_cr__ok$16 + assign \op__output_carry$17$next \op__output_carry$17 + assign \op__is_32bit$18$next \op__is_32bit$18 + assign \op__is_signed$19$next \op__is_signed$19 + assign \op__data_len$20$next \op__data_len$20 + assign \op__insn$21$next \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5$next 1'0 + assign \op__rc__rc$7$next 1'0 + assign \op__rc__rc_ok$8$next 1'0 + assign \op__oe__oe$9$next 1'0 + assign \op__oe__oe_ok$10$next 1'0 + assign \op__write_cr__data$15$next 3'000 + assign \op__write_cr__ok$16$next 1'0 + assign \op__insn$21$next 32'00000000000000000000000000000000 + end + sync init + update \op__insn_type$2 7'0000000 + update \op__fn_unit$3 10'0000000000 + update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \op__imm_data__imm_ok$5 1'0 + update \op__lk$6 1'0 + update \op__rc__rc$7 1'0 + update \op__rc__rc_ok$8 1'0 + update \op__oe__oe$9 1'0 + update \op__oe__oe_ok$10 1'0 + update \op__invert_a$11 1'0 + update \op__zero_a$12 1'0 + update \op__input_carry$13 2'00 + update \op__invert_out$14 1'0 + update \op__write_cr__data$15 3'000 + update \op__write_cr__ok$16 1'0 + update \op__output_carry$17 1'0 + update \op__is_32bit$18 1'0 + update \op__is_signed$19 1'0 + update \op__data_len$20 4'0000 + update \op__insn$21 32'00000000000000000000000000000000 + sync posedge \clk + update \op__insn_type$2 \op__insn_type$2$next + update \op__fn_unit$3 \op__fn_unit$3$next + update \op__imm_data__imm$4 \op__imm_data__imm$4$next + update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next + update \op__lk$6 \op__lk$6$next + update \op__rc__rc$7 \op__rc__rc$7$next + update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next + update \op__oe__oe$9 \op__oe__oe$9$next + update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next + update \op__invert_a$11 \op__invert_a$11$next + update \op__zero_a$12 \op__zero_a$12$next + update \op__input_carry$13 \op__input_carry$13$next + update \op__invert_out$14 \op__invert_out$14$next + update \op__write_cr__data$15 \op__write_cr__data$15$next + update \op__write_cr__ok$16 \op__write_cr__ok$16$next + update \op__output_carry$17 \op__output_carry$17$next + update \op__is_32bit$18 \op__is_32bit$18$next + update \op__is_signed$19 \op__is_signed$19$next + update \op__data_len$20 \op__data_len$20$next + update \op__insn$21 \op__insn$21$next + end + process $group_121 + assign \ra$22$next \ra$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$22$next \ra$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$22$next \ra$121 + end + sync init + update \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \ra$22 \ra$22$next + end + process $group_122 + assign \rb$23$next \rb$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$23$next \rb$122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$23$next \rb$122 + end + sync init + update \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \rb$23 \rb$23$next + end + process $group_123 + assign \xer_so$24$next \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$24$next \xer_so$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$24$next \xer_so$123 + end + sync init + update \xer_so$24 1'0 + sync posedge \clk + update \xer_so$24 \xer_so$24$next + end + process $group_124 + assign \divisor_neg$25$next \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$25$next \divisor_neg$124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$25$next \divisor_neg$124 + end + sync init + update \divisor_neg$25 1'0 + sync posedge \clk + update \divisor_neg$25 \divisor_neg$25$next + end + process $group_125 + assign \dividend_neg$26$next \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$26$next \dividend_neg$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$26$next \dividend_neg$125 + end + sync init + update \dividend_neg$26 1'0 + sync posedge \clk + update \dividend_neg$26 \dividend_neg$26$next + end + process $group_126 + assign \divisor_radicand$27$next \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$27$next \divisor_radicand$126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$27$next \divisor_radicand$126 + end + sync init + update \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \divisor_radicand$27 \divisor_radicand$27$next + end + process $group_127 + assign \operation$28$next \operation$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$28$next \operation$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$28$next \operation$127 + end + sync init + update \operation$28 2'00 + sync posedge \clk + update \operation$28 \operation$28$next + end + process $group_128 + assign \quotient_root$29$next \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$29$next \quotient_root$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$29$next \quotient_root$128 + end + sync init + update \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \quotient_root$29 \quotient_root$29$next + end + process $group_129 + assign \root_times_radicand$30$next \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$30$next \root_times_radicand$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$30$next \root_times_radicand$129 + end + sync init + update \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \root_times_radicand$30 \root_times_radicand$30$next + end + process $group_130 + assign \compare_lhs$31$next \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$31$next \compare_lhs$130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$31$next \compare_lhs$130 + end + sync init + update \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_lhs$31 \compare_lhs$31$next + end + process $group_131 + assign \compare_rhs$32$next \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$32$next \compare_rhs$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$32$next \compare_rhs$131 + end + sync init + update \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_rhs$32 \compare_rhs$32$next + end + process $group_132 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_133 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.p" +module \p$219 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.n" +module \n$220 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_16.core.trial0" +module \trial0$222 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000000 + connect \B 7'1011010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'11010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_16.core.trial1" +module \trial1$223 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000001 + connect \B 7'1011010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'11010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_16.core.trial2" +module \trial2$224 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000100 + connect \B 7'1011010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'11010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_16.core.trial3" +module \trial3$225 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'001001 + connect \B 7'1011010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'11010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_16.core.trial4" +module \trial4$226 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'010000 + connect \B 7'1011010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'11010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_16.core.trial5" +module \trial5$227 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'011001 + connect \B 7'1011010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'11010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_16.core.trial6" +module \trial6$228 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'100100 + connect \B 7'1011010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'11010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_16.core.trial7" +module \trial7$229 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001101 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001110 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'110001 + connect \B 7'1011010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1110 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'11010 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_16.core.pe" +module \pe$230 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_16.core" +module \core$221 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$222 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$223 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$224 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$225 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$226 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$227 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$228 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$229 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$230 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 18 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 18 + connect \A \next_bits + connect \B 4'1101 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 18 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 82 $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 82 + connect \A $35 + connect \B 4'1101 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 82 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B $37 + connect \Y $39 + end + connect $34 $39 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $34 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_16" +module \core_calculate_stage_16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$221 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_17.core.trial0" +module \trial0$232 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000000 + connect \B 7'1010100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'10100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_17.core.trial1" +module \trial1$233 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000001 + connect \B 7'1010100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'10100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_17.core.trial2" +module \trial2$234 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000100 + connect \B 7'1010100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'10100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_17.core.trial3" +module \trial3$235 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'001001 + connect \B 7'1010100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'10100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_17.core.trial4" +module \trial4$236 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'010000 + connect \B 7'1010100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'10100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_17.core.trial5" +module \trial5$237 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'011001 + connect \B 7'1010100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'10100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_17.core.trial6" +module \trial6$238 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'100100 + connect \B 7'1010100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'10100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_17.core.trial7" +module \trial7$239 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1001010 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001011 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'110001 + connect \B 7'1010100 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1011 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 101 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 101 + connect \A \dr_times_trial_bits_sqrd + connect \B 5'10100 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 101 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_17.core.pe" +module \pe$240 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_17.core" +module \core$231 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$232 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$233 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$234 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$235 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$236 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$237 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$238 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$239 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$240 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 18 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 18 + connect \A \next_bits + connect \B 4'1010 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 18 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 82 $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 82 + connect \A $35 + connect \B 4'1010 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 82 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B $37 + connect \Y $39 + end + connect $34 $39 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $34 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18.core_calculate_stage_17" +module \core_calculate_stage_17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$231 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_16_to_18" +module \pipe_16_to_18 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 4 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 5 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 7 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 16 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 18 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 20 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 21 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 22 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 23 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 24 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 25 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 26 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 28 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 29 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 30 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 31 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 32 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 33 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 34 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 35 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 36 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 37 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 38 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$1$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 39 \op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 40 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 41 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 46 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 50 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 51 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 52 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 53 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 54 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 55 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 56 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 57 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 58 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 59 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 60 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 61 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 62 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 63 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$26$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 64 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 65 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 66 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 67 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 68 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 69 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$32$next + cell \p$219 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$220 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_16_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_16_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_16_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_16_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_16_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_16_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_16_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_16_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_16_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_16_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_16_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_16_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_16_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_16_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_16_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_16_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_16_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_16_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_16_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_16_muxid$33 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_16_op__insn_type$34 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_16_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_16_op__imm_data__imm$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__imm_data__imm_ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__lk$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__invert_a$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_16_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_16_op__write_cr__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__write_cr__ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__output_carry$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__is_32bit$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_16_op__is_signed$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_16_op__data_len$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_16_op__insn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_16_ra$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_16_rb$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_16_xer_so$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_16_divisor_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_16_dividend_neg$58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_16_divisor_radicand$59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_16_operation$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_16_quotient_root$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_16_root_times_radicand$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_16_compare_lhs$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_16_compare_rhs$64 + cell \core_calculate_stage_16 \core_calculate_stage_16 + connect \muxid \core_calculate_stage_16_muxid + connect \op__insn_type \core_calculate_stage_16_op__insn_type + connect \op__fn_unit \core_calculate_stage_16_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_16_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_16_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_16_op__lk + connect \op__rc__rc \core_calculate_stage_16_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_16_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_16_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_16_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_16_op__invert_a + connect \op__zero_a \core_calculate_stage_16_op__zero_a + connect \op__input_carry \core_calculate_stage_16_op__input_carry + connect \op__invert_out \core_calculate_stage_16_op__invert_out + connect \op__write_cr__data \core_calculate_stage_16_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_16_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_16_op__output_carry + connect \op__is_32bit \core_calculate_stage_16_op__is_32bit + connect \op__is_signed \core_calculate_stage_16_op__is_signed + connect \op__data_len \core_calculate_stage_16_op__data_len + connect \op__insn \core_calculate_stage_16_op__insn + connect \ra \core_calculate_stage_16_ra + connect \rb \core_calculate_stage_16_rb + connect \xer_so \core_calculate_stage_16_xer_so + connect \divisor_neg \core_calculate_stage_16_divisor_neg + connect \dividend_neg \core_calculate_stage_16_dividend_neg + connect \divisor_radicand \core_calculate_stage_16_divisor_radicand + connect \operation \core_calculate_stage_16_operation + connect \quotient_root \core_calculate_stage_16_quotient_root + connect \root_times_radicand \core_calculate_stage_16_root_times_radicand + connect \compare_lhs \core_calculate_stage_16_compare_lhs + connect \compare_rhs \core_calculate_stage_16_compare_rhs + connect \muxid$1 \core_calculate_stage_16_muxid$33 + connect \op__insn_type$2 \core_calculate_stage_16_op__insn_type$34 + connect \op__fn_unit$3 \core_calculate_stage_16_op__fn_unit$35 + connect \op__imm_data__imm$4 \core_calculate_stage_16_op__imm_data__imm$36 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_16_op__imm_data__imm_ok$37 + connect \op__lk$6 \core_calculate_stage_16_op__lk$38 + connect \op__rc__rc$7 \core_calculate_stage_16_op__rc__rc$39 + connect \op__rc__rc_ok$8 \core_calculate_stage_16_op__rc__rc_ok$40 + connect \op__oe__oe$9 \core_calculate_stage_16_op__oe__oe$41 + connect \op__oe__oe_ok$10 \core_calculate_stage_16_op__oe__oe_ok$42 + connect \op__invert_a$11 \core_calculate_stage_16_op__invert_a$43 + connect \op__zero_a$12 \core_calculate_stage_16_op__zero_a$44 + connect \op__input_carry$13 \core_calculate_stage_16_op__input_carry$45 + connect \op__invert_out$14 \core_calculate_stage_16_op__invert_out$46 + connect \op__write_cr__data$15 \core_calculate_stage_16_op__write_cr__data$47 + connect \op__write_cr__ok$16 \core_calculate_stage_16_op__write_cr__ok$48 + connect \op__output_carry$17 \core_calculate_stage_16_op__output_carry$49 + connect \op__is_32bit$18 \core_calculate_stage_16_op__is_32bit$50 + connect \op__is_signed$19 \core_calculate_stage_16_op__is_signed$51 + connect \op__data_len$20 \core_calculate_stage_16_op__data_len$52 + connect \op__insn$21 \core_calculate_stage_16_op__insn$53 + connect \ra$22 \core_calculate_stage_16_ra$54 + connect \rb$23 \core_calculate_stage_16_rb$55 + connect \xer_so$24 \core_calculate_stage_16_xer_so$56 + connect \divisor_neg$25 \core_calculate_stage_16_divisor_neg$57 + connect \dividend_neg$26 \core_calculate_stage_16_dividend_neg$58 + connect \divisor_radicand$27 \core_calculate_stage_16_divisor_radicand$59 + connect \operation$28 \core_calculate_stage_16_operation$60 + connect \quotient_root$29 \core_calculate_stage_16_quotient_root$61 + connect \root_times_radicand$30 \core_calculate_stage_16_root_times_radicand$62 + connect \compare_lhs$31 \core_calculate_stage_16_compare_lhs$63 + connect \compare_rhs$32 \core_calculate_stage_16_compare_rhs$64 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_17_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_17_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_17_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_17_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_17_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_17_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_17_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_17_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_17_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_17_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_17_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_17_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_17_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_17_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_17_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_17_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_17_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_17_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_17_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_17_muxid$65 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_17_op__insn_type$66 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_17_op__fn_unit$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_17_op__imm_data__imm$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__imm_data__imm_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__lk$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__rc__rc_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__oe__oe_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__invert_a$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__zero_a$76 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_17_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_17_op__write_cr__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__write_cr__ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_17_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_17_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_17_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_17_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_17_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_17_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_17_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_17_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_17_divisor_radicand$91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_17_operation$92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_17_quotient_root$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_17_root_times_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_17_compare_lhs$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_17_compare_rhs$96 + cell \core_calculate_stage_17 \core_calculate_stage_17 + connect \muxid \core_calculate_stage_17_muxid + connect \op__insn_type \core_calculate_stage_17_op__insn_type + connect \op__fn_unit \core_calculate_stage_17_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_17_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_17_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_17_op__lk + connect \op__rc__rc \core_calculate_stage_17_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_17_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_17_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_17_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_17_op__invert_a + connect \op__zero_a \core_calculate_stage_17_op__zero_a + connect \op__input_carry \core_calculate_stage_17_op__input_carry + connect \op__invert_out \core_calculate_stage_17_op__invert_out + connect \op__write_cr__data \core_calculate_stage_17_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_17_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_17_op__output_carry + connect \op__is_32bit \core_calculate_stage_17_op__is_32bit + connect \op__is_signed \core_calculate_stage_17_op__is_signed + connect \op__data_len \core_calculate_stage_17_op__data_len + connect \op__insn \core_calculate_stage_17_op__insn + connect \ra \core_calculate_stage_17_ra + connect \rb \core_calculate_stage_17_rb + connect \xer_so \core_calculate_stage_17_xer_so + connect \divisor_neg \core_calculate_stage_17_divisor_neg + connect \dividend_neg \core_calculate_stage_17_dividend_neg + connect \divisor_radicand \core_calculate_stage_17_divisor_radicand + connect \operation \core_calculate_stage_17_operation + connect \quotient_root \core_calculate_stage_17_quotient_root + connect \root_times_radicand \core_calculate_stage_17_root_times_radicand + connect \compare_lhs \core_calculate_stage_17_compare_lhs + connect \compare_rhs \core_calculate_stage_17_compare_rhs + connect \muxid$1 \core_calculate_stage_17_muxid$65 + connect \op__insn_type$2 \core_calculate_stage_17_op__insn_type$66 + connect \op__fn_unit$3 \core_calculate_stage_17_op__fn_unit$67 + connect \op__imm_data__imm$4 \core_calculate_stage_17_op__imm_data__imm$68 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_17_op__imm_data__imm_ok$69 + connect \op__lk$6 \core_calculate_stage_17_op__lk$70 + connect \op__rc__rc$7 \core_calculate_stage_17_op__rc__rc$71 + connect \op__rc__rc_ok$8 \core_calculate_stage_17_op__rc__rc_ok$72 + connect \op__oe__oe$9 \core_calculate_stage_17_op__oe__oe$73 + connect \op__oe__oe_ok$10 \core_calculate_stage_17_op__oe__oe_ok$74 + connect \op__invert_a$11 \core_calculate_stage_17_op__invert_a$75 + connect \op__zero_a$12 \core_calculate_stage_17_op__zero_a$76 + connect \op__input_carry$13 \core_calculate_stage_17_op__input_carry$77 + connect \op__invert_out$14 \core_calculate_stage_17_op__invert_out$78 + connect \op__write_cr__data$15 \core_calculate_stage_17_op__write_cr__data$79 + connect \op__write_cr__ok$16 \core_calculate_stage_17_op__write_cr__ok$80 + connect \op__output_carry$17 \core_calculate_stage_17_op__output_carry$81 + connect \op__is_32bit$18 \core_calculate_stage_17_op__is_32bit$82 + connect \op__is_signed$19 \core_calculate_stage_17_op__is_signed$83 + connect \op__data_len$20 \core_calculate_stage_17_op__data_len$84 + connect \op__insn$21 \core_calculate_stage_17_op__insn$85 + connect \ra$22 \core_calculate_stage_17_ra$86 + connect \rb$23 \core_calculate_stage_17_rb$87 + connect \xer_so$24 \core_calculate_stage_17_xer_so$88 + connect \divisor_neg$25 \core_calculate_stage_17_divisor_neg$89 + connect \dividend_neg$26 \core_calculate_stage_17_dividend_neg$90 + connect \divisor_radicand$27 \core_calculate_stage_17_divisor_radicand$91 + connect \operation$28 \core_calculate_stage_17_operation$92 + connect \quotient_root$29 \core_calculate_stage_17_quotient_root$93 + connect \root_times_radicand$30 \core_calculate_stage_17_root_times_radicand$94 + connect \compare_lhs$31 \core_calculate_stage_17_compare_lhs$95 + connect \compare_rhs$32 \core_calculate_stage_17_compare_rhs$96 + end + process $group_0 + assign \core_calculate_stage_16_muxid 2'00 + assign \core_calculate_stage_16_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_16_op__insn_type 7'0000000 + assign \core_calculate_stage_16_op__fn_unit 10'0000000000 + assign \core_calculate_stage_16_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_16_op__lk 1'0 + assign \core_calculate_stage_16_op__rc__rc 1'0 + assign \core_calculate_stage_16_op__rc__rc_ok 1'0 + assign \core_calculate_stage_16_op__oe__oe 1'0 + assign \core_calculate_stage_16_op__oe__oe_ok 1'0 + assign \core_calculate_stage_16_op__invert_a 1'0 + assign \core_calculate_stage_16_op__zero_a 1'0 + assign \core_calculate_stage_16_op__input_carry 2'00 + assign \core_calculate_stage_16_op__invert_out 1'0 + assign \core_calculate_stage_16_op__write_cr__data 3'000 + assign \core_calculate_stage_16_op__write_cr__ok 1'0 + assign \core_calculate_stage_16_op__output_carry 1'0 + assign \core_calculate_stage_16_op__is_32bit 1'0 + assign \core_calculate_stage_16_op__is_signed 1'0 + assign \core_calculate_stage_16_op__data_len 4'0000 + assign \core_calculate_stage_16_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_16_op__insn \core_calculate_stage_16_op__data_len \core_calculate_stage_16_op__is_signed \core_calculate_stage_16_op__is_32bit \core_calculate_stage_16_op__output_carry { \core_calculate_stage_16_op__write_cr__ok \core_calculate_stage_16_op__write_cr__data } \core_calculate_stage_16_op__invert_out \core_calculate_stage_16_op__input_carry \core_calculate_stage_16_op__zero_a \core_calculate_stage_16_op__invert_a { \core_calculate_stage_16_op__oe__oe_ok \core_calculate_stage_16_op__oe__oe } { \core_calculate_stage_16_op__rc__rc_ok \core_calculate_stage_16_op__rc__rc } \core_calculate_stage_16_op__lk { \core_calculate_stage_16_op__imm_data__imm_ok \core_calculate_stage_16_op__imm_data__imm } \core_calculate_stage_16_op__fn_unit \core_calculate_stage_16_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \core_calculate_stage_16_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_ra \ra + sync init + end + process $group_22 + assign \core_calculate_stage_16_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_rb \rb + sync init + end + process $group_23 + assign \core_calculate_stage_16_xer_so 1'0 + assign \core_calculate_stage_16_xer_so \xer_so + sync init + end + process $group_24 + assign \core_calculate_stage_16_divisor_neg 1'0 + assign \core_calculate_stage_16_divisor_neg \divisor_neg + sync init + end + process $group_25 + assign \core_calculate_stage_16_dividend_neg 1'0 + assign \core_calculate_stage_16_dividend_neg \dividend_neg + sync init + end + process $group_26 + assign \core_calculate_stage_16_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_calculate_stage_16_operation 2'00 + assign \core_calculate_stage_16_operation \operation + sync init + end + process $group_28 + assign \core_calculate_stage_16_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_calculate_stage_16_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_calculate_stage_16_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_calculate_stage_16_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_16_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \core_calculate_stage_17_muxid 2'00 + assign \core_calculate_stage_17_muxid \core_calculate_stage_16_muxid$33 + sync init + end + process $group_33 + assign \core_calculate_stage_17_op__insn_type 7'0000000 + assign \core_calculate_stage_17_op__fn_unit 10'0000000000 + assign \core_calculate_stage_17_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_17_op__lk 1'0 + assign \core_calculate_stage_17_op__rc__rc 1'0 + assign \core_calculate_stage_17_op__rc__rc_ok 1'0 + assign \core_calculate_stage_17_op__oe__oe 1'0 + assign \core_calculate_stage_17_op__oe__oe_ok 1'0 + assign \core_calculate_stage_17_op__invert_a 1'0 + assign \core_calculate_stage_17_op__zero_a 1'0 + assign \core_calculate_stage_17_op__input_carry 2'00 + assign \core_calculate_stage_17_op__invert_out 1'0 + assign \core_calculate_stage_17_op__write_cr__data 3'000 + assign \core_calculate_stage_17_op__write_cr__ok 1'0 + assign \core_calculate_stage_17_op__output_carry 1'0 + assign \core_calculate_stage_17_op__is_32bit 1'0 + assign \core_calculate_stage_17_op__is_signed 1'0 + assign \core_calculate_stage_17_op__data_len 4'0000 + assign \core_calculate_stage_17_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_17_op__insn \core_calculate_stage_17_op__data_len \core_calculate_stage_17_op__is_signed \core_calculate_stage_17_op__is_32bit \core_calculate_stage_17_op__output_carry { \core_calculate_stage_17_op__write_cr__ok \core_calculate_stage_17_op__write_cr__data } \core_calculate_stage_17_op__invert_out \core_calculate_stage_17_op__input_carry \core_calculate_stage_17_op__zero_a \core_calculate_stage_17_op__invert_a { \core_calculate_stage_17_op__oe__oe_ok \core_calculate_stage_17_op__oe__oe } { \core_calculate_stage_17_op__rc__rc_ok \core_calculate_stage_17_op__rc__rc } \core_calculate_stage_17_op__lk { \core_calculate_stage_17_op__imm_data__imm_ok \core_calculate_stage_17_op__imm_data__imm } \core_calculate_stage_17_op__fn_unit \core_calculate_stage_17_op__insn_type } { \core_calculate_stage_16_op__insn$53 \core_calculate_stage_16_op__data_len$52 \core_calculate_stage_16_op__is_signed$51 \core_calculate_stage_16_op__is_32bit$50 \core_calculate_stage_16_op__output_carry$49 { \core_calculate_stage_16_op__write_cr__ok$48 \core_calculate_stage_16_op__write_cr__data$47 } \core_calculate_stage_16_op__invert_out$46 \core_calculate_stage_16_op__input_carry$45 \core_calculate_stage_16_op__zero_a$44 \core_calculate_stage_16_op__invert_a$43 { \core_calculate_stage_16_op__oe__oe_ok$42 \core_calculate_stage_16_op__oe__oe$41 } { \core_calculate_stage_16_op__rc__rc_ok$40 \core_calculate_stage_16_op__rc__rc$39 } \core_calculate_stage_16_op__lk$38 { \core_calculate_stage_16_op__imm_data__imm_ok$37 \core_calculate_stage_16_op__imm_data__imm$36 } \core_calculate_stage_16_op__fn_unit$35 \core_calculate_stage_16_op__insn_type$34 } + sync init + end + process $group_53 + assign \core_calculate_stage_17_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_ra \core_calculate_stage_16_ra$54 + sync init + end + process $group_54 + assign \core_calculate_stage_17_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_rb \core_calculate_stage_16_rb$55 + sync init + end + process $group_55 + assign \core_calculate_stage_17_xer_so 1'0 + assign \core_calculate_stage_17_xer_so \core_calculate_stage_16_xer_so$56 + sync init + end + process $group_56 + assign \core_calculate_stage_17_divisor_neg 1'0 + assign \core_calculate_stage_17_divisor_neg \core_calculate_stage_16_divisor_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_17_dividend_neg 1'0 + assign \core_calculate_stage_17_dividend_neg \core_calculate_stage_16_dividend_neg$58 + sync init + end + process $group_58 + assign \core_calculate_stage_17_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_divisor_radicand \core_calculate_stage_16_divisor_radicand$59 + sync init + end + process $group_59 + assign \core_calculate_stage_17_operation 2'00 + assign \core_calculate_stage_17_operation \core_calculate_stage_16_operation$60 + sync init + end + process $group_60 + assign \core_calculate_stage_17_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_quotient_root \core_calculate_stage_16_quotient_root$61 + sync init + end + process $group_61 + assign \core_calculate_stage_17_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_root_times_radicand \core_calculate_stage_16_root_times_radicand$62 + sync init + end + process $group_62 + assign \core_calculate_stage_17_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_compare_lhs \core_calculate_stage_16_compare_lhs$63 + sync init + end + process $group_63 + assign \core_calculate_stage_17_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_17_compare_rhs \core_calculate_stage_16_compare_rhs$64 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$97 + process $group_64 + assign \p_valid_i$97 1'0 + assign \p_valid_i$97 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_65 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $98 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$97 + connect \B \p_ready_o + connect \Y $98 + end + process $group_66 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $98 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$100 + process $group_67 + assign \muxid$100 2'00 + assign \muxid$100 \core_calculate_stage_17_muxid$65 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$111 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$120 + process $group_68 + assign \op__insn_type$101 7'0000000 + assign \op__fn_unit$102 10'0000000000 + assign \op__imm_data__imm$103 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$104 1'0 + assign \op__lk$105 1'0 + assign \op__rc__rc$106 1'0 + assign \op__rc__rc_ok$107 1'0 + assign \op__oe__oe$108 1'0 + assign \op__oe__oe_ok$109 1'0 + assign \op__invert_a$110 1'0 + assign \op__zero_a$111 1'0 + assign \op__input_carry$112 2'00 + assign \op__invert_out$113 1'0 + assign \op__write_cr__data$114 3'000 + assign \op__write_cr__ok$115 1'0 + assign \op__output_carry$116 1'0 + assign \op__is_32bit$117 1'0 + assign \op__is_signed$118 1'0 + assign \op__data_len$119 4'0000 + assign \op__insn$120 32'00000000000000000000000000000000 + assign { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } { \core_calculate_stage_17_op__insn$85 \core_calculate_stage_17_op__data_len$84 \core_calculate_stage_17_op__is_signed$83 \core_calculate_stage_17_op__is_32bit$82 \core_calculate_stage_17_op__output_carry$81 { \core_calculate_stage_17_op__write_cr__ok$80 \core_calculate_stage_17_op__write_cr__data$79 } \core_calculate_stage_17_op__invert_out$78 \core_calculate_stage_17_op__input_carry$77 \core_calculate_stage_17_op__zero_a$76 \core_calculate_stage_17_op__invert_a$75 { \core_calculate_stage_17_op__oe__oe_ok$74 \core_calculate_stage_17_op__oe__oe$73 } { \core_calculate_stage_17_op__rc__rc_ok$72 \core_calculate_stage_17_op__rc__rc$71 } \core_calculate_stage_17_op__lk$70 { \core_calculate_stage_17_op__imm_data__imm_ok$69 \core_calculate_stage_17_op__imm_data__imm$68 } \core_calculate_stage_17_op__fn_unit$67 \core_calculate_stage_17_op__insn_type$66 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$121 + process $group_88 + assign \ra$121 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$121 \core_calculate_stage_17_ra$86 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$122 + process $group_89 + assign \rb$122 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$122 \core_calculate_stage_17_rb$87 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$123 + process $group_90 + assign \xer_so$123 1'0 + assign \xer_so$123 \core_calculate_stage_17_xer_so$88 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$124 + process $group_91 + assign \divisor_neg$124 1'0 + assign \divisor_neg$124 \core_calculate_stage_17_divisor_neg$89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$125 + process $group_92 + assign \dividend_neg$125 1'0 + assign \dividend_neg$125 \core_calculate_stage_17_dividend_neg$90 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$126 + process $group_93 + assign \divisor_radicand$126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$126 \core_calculate_stage_17_divisor_radicand$91 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$127 + process $group_94 + assign \operation$127 2'00 + assign \operation$127 \core_calculate_stage_17_operation$92 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$128 + process $group_95 + assign \quotient_root$128 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$128 \core_calculate_stage_17_quotient_root$93 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$129 + process $group_96 + assign \root_times_radicand$129 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$129 \core_calculate_stage_17_root_times_radicand$94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$130 + process $group_97 + assign \compare_lhs$130 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$130 \core_calculate_stage_17_compare_lhs$95 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$131 + process $group_98 + assign \compare_rhs$131 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$131 \core_calculate_stage_17_compare_rhs$96 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_99 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_100 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$100 + end + sync init + update \muxid$1 2'00 + sync posedge \clk + update \muxid$1 \muxid$1$next + end + process $group_101 + assign \op__insn_type$2$next \op__insn_type$2 + assign \op__fn_unit$3$next \op__fn_unit$3 + assign \op__imm_data__imm$4$next \op__imm_data__imm$4 + assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5 + assign \op__lk$6$next \op__lk$6 + assign \op__rc__rc$7$next \op__rc__rc$7 + assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8 + assign \op__oe__oe$9$next \op__oe__oe$9 + assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10 + assign \op__invert_a$11$next \op__invert_a$11 + assign \op__zero_a$12$next \op__zero_a$12 + assign \op__input_carry$13$next \op__input_carry$13 + assign \op__invert_out$14$next \op__invert_out$14 + assign \op__write_cr__data$15$next \op__write_cr__data$15 + assign \op__write_cr__ok$16$next \op__write_cr__ok$16 + assign \op__output_carry$17$next \op__output_carry$17 + assign \op__is_32bit$18$next \op__is_32bit$18 + assign \op__is_signed$19$next \op__is_signed$19 + assign \op__data_len$20$next \op__data_len$20 + assign \op__insn$21$next \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5$next 1'0 + assign \op__rc__rc$7$next 1'0 + assign \op__rc__rc_ok$8$next 1'0 + assign \op__oe__oe$9$next 1'0 + assign \op__oe__oe_ok$10$next 1'0 + assign \op__write_cr__data$15$next 3'000 + assign \op__write_cr__ok$16$next 1'0 + assign \op__insn$21$next 32'00000000000000000000000000000000 + end + sync init + update \op__insn_type$2 7'0000000 + update \op__fn_unit$3 10'0000000000 + update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \op__imm_data__imm_ok$5 1'0 + update \op__lk$6 1'0 + update \op__rc__rc$7 1'0 + update \op__rc__rc_ok$8 1'0 + update \op__oe__oe$9 1'0 + update \op__oe__oe_ok$10 1'0 + update \op__invert_a$11 1'0 + update \op__zero_a$12 1'0 + update \op__input_carry$13 2'00 + update \op__invert_out$14 1'0 + update \op__write_cr__data$15 3'000 + update \op__write_cr__ok$16 1'0 + update \op__output_carry$17 1'0 + update \op__is_32bit$18 1'0 + update \op__is_signed$19 1'0 + update \op__data_len$20 4'0000 + update \op__insn$21 32'00000000000000000000000000000000 + sync posedge \clk + update \op__insn_type$2 \op__insn_type$2$next + update \op__fn_unit$3 \op__fn_unit$3$next + update \op__imm_data__imm$4 \op__imm_data__imm$4$next + update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next + update \op__lk$6 \op__lk$6$next + update \op__rc__rc$7 \op__rc__rc$7$next + update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next + update \op__oe__oe$9 \op__oe__oe$9$next + update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next + update \op__invert_a$11 \op__invert_a$11$next + update \op__zero_a$12 \op__zero_a$12$next + update \op__input_carry$13 \op__input_carry$13$next + update \op__invert_out$14 \op__invert_out$14$next + update \op__write_cr__data$15 \op__write_cr__data$15$next + update \op__write_cr__ok$16 \op__write_cr__ok$16$next + update \op__output_carry$17 \op__output_carry$17$next + update \op__is_32bit$18 \op__is_32bit$18$next + update \op__is_signed$19 \op__is_signed$19$next + update \op__data_len$20 \op__data_len$20$next + update \op__insn$21 \op__insn$21$next + end + process $group_121 + assign \ra$22$next \ra$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$22$next \ra$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$22$next \ra$121 + end + sync init + update \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \ra$22 \ra$22$next + end + process $group_122 + assign \rb$23$next \rb$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$23$next \rb$122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$23$next \rb$122 + end + sync init + update \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \rb$23 \rb$23$next + end + process $group_123 + assign \xer_so$24$next \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$24$next \xer_so$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$24$next \xer_so$123 + end + sync init + update \xer_so$24 1'0 + sync posedge \clk + update \xer_so$24 \xer_so$24$next + end + process $group_124 + assign \divisor_neg$25$next \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$25$next \divisor_neg$124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$25$next \divisor_neg$124 + end + sync init + update \divisor_neg$25 1'0 + sync posedge \clk + update \divisor_neg$25 \divisor_neg$25$next + end + process $group_125 + assign \dividend_neg$26$next \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$26$next \dividend_neg$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$26$next \dividend_neg$125 + end + sync init + update \dividend_neg$26 1'0 + sync posedge \clk + update \dividend_neg$26 \dividend_neg$26$next + end + process $group_126 + assign \divisor_radicand$27$next \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$27$next \divisor_radicand$126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$27$next \divisor_radicand$126 + end + sync init + update \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \divisor_radicand$27 \divisor_radicand$27$next + end + process $group_127 + assign \operation$28$next \operation$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$28$next \operation$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$28$next \operation$127 + end + sync init + update \operation$28 2'00 + sync posedge \clk + update \operation$28 \operation$28$next + end + process $group_128 + assign \quotient_root$29$next \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$29$next \quotient_root$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$29$next \quotient_root$128 + end + sync init + update \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \quotient_root$29 \quotient_root$29$next + end + process $group_129 + assign \root_times_radicand$30$next \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$30$next \root_times_radicand$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$30$next \root_times_radicand$129 + end + sync init + update \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \root_times_radicand$30 \root_times_radicand$30$next + end + process $group_130 + assign \compare_lhs$31$next \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$31$next \compare_lhs$130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$31$next \compare_lhs$130 + end + sync init + update \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_lhs$31 \compare_lhs$31$next + end + process $group_131 + assign \compare_rhs$32$next \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$32$next \compare_rhs$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$32$next \compare_rhs$131 + end + sync init + update \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_rhs$32 \compare_rhs$32$next + end + process $group_132 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_133 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.p" +module \p$241 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.n" +module \n$242 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_18.core.trial0" +module \trial0$244 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000000 + connect \B 7'1001110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_18.core.trial1" +module \trial1$245 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000001 + connect \B 7'1001110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_18.core.trial2" +module \trial2$246 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000100 + connect \B 7'1001110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_18.core.trial3" +module \trial3$247 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'001001 + connect \B 7'1001110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_18.core.trial4" +module \trial4$248 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'010000 + connect \B 7'1001110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_18.core.trial5" +module \trial5$249 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'011001 + connect \B 7'1001110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_18.core.trial6" +module \trial6$250 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'100100 + connect \B 7'1001110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_18.core.trial7" +module \trial7$251 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000111 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1001000 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'110001 + connect \B 7'1001110 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 219 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 219 + connect \A \rr_times_trial_bits + connect \B 4'1000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 220 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 219 + parameter \Y_WIDTH 220 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1110 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 221 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 220 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 221 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_18.core.pe" +module \pe$252 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_18.core" +module \core$243 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$244 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$245 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$246 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$247 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$248 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$249 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$250 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$251 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$252 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 10 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 10 + connect \A \next_bits + connect \B 3'111 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 74 $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 74 + connect \A $35 + connect \B 3'111 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 74 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B $37 + connect \Y $39 + end + connect $34 $39 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $34 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_18" +module \core_calculate_stage_18 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$243 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_19.core.trial0" +module \trial0$254 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000000 + connect \B 7'1001000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 211 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 211 + connect \A \rr_times_trial_bits + connect \B 3'101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 212 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 211 + parameter \Y_WIDTH 212 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 212 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 213 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_19.core.trial1" +module \trial1$255 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000001 + connect \B 7'1001000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 211 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 211 + connect \A \rr_times_trial_bits + connect \B 3'101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 212 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 211 + parameter \Y_WIDTH 212 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 212 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 213 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_19.core.trial2" +module \trial2$256 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000100 + connect \B 7'1001000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 211 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 211 + connect \A \rr_times_trial_bits + connect \B 3'101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 212 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 211 + parameter \Y_WIDTH 212 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 212 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 213 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_19.core.trial3" +module \trial3$257 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'001001 + connect \B 7'1001000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 211 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 211 + connect \A \rr_times_trial_bits + connect \B 3'101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 212 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 211 + parameter \Y_WIDTH 212 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 212 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 213 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_19.core.trial4" +module \trial4$258 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'010000 + connect \B 7'1001000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 211 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 211 + connect \A \rr_times_trial_bits + connect \B 3'101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 212 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 211 + parameter \Y_WIDTH 212 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 212 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 213 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_19.core.trial5" +module \trial5$259 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'011001 + connect \B 7'1001000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 211 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 211 + connect \A \rr_times_trial_bits + connect \B 3'101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 212 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 211 + parameter \Y_WIDTH 212 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 212 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 213 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_19.core.trial6" +module \trial6$260 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'100100 + connect \B 7'1001000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 211 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 211 + connect \A \rr_times_trial_bits + connect \B 3'101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 212 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 211 + parameter \Y_WIDTH 212 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 212 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 213 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_19.core.trial7" +module \trial7$261 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000100 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000101 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'110001 + connect \B 7'1001000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 211 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 211 + connect \A \rr_times_trial_bits + connect \B 3'101 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 212 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 211 + parameter \Y_WIDTH 212 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 85 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 85 + connect \A \dr_times_trial_bits_sqrd + connect \B 4'1000 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 213 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 212 + parameter \B_SIGNED 0 + parameter \B_WIDTH 85 + parameter \Y_WIDTH 213 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_19.core.pe" +module \pe$262 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_19.core" +module \core$253 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$254 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$255 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$256 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$257 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$258 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$259 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$260 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$261 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$262 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 10 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 10 + connect \A \next_bits + connect \B 3'100 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 74 $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 74 + connect \A $35 + connect \B 3'100 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 74 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B $37 + connect \Y $39 + end + connect $34 $39 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $34 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20.core_calculate_stage_19" +module \core_calculate_stage_19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$253 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_18_to_20" +module \pipe_18_to_20 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 4 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 5 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 7 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 16 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 18 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 20 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 21 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 22 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 23 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 24 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 25 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 26 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 28 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 29 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 30 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 31 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 32 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 33 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 34 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 35 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 36 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 37 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 38 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$1$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 39 \op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 40 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 41 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 46 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 50 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 51 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 52 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 53 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 54 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 55 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 56 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 57 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 58 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 59 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 60 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 61 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 62 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 63 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$26$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 64 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 65 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 66 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 67 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 68 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 69 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$32$next + cell \p$241 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$242 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_18_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_18_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_18_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_18_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_18_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_18_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_18_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_18_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_18_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_18_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_18_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_18_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_18_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_18_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_18_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_18_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_18_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_18_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_18_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_18_muxid$33 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_18_op__insn_type$34 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_18_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_18_op__imm_data__imm$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__imm_data__imm_ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__lk$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__invert_a$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_18_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_18_op__write_cr__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__write_cr__ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__output_carry$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__is_32bit$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_18_op__is_signed$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_18_op__data_len$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_18_op__insn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_18_ra$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_18_rb$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_18_xer_so$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_18_divisor_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_18_dividend_neg$58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_18_divisor_radicand$59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_18_operation$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_18_quotient_root$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_18_root_times_radicand$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_18_compare_lhs$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_18_compare_rhs$64 + cell \core_calculate_stage_18 \core_calculate_stage_18 + connect \muxid \core_calculate_stage_18_muxid + connect \op__insn_type \core_calculate_stage_18_op__insn_type + connect \op__fn_unit \core_calculate_stage_18_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_18_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_18_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_18_op__lk + connect \op__rc__rc \core_calculate_stage_18_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_18_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_18_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_18_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_18_op__invert_a + connect \op__zero_a \core_calculate_stage_18_op__zero_a + connect \op__input_carry \core_calculate_stage_18_op__input_carry + connect \op__invert_out \core_calculate_stage_18_op__invert_out + connect \op__write_cr__data \core_calculate_stage_18_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_18_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_18_op__output_carry + connect \op__is_32bit \core_calculate_stage_18_op__is_32bit + connect \op__is_signed \core_calculate_stage_18_op__is_signed + connect \op__data_len \core_calculate_stage_18_op__data_len + connect \op__insn \core_calculate_stage_18_op__insn + connect \ra \core_calculate_stage_18_ra + connect \rb \core_calculate_stage_18_rb + connect \xer_so \core_calculate_stage_18_xer_so + connect \divisor_neg \core_calculate_stage_18_divisor_neg + connect \dividend_neg \core_calculate_stage_18_dividend_neg + connect \divisor_radicand \core_calculate_stage_18_divisor_radicand + connect \operation \core_calculate_stage_18_operation + connect \quotient_root \core_calculate_stage_18_quotient_root + connect \root_times_radicand \core_calculate_stage_18_root_times_radicand + connect \compare_lhs \core_calculate_stage_18_compare_lhs + connect \compare_rhs \core_calculate_stage_18_compare_rhs + connect \muxid$1 \core_calculate_stage_18_muxid$33 + connect \op__insn_type$2 \core_calculate_stage_18_op__insn_type$34 + connect \op__fn_unit$3 \core_calculate_stage_18_op__fn_unit$35 + connect \op__imm_data__imm$4 \core_calculate_stage_18_op__imm_data__imm$36 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_18_op__imm_data__imm_ok$37 + connect \op__lk$6 \core_calculate_stage_18_op__lk$38 + connect \op__rc__rc$7 \core_calculate_stage_18_op__rc__rc$39 + connect \op__rc__rc_ok$8 \core_calculate_stage_18_op__rc__rc_ok$40 + connect \op__oe__oe$9 \core_calculate_stage_18_op__oe__oe$41 + connect \op__oe__oe_ok$10 \core_calculate_stage_18_op__oe__oe_ok$42 + connect \op__invert_a$11 \core_calculate_stage_18_op__invert_a$43 + connect \op__zero_a$12 \core_calculate_stage_18_op__zero_a$44 + connect \op__input_carry$13 \core_calculate_stage_18_op__input_carry$45 + connect \op__invert_out$14 \core_calculate_stage_18_op__invert_out$46 + connect \op__write_cr__data$15 \core_calculate_stage_18_op__write_cr__data$47 + connect \op__write_cr__ok$16 \core_calculate_stage_18_op__write_cr__ok$48 + connect \op__output_carry$17 \core_calculate_stage_18_op__output_carry$49 + connect \op__is_32bit$18 \core_calculate_stage_18_op__is_32bit$50 + connect \op__is_signed$19 \core_calculate_stage_18_op__is_signed$51 + connect \op__data_len$20 \core_calculate_stage_18_op__data_len$52 + connect \op__insn$21 \core_calculate_stage_18_op__insn$53 + connect \ra$22 \core_calculate_stage_18_ra$54 + connect \rb$23 \core_calculate_stage_18_rb$55 + connect \xer_so$24 \core_calculate_stage_18_xer_so$56 + connect \divisor_neg$25 \core_calculate_stage_18_divisor_neg$57 + connect \dividend_neg$26 \core_calculate_stage_18_dividend_neg$58 + connect \divisor_radicand$27 \core_calculate_stage_18_divisor_radicand$59 + connect \operation$28 \core_calculate_stage_18_operation$60 + connect \quotient_root$29 \core_calculate_stage_18_quotient_root$61 + connect \root_times_radicand$30 \core_calculate_stage_18_root_times_radicand$62 + connect \compare_lhs$31 \core_calculate_stage_18_compare_lhs$63 + connect \compare_rhs$32 \core_calculate_stage_18_compare_rhs$64 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_19_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_19_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_19_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_19_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_19_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_19_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_19_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_19_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_19_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_19_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_19_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_19_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_19_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_19_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_19_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_19_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_19_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_19_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_19_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_19_muxid$65 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_19_op__insn_type$66 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_19_op__fn_unit$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_19_op__imm_data__imm$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__imm_data__imm_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__lk$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__rc__rc_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__oe__oe_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__invert_a$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__zero_a$76 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_19_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_19_op__write_cr__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__write_cr__ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_19_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_19_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_19_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_19_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_19_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_19_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_19_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_19_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_19_divisor_radicand$91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_19_operation$92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_19_quotient_root$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_19_root_times_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_19_compare_lhs$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_19_compare_rhs$96 + cell \core_calculate_stage_19 \core_calculate_stage_19 + connect \muxid \core_calculate_stage_19_muxid + connect \op__insn_type \core_calculate_stage_19_op__insn_type + connect \op__fn_unit \core_calculate_stage_19_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_19_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_19_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_19_op__lk + connect \op__rc__rc \core_calculate_stage_19_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_19_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_19_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_19_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_19_op__invert_a + connect \op__zero_a \core_calculate_stage_19_op__zero_a + connect \op__input_carry \core_calculate_stage_19_op__input_carry + connect \op__invert_out \core_calculate_stage_19_op__invert_out + connect \op__write_cr__data \core_calculate_stage_19_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_19_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_19_op__output_carry + connect \op__is_32bit \core_calculate_stage_19_op__is_32bit + connect \op__is_signed \core_calculate_stage_19_op__is_signed + connect \op__data_len \core_calculate_stage_19_op__data_len + connect \op__insn \core_calculate_stage_19_op__insn + connect \ra \core_calculate_stage_19_ra + connect \rb \core_calculate_stage_19_rb + connect \xer_so \core_calculate_stage_19_xer_so + connect \divisor_neg \core_calculate_stage_19_divisor_neg + connect \dividend_neg \core_calculate_stage_19_dividend_neg + connect \divisor_radicand \core_calculate_stage_19_divisor_radicand + connect \operation \core_calculate_stage_19_operation + connect \quotient_root \core_calculate_stage_19_quotient_root + connect \root_times_radicand \core_calculate_stage_19_root_times_radicand + connect \compare_lhs \core_calculate_stage_19_compare_lhs + connect \compare_rhs \core_calculate_stage_19_compare_rhs + connect \muxid$1 \core_calculate_stage_19_muxid$65 + connect \op__insn_type$2 \core_calculate_stage_19_op__insn_type$66 + connect \op__fn_unit$3 \core_calculate_stage_19_op__fn_unit$67 + connect \op__imm_data__imm$4 \core_calculate_stage_19_op__imm_data__imm$68 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_19_op__imm_data__imm_ok$69 + connect \op__lk$6 \core_calculate_stage_19_op__lk$70 + connect \op__rc__rc$7 \core_calculate_stage_19_op__rc__rc$71 + connect \op__rc__rc_ok$8 \core_calculate_stage_19_op__rc__rc_ok$72 + connect \op__oe__oe$9 \core_calculate_stage_19_op__oe__oe$73 + connect \op__oe__oe_ok$10 \core_calculate_stage_19_op__oe__oe_ok$74 + connect \op__invert_a$11 \core_calculate_stage_19_op__invert_a$75 + connect \op__zero_a$12 \core_calculate_stage_19_op__zero_a$76 + connect \op__input_carry$13 \core_calculate_stage_19_op__input_carry$77 + connect \op__invert_out$14 \core_calculate_stage_19_op__invert_out$78 + connect \op__write_cr__data$15 \core_calculate_stage_19_op__write_cr__data$79 + connect \op__write_cr__ok$16 \core_calculate_stage_19_op__write_cr__ok$80 + connect \op__output_carry$17 \core_calculate_stage_19_op__output_carry$81 + connect \op__is_32bit$18 \core_calculate_stage_19_op__is_32bit$82 + connect \op__is_signed$19 \core_calculate_stage_19_op__is_signed$83 + connect \op__data_len$20 \core_calculate_stage_19_op__data_len$84 + connect \op__insn$21 \core_calculate_stage_19_op__insn$85 + connect \ra$22 \core_calculate_stage_19_ra$86 + connect \rb$23 \core_calculate_stage_19_rb$87 + connect \xer_so$24 \core_calculate_stage_19_xer_so$88 + connect \divisor_neg$25 \core_calculate_stage_19_divisor_neg$89 + connect \dividend_neg$26 \core_calculate_stage_19_dividend_neg$90 + connect \divisor_radicand$27 \core_calculate_stage_19_divisor_radicand$91 + connect \operation$28 \core_calculate_stage_19_operation$92 + connect \quotient_root$29 \core_calculate_stage_19_quotient_root$93 + connect \root_times_radicand$30 \core_calculate_stage_19_root_times_radicand$94 + connect \compare_lhs$31 \core_calculate_stage_19_compare_lhs$95 + connect \compare_rhs$32 \core_calculate_stage_19_compare_rhs$96 + end + process $group_0 + assign \core_calculate_stage_18_muxid 2'00 + assign \core_calculate_stage_18_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_18_op__insn_type 7'0000000 + assign \core_calculate_stage_18_op__fn_unit 10'0000000000 + assign \core_calculate_stage_18_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_18_op__lk 1'0 + assign \core_calculate_stage_18_op__rc__rc 1'0 + assign \core_calculate_stage_18_op__rc__rc_ok 1'0 + assign \core_calculate_stage_18_op__oe__oe 1'0 + assign \core_calculate_stage_18_op__oe__oe_ok 1'0 + assign \core_calculate_stage_18_op__invert_a 1'0 + assign \core_calculate_stage_18_op__zero_a 1'0 + assign \core_calculate_stage_18_op__input_carry 2'00 + assign \core_calculate_stage_18_op__invert_out 1'0 + assign \core_calculate_stage_18_op__write_cr__data 3'000 + assign \core_calculate_stage_18_op__write_cr__ok 1'0 + assign \core_calculate_stage_18_op__output_carry 1'0 + assign \core_calculate_stage_18_op__is_32bit 1'0 + assign \core_calculate_stage_18_op__is_signed 1'0 + assign \core_calculate_stage_18_op__data_len 4'0000 + assign \core_calculate_stage_18_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_18_op__insn \core_calculate_stage_18_op__data_len \core_calculate_stage_18_op__is_signed \core_calculate_stage_18_op__is_32bit \core_calculate_stage_18_op__output_carry { \core_calculate_stage_18_op__write_cr__ok \core_calculate_stage_18_op__write_cr__data } \core_calculate_stage_18_op__invert_out \core_calculate_stage_18_op__input_carry \core_calculate_stage_18_op__zero_a \core_calculate_stage_18_op__invert_a { \core_calculate_stage_18_op__oe__oe_ok \core_calculate_stage_18_op__oe__oe } { \core_calculate_stage_18_op__rc__rc_ok \core_calculate_stage_18_op__rc__rc } \core_calculate_stage_18_op__lk { \core_calculate_stage_18_op__imm_data__imm_ok \core_calculate_stage_18_op__imm_data__imm } \core_calculate_stage_18_op__fn_unit \core_calculate_stage_18_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \core_calculate_stage_18_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_ra \ra + sync init + end + process $group_22 + assign \core_calculate_stage_18_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_rb \rb + sync init + end + process $group_23 + assign \core_calculate_stage_18_xer_so 1'0 + assign \core_calculate_stage_18_xer_so \xer_so + sync init + end + process $group_24 + assign \core_calculate_stage_18_divisor_neg 1'0 + assign \core_calculate_stage_18_divisor_neg \divisor_neg + sync init + end + process $group_25 + assign \core_calculate_stage_18_dividend_neg 1'0 + assign \core_calculate_stage_18_dividend_neg \dividend_neg + sync init + end + process $group_26 + assign \core_calculate_stage_18_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_calculate_stage_18_operation 2'00 + assign \core_calculate_stage_18_operation \operation + sync init + end + process $group_28 + assign \core_calculate_stage_18_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_calculate_stage_18_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_calculate_stage_18_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_calculate_stage_18_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_18_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \core_calculate_stage_19_muxid 2'00 + assign \core_calculate_stage_19_muxid \core_calculate_stage_18_muxid$33 + sync init + end + process $group_33 + assign \core_calculate_stage_19_op__insn_type 7'0000000 + assign \core_calculate_stage_19_op__fn_unit 10'0000000000 + assign \core_calculate_stage_19_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_19_op__lk 1'0 + assign \core_calculate_stage_19_op__rc__rc 1'0 + assign \core_calculate_stage_19_op__rc__rc_ok 1'0 + assign \core_calculate_stage_19_op__oe__oe 1'0 + assign \core_calculate_stage_19_op__oe__oe_ok 1'0 + assign \core_calculate_stage_19_op__invert_a 1'0 + assign \core_calculate_stage_19_op__zero_a 1'0 + assign \core_calculate_stage_19_op__input_carry 2'00 + assign \core_calculate_stage_19_op__invert_out 1'0 + assign \core_calculate_stage_19_op__write_cr__data 3'000 + assign \core_calculate_stage_19_op__write_cr__ok 1'0 + assign \core_calculate_stage_19_op__output_carry 1'0 + assign \core_calculate_stage_19_op__is_32bit 1'0 + assign \core_calculate_stage_19_op__is_signed 1'0 + assign \core_calculate_stage_19_op__data_len 4'0000 + assign \core_calculate_stage_19_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_19_op__insn \core_calculate_stage_19_op__data_len \core_calculate_stage_19_op__is_signed \core_calculate_stage_19_op__is_32bit \core_calculate_stage_19_op__output_carry { \core_calculate_stage_19_op__write_cr__ok \core_calculate_stage_19_op__write_cr__data } \core_calculate_stage_19_op__invert_out \core_calculate_stage_19_op__input_carry \core_calculate_stage_19_op__zero_a \core_calculate_stage_19_op__invert_a { \core_calculate_stage_19_op__oe__oe_ok \core_calculate_stage_19_op__oe__oe } { \core_calculate_stage_19_op__rc__rc_ok \core_calculate_stage_19_op__rc__rc } \core_calculate_stage_19_op__lk { \core_calculate_stage_19_op__imm_data__imm_ok \core_calculate_stage_19_op__imm_data__imm } \core_calculate_stage_19_op__fn_unit \core_calculate_stage_19_op__insn_type } { \core_calculate_stage_18_op__insn$53 \core_calculate_stage_18_op__data_len$52 \core_calculate_stage_18_op__is_signed$51 \core_calculate_stage_18_op__is_32bit$50 \core_calculate_stage_18_op__output_carry$49 { \core_calculate_stage_18_op__write_cr__ok$48 \core_calculate_stage_18_op__write_cr__data$47 } \core_calculate_stage_18_op__invert_out$46 \core_calculate_stage_18_op__input_carry$45 \core_calculate_stage_18_op__zero_a$44 \core_calculate_stage_18_op__invert_a$43 { \core_calculate_stage_18_op__oe__oe_ok$42 \core_calculate_stage_18_op__oe__oe$41 } { \core_calculate_stage_18_op__rc__rc_ok$40 \core_calculate_stage_18_op__rc__rc$39 } \core_calculate_stage_18_op__lk$38 { \core_calculate_stage_18_op__imm_data__imm_ok$37 \core_calculate_stage_18_op__imm_data__imm$36 } \core_calculate_stage_18_op__fn_unit$35 \core_calculate_stage_18_op__insn_type$34 } + sync init + end + process $group_53 + assign \core_calculate_stage_19_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_ra \core_calculate_stage_18_ra$54 + sync init + end + process $group_54 + assign \core_calculate_stage_19_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_rb \core_calculate_stage_18_rb$55 + sync init + end + process $group_55 + assign \core_calculate_stage_19_xer_so 1'0 + assign \core_calculate_stage_19_xer_so \core_calculate_stage_18_xer_so$56 + sync init + end + process $group_56 + assign \core_calculate_stage_19_divisor_neg 1'0 + assign \core_calculate_stage_19_divisor_neg \core_calculate_stage_18_divisor_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_19_dividend_neg 1'0 + assign \core_calculate_stage_19_dividend_neg \core_calculate_stage_18_dividend_neg$58 + sync init + end + process $group_58 + assign \core_calculate_stage_19_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_divisor_radicand \core_calculate_stage_18_divisor_radicand$59 + sync init + end + process $group_59 + assign \core_calculate_stage_19_operation 2'00 + assign \core_calculate_stage_19_operation \core_calculate_stage_18_operation$60 + sync init + end + process $group_60 + assign \core_calculate_stage_19_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_quotient_root \core_calculate_stage_18_quotient_root$61 + sync init + end + process $group_61 + assign \core_calculate_stage_19_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_root_times_radicand \core_calculate_stage_18_root_times_radicand$62 + sync init + end + process $group_62 + assign \core_calculate_stage_19_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_compare_lhs \core_calculate_stage_18_compare_lhs$63 + sync init + end + process $group_63 + assign \core_calculate_stage_19_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_19_compare_rhs \core_calculate_stage_18_compare_rhs$64 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$97 + process $group_64 + assign \p_valid_i$97 1'0 + assign \p_valid_i$97 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_65 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $98 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$97 + connect \B \p_ready_o + connect \Y $98 + end + process $group_66 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $98 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$100 + process $group_67 + assign \muxid$100 2'00 + assign \muxid$100 \core_calculate_stage_19_muxid$65 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$111 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$120 + process $group_68 + assign \op__insn_type$101 7'0000000 + assign \op__fn_unit$102 10'0000000000 + assign \op__imm_data__imm$103 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$104 1'0 + assign \op__lk$105 1'0 + assign \op__rc__rc$106 1'0 + assign \op__rc__rc_ok$107 1'0 + assign \op__oe__oe$108 1'0 + assign \op__oe__oe_ok$109 1'0 + assign \op__invert_a$110 1'0 + assign \op__zero_a$111 1'0 + assign \op__input_carry$112 2'00 + assign \op__invert_out$113 1'0 + assign \op__write_cr__data$114 3'000 + assign \op__write_cr__ok$115 1'0 + assign \op__output_carry$116 1'0 + assign \op__is_32bit$117 1'0 + assign \op__is_signed$118 1'0 + assign \op__data_len$119 4'0000 + assign \op__insn$120 32'00000000000000000000000000000000 + assign { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } { \core_calculate_stage_19_op__insn$85 \core_calculate_stage_19_op__data_len$84 \core_calculate_stage_19_op__is_signed$83 \core_calculate_stage_19_op__is_32bit$82 \core_calculate_stage_19_op__output_carry$81 { \core_calculate_stage_19_op__write_cr__ok$80 \core_calculate_stage_19_op__write_cr__data$79 } \core_calculate_stage_19_op__invert_out$78 \core_calculate_stage_19_op__input_carry$77 \core_calculate_stage_19_op__zero_a$76 \core_calculate_stage_19_op__invert_a$75 { \core_calculate_stage_19_op__oe__oe_ok$74 \core_calculate_stage_19_op__oe__oe$73 } { \core_calculate_stage_19_op__rc__rc_ok$72 \core_calculate_stage_19_op__rc__rc$71 } \core_calculate_stage_19_op__lk$70 { \core_calculate_stage_19_op__imm_data__imm_ok$69 \core_calculate_stage_19_op__imm_data__imm$68 } \core_calculate_stage_19_op__fn_unit$67 \core_calculate_stage_19_op__insn_type$66 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$121 + process $group_88 + assign \ra$121 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$121 \core_calculate_stage_19_ra$86 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$122 + process $group_89 + assign \rb$122 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$122 \core_calculate_stage_19_rb$87 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$123 + process $group_90 + assign \xer_so$123 1'0 + assign \xer_so$123 \core_calculate_stage_19_xer_so$88 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$124 + process $group_91 + assign \divisor_neg$124 1'0 + assign \divisor_neg$124 \core_calculate_stage_19_divisor_neg$89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$125 + process $group_92 + assign \dividend_neg$125 1'0 + assign \dividend_neg$125 \core_calculate_stage_19_dividend_neg$90 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$126 + process $group_93 + assign \divisor_radicand$126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$126 \core_calculate_stage_19_divisor_radicand$91 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$127 + process $group_94 + assign \operation$127 2'00 + assign \operation$127 \core_calculate_stage_19_operation$92 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$128 + process $group_95 + assign \quotient_root$128 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$128 \core_calculate_stage_19_quotient_root$93 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$129 + process $group_96 + assign \root_times_radicand$129 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$129 \core_calculate_stage_19_root_times_radicand$94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$130 + process $group_97 + assign \compare_lhs$130 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$130 \core_calculate_stage_19_compare_lhs$95 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$131 + process $group_98 + assign \compare_rhs$131 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$131 \core_calculate_stage_19_compare_rhs$96 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_99 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_100 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$100 + end + sync init + update \muxid$1 2'00 + sync posedge \clk + update \muxid$1 \muxid$1$next + end + process $group_101 + assign \op__insn_type$2$next \op__insn_type$2 + assign \op__fn_unit$3$next \op__fn_unit$3 + assign \op__imm_data__imm$4$next \op__imm_data__imm$4 + assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5 + assign \op__lk$6$next \op__lk$6 + assign \op__rc__rc$7$next \op__rc__rc$7 + assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8 + assign \op__oe__oe$9$next \op__oe__oe$9 + assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10 + assign \op__invert_a$11$next \op__invert_a$11 + assign \op__zero_a$12$next \op__zero_a$12 + assign \op__input_carry$13$next \op__input_carry$13 + assign \op__invert_out$14$next \op__invert_out$14 + assign \op__write_cr__data$15$next \op__write_cr__data$15 + assign \op__write_cr__ok$16$next \op__write_cr__ok$16 + assign \op__output_carry$17$next \op__output_carry$17 + assign \op__is_32bit$18$next \op__is_32bit$18 + assign \op__is_signed$19$next \op__is_signed$19 + assign \op__data_len$20$next \op__data_len$20 + assign \op__insn$21$next \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5$next 1'0 + assign \op__rc__rc$7$next 1'0 + assign \op__rc__rc_ok$8$next 1'0 + assign \op__oe__oe$9$next 1'0 + assign \op__oe__oe_ok$10$next 1'0 + assign \op__write_cr__data$15$next 3'000 + assign \op__write_cr__ok$16$next 1'0 + assign \op__insn$21$next 32'00000000000000000000000000000000 + end + sync init + update \op__insn_type$2 7'0000000 + update \op__fn_unit$3 10'0000000000 + update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \op__imm_data__imm_ok$5 1'0 + update \op__lk$6 1'0 + update \op__rc__rc$7 1'0 + update \op__rc__rc_ok$8 1'0 + update \op__oe__oe$9 1'0 + update \op__oe__oe_ok$10 1'0 + update \op__invert_a$11 1'0 + update \op__zero_a$12 1'0 + update \op__input_carry$13 2'00 + update \op__invert_out$14 1'0 + update \op__write_cr__data$15 3'000 + update \op__write_cr__ok$16 1'0 + update \op__output_carry$17 1'0 + update \op__is_32bit$18 1'0 + update \op__is_signed$19 1'0 + update \op__data_len$20 4'0000 + update \op__insn$21 32'00000000000000000000000000000000 + sync posedge \clk + update \op__insn_type$2 \op__insn_type$2$next + update \op__fn_unit$3 \op__fn_unit$3$next + update \op__imm_data__imm$4 \op__imm_data__imm$4$next + update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next + update \op__lk$6 \op__lk$6$next + update \op__rc__rc$7 \op__rc__rc$7$next + update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next + update \op__oe__oe$9 \op__oe__oe$9$next + update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next + update \op__invert_a$11 \op__invert_a$11$next + update \op__zero_a$12 \op__zero_a$12$next + update \op__input_carry$13 \op__input_carry$13$next + update \op__invert_out$14 \op__invert_out$14$next + update \op__write_cr__data$15 \op__write_cr__data$15$next + update \op__write_cr__ok$16 \op__write_cr__ok$16$next + update \op__output_carry$17 \op__output_carry$17$next + update \op__is_32bit$18 \op__is_32bit$18$next + update \op__is_signed$19 \op__is_signed$19$next + update \op__data_len$20 \op__data_len$20$next + update \op__insn$21 \op__insn$21$next + end + process $group_121 + assign \ra$22$next \ra$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$22$next \ra$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$22$next \ra$121 + end + sync init + update \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \ra$22 \ra$22$next + end + process $group_122 + assign \rb$23$next \rb$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$23$next \rb$122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$23$next \rb$122 + end + sync init + update \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \rb$23 \rb$23$next + end + process $group_123 + assign \xer_so$24$next \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$24$next \xer_so$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$24$next \xer_so$123 + end + sync init + update \xer_so$24 1'0 + sync posedge \clk + update \xer_so$24 \xer_so$24$next + end + process $group_124 + assign \divisor_neg$25$next \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$25$next \divisor_neg$124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$25$next \divisor_neg$124 + end + sync init + update \divisor_neg$25 1'0 + sync posedge \clk + update \divisor_neg$25 \divisor_neg$25$next + end + process $group_125 + assign \dividend_neg$26$next \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$26$next \dividend_neg$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$26$next \dividend_neg$125 + end + sync init + update \dividend_neg$26 1'0 + sync posedge \clk + update \dividend_neg$26 \dividend_neg$26$next + end + process $group_126 + assign \divisor_radicand$27$next \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$27$next \divisor_radicand$126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$27$next \divisor_radicand$126 + end + sync init + update \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \divisor_radicand$27 \divisor_radicand$27$next + end + process $group_127 + assign \operation$28$next \operation$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$28$next \operation$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$28$next \operation$127 + end + sync init + update \operation$28 2'00 + sync posedge \clk + update \operation$28 \operation$28$next + end + process $group_128 + assign \quotient_root$29$next \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$29$next \quotient_root$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$29$next \quotient_root$128 + end + sync init + update \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \quotient_root$29 \quotient_root$29$next + end + process $group_129 + assign \root_times_radicand$30$next \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$30$next \root_times_radicand$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$30$next \root_times_radicand$129 + end + sync init + update \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \root_times_radicand$30 \root_times_radicand$30$next + end + process $group_130 + assign \compare_lhs$31$next \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$31$next \compare_lhs$130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$31$next \compare_lhs$130 + end + sync init + update \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_lhs$31 \compare_lhs$31$next + end + process $group_131 + assign \compare_rhs$32$next \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$32$next \compare_rhs$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$32$next \compare_rhs$131 + end + sync init + update \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_rhs$32 \compare_rhs$32$next + end + process $group_132 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_133 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.p" +module \p$263 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.n" +module \n$264 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_20.core.trial0" +module \trial0$266 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'000 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000000 + connect \B 7'1000010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 207 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 207 + connect \A \rr_times_trial_bits + connect \B 2'10 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 208 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 207 + parameter \Y_WIDTH 208 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 73 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 73 + connect \A \dr_times_trial_bits_sqrd + connect \B 2'10 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 208 + parameter \B_SIGNED 0 + parameter \B_WIDTH 73 + parameter \Y_WIDTH 209 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'000 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'000 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_20.core.trial1" +module \trial1$267 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'001 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000001 + connect \B 7'1000010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 207 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 207 + connect \A \rr_times_trial_bits + connect \B 2'10 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 208 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 207 + parameter \Y_WIDTH 208 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 73 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 73 + connect \A \dr_times_trial_bits_sqrd + connect \B 2'10 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 208 + parameter \B_SIGNED 0 + parameter \B_WIDTH 73 + parameter \Y_WIDTH 209 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'001 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'001 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_20.core.trial2" +module \trial2$268 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'000100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'010 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'000100 + connect \B 7'1000010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 207 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 207 + connect \A \rr_times_trial_bits + connect \B 2'10 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 208 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 207 + parameter \Y_WIDTH 208 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 73 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 73 + connect \A \dr_times_trial_bits_sqrd + connect \B 2'10 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 208 + parameter \B_SIGNED 0 + parameter \B_WIDTH 73 + parameter \Y_WIDTH 209 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'010 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'010 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_20.core.trial3" +module \trial3$269 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'001001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'011 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'001001 + connect \B 7'1000010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 207 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 207 + connect \A \rr_times_trial_bits + connect \B 2'10 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 208 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 207 + parameter \Y_WIDTH 208 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 73 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 73 + connect \A \dr_times_trial_bits_sqrd + connect \B 2'10 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 208 + parameter \B_SIGNED 0 + parameter \B_WIDTH 73 + parameter \Y_WIDTH 209 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'011 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'011 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_20.core.trial4" +module \trial4$270 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'010000 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'100 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'010000 + connect \B 7'1000010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 207 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 207 + connect \A \rr_times_trial_bits + connect \B 2'10 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 208 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 207 + parameter \Y_WIDTH 208 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 73 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 73 + connect \A \dr_times_trial_bits_sqrd + connect \B 2'10 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 208 + parameter \B_SIGNED 0 + parameter \B_WIDTH 73 + parameter \Y_WIDTH 209 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'100 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'100 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_20.core.trial5" +module \trial5$271 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'011001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'101 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'011001 + connect \B 7'1000010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 207 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 207 + connect \A \rr_times_trial_bits + connect \B 2'10 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 208 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 207 + parameter \Y_WIDTH 208 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 73 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 73 + connect \A \dr_times_trial_bits_sqrd + connect \B 2'10 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 208 + parameter \B_SIGNED 0 + parameter \B_WIDTH 73 + parameter \Y_WIDTH 209 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'101 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'101 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_20.core.trial6" +module \trial6$272 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'100100 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'110 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'100100 + connect \B 7'1000010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 207 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 207 + connect \A \rr_times_trial_bits + connect \B 2'10 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 208 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 207 + parameter \Y_WIDTH 208 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 73 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 73 + connect \A \dr_times_trial_bits_sqrd + connect \B 2'10 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 208 + parameter \B_SIGNED 0 + parameter \B_WIDTH 73 + parameter \Y_WIDTH 209 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'110 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'110 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_20.core.trial7" +module \trial7$273 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 70 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 70 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 70 + connect \A \divisor_radicand + connect \B 6'110001 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 70'0000000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 67 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 67 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B 3'111 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 67'0000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 194 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 194 + connect \A \dr_times_trial_bits + connect \B 7'1000001 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 195 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 194 + parameter \Y_WIDTH 195 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 136 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 263 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 136 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 263 + connect \A \qr_times_trial_bits + connect \B 7'1000010 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 264 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 263 + parameter \Y_WIDTH 264 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 133 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 133 + connect \A 6'110001 + connect \B 7'1000010 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 265 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 264 + parameter \B_SIGNED 0 + parameter \B_WIDTH 133 + parameter \Y_WIDTH 265 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 204 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 207 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 204 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 207 + connect \A \rr_times_trial_bits + connect \B 2'10 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 208 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 207 + parameter \Y_WIDTH 208 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 73 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 70 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 73 + connect \A \dr_times_trial_bits_sqrd + connect \B 2'10 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 209 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 208 + parameter \B_SIGNED 0 + parameter \B_WIDTH 73 + parameter \Y_WIDTH 209 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 136 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 67 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \quotient_root + connect \B 3'111 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \Y_WIDTH 136 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 136'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 204 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 131 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 131 + connect \A \root_times_radicand + connect \B 3'111 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 131 + parameter \Y_WIDTH 204 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 204'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_20.core.pe" +module \pe$274 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 output 2 \o + process $group_0 + assign \o 3'000 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'111 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'110 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'101 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'100 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'011 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'010 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'001 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 3'000 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_20.core" +module \core$265 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$266 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$267 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial2_trial_compare_rhs + cell \trial2$268 \trial2 + connect \divisor_radicand \trial2_divisor_radicand + connect \quotient_root \trial2_quotient_root + connect \root_times_radicand \trial2_root_times_radicand + connect \compare_rhs \trial2_compare_rhs + connect \operation \trial2_operation + connect \trial_compare_rhs \trial2_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial3_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial3_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial3_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial3_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial3_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial3_trial_compare_rhs + cell \trial3$269 \trial3 + connect \divisor_radicand \trial3_divisor_radicand + connect \quotient_root \trial3_quotient_root + connect \root_times_radicand \trial3_root_times_radicand + connect \compare_rhs \trial3_compare_rhs + connect \operation \trial3_operation + connect \trial_compare_rhs \trial3_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial4_trial_compare_rhs + cell \trial4$270 \trial4 + connect \divisor_radicand \trial4_divisor_radicand + connect \quotient_root \trial4_quotient_root + connect \root_times_radicand \trial4_root_times_radicand + connect \compare_rhs \trial4_compare_rhs + connect \operation \trial4_operation + connect \trial_compare_rhs \trial4_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial5_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial5_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial5_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial5_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial5_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial5_trial_compare_rhs + cell \trial5$271 \trial5 + connect \divisor_radicand \trial5_divisor_radicand + connect \quotient_root \trial5_quotient_root + connect \root_times_radicand \trial5_root_times_radicand + connect \compare_rhs \trial5_compare_rhs + connect \operation \trial5_operation + connect \trial_compare_rhs \trial5_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial6_trial_compare_rhs + cell \trial6$272 \trial6 + connect \divisor_radicand \trial6_divisor_radicand + connect \quotient_root \trial6_quotient_root + connect \root_times_radicand \trial6_root_times_radicand + connect \compare_rhs \trial6_compare_rhs + connect \operation \trial6_operation + connect \trial_compare_rhs \trial6_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial7_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial7_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial7_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial7_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial7_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial7_trial_compare_rhs + cell \trial7$273 \trial7 + connect \divisor_radicand \trial7_divisor_radicand + connect \quotient_root \trial7_quotient_root + connect \root_times_radicand \trial7_root_times_radicand + connect \compare_rhs \trial7_compare_rhs + connect \operation \trial7_operation + connect \trial_compare_rhs \trial7_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 8 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 3 \pe_o + cell \pe$274 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + process $group_15 + assign \trial2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_divisor_radicand \divisor_radicand + sync init + end + process $group_16 + assign \trial2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_quotient_root \quotient_root + sync init + end + process $group_17 + assign \trial2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_root_times_radicand \root_times_radicand + sync init + end + process $group_18 + assign \trial2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial2_compare_rhs \compare_rhs + sync init + end + process $group_19 + assign \trial2_operation 2'00 + assign \trial2_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial2_trial_compare_rhs + connect \Y $11 + end + process $group_20 + assign \pass_flag_2 1'0 + assign \pass_flag_2 $11 + sync init + end + process $group_21 + assign \trial3_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_divisor_radicand \divisor_radicand + sync init + end + process $group_22 + assign \trial3_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_quotient_root \quotient_root + sync init + end + process $group_23 + assign \trial3_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_root_times_radicand \root_times_radicand + sync init + end + process $group_24 + assign \trial3_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial3_compare_rhs \compare_rhs + sync init + end + process $group_25 + assign \trial3_operation 2'00 + assign \trial3_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial3_trial_compare_rhs + connect \Y $13 + end + process $group_26 + assign \pass_flag_3 1'0 + assign \pass_flag_3 $13 + sync init + end + process $group_27 + assign \trial4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_divisor_radicand \divisor_radicand + sync init + end + process $group_28 + assign \trial4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_quotient_root \quotient_root + sync init + end + process $group_29 + assign \trial4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \trial4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial4_compare_rhs \compare_rhs + sync init + end + process $group_31 + assign \trial4_operation 2'00 + assign \trial4_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial4_trial_compare_rhs + connect \Y $15 + end + process $group_32 + assign \pass_flag_4 1'0 + assign \pass_flag_4 $15 + sync init + end + process $group_33 + assign \trial5_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_divisor_radicand \divisor_radicand + sync init + end + process $group_34 + assign \trial5_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_quotient_root \quotient_root + sync init + end + process $group_35 + assign \trial5_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_root_times_radicand \root_times_radicand + sync init + end + process $group_36 + assign \trial5_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial5_compare_rhs \compare_rhs + sync init + end + process $group_37 + assign \trial5_operation 2'00 + assign \trial5_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial5_trial_compare_rhs + connect \Y $17 + end + process $group_38 + assign \pass_flag_5 1'0 + assign \pass_flag_5 $17 + sync init + end + process $group_39 + assign \trial6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_divisor_radicand \divisor_radicand + sync init + end + process $group_40 + assign \trial6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_quotient_root \quotient_root + sync init + end + process $group_41 + assign \trial6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_root_times_radicand \root_times_radicand + sync init + end + process $group_42 + assign \trial6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial6_compare_rhs \compare_rhs + sync init + end + process $group_43 + assign \trial6_operation 2'00 + assign \trial6_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial6_trial_compare_rhs + connect \Y $19 + end + process $group_44 + assign \pass_flag_6 1'0 + assign \pass_flag_6 $19 + sync init + end + process $group_45 + assign \trial7_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_divisor_radicand \divisor_radicand + sync init + end + process $group_46 + assign \trial7_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_quotient_root \quotient_root + sync init + end + process $group_47 + assign \trial7_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_root_times_radicand \root_times_radicand + sync init + end + process $group_48 + assign \trial7_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial7_compare_rhs \compare_rhs + sync init + end + process $group_49 + assign \trial7_operation 2'00 + assign \trial7_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial7_trial_compare_rhs + connect \Y $21 + end + process $group_50 + assign \pass_flag_7 1'0 + assign \pass_flag_7 $21 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 8 \pass_flags + process $group_51 + assign \pass_flags 8'00000000 + assign \pass_flags { \pass_flag_7 \pass_flag_6 \pass_flag_5 \pass_flag_4 \pass_flag_3 \pass_flag_2 \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 8 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \pass_flags + connect \Y $23 + end + process $group_52 + assign \pe_i 8'00000000 + assign \pe_i $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 3 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 4 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \pe_o + connect \B 1'1 + connect \Y $28 + end + connect $27 $28 + process $group_53 + assign \next_bits 3'000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $27 [2:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 3'111 + end + sync init + end + process $group_54 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 3'000 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 3'001 + assign \compare_rhs$6 \trial1_trial_compare_rhs + case 3'010 + assign \compare_rhs$6 \trial2_trial_compare_rhs + case 3'011 + assign \compare_rhs$6 \trial3_trial_compare_rhs + case 3'100 + assign \compare_rhs$6 \trial4_trial_compare_rhs + case 3'101 + assign \compare_rhs$6 \trial5_trial_compare_rhs + case 3'110 + assign \compare_rhs$6 \trial6_trial_compare_rhs + case 3'--- + assign \compare_rhs$6 \trial7_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 4 $30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \next_bits + connect \B 1'1 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 64 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $30 + connect \Y $32 + end + process $group_55 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $32 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 67 $35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 67 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 68 $37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 67 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 68 + connect \A $35 + connect \B 1'1 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $39 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 68 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B $37 + connect \Y $39 + end + connect $34 $39 + process $group_56 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $34 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_20" +module \core_calculate_stage_20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$265 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_21.core.trial0" +module \trial0$276 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 66 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 66 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 66 + connect \A \divisor_radicand + connect \B 2'00 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 66'000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 193 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 192 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 193 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 132 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 259 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 132 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 259 + connect \A \qr_times_trial_bits + connect \B 7'1000001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 260 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 259 + parameter \Y_WIDTH 260 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 129 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 129 + connect \A 2'00 + connect \B 7'1000000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 260 + parameter \B_SIGNED 0 + parameter \B_WIDTH 129 + parameter \Y_WIDTH 261 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 201 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 198 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 199 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 198 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 199 + connect \A \rr_times_trial_bits + connect \B 1'1 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 200 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 199 + parameter \Y_WIDTH 200 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 67 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 66 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 67 + connect \A \dr_times_trial_bits_sqrd + connect \B 1'0 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 201 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 200 + parameter \B_SIGNED 0 + parameter \B_WIDTH 67 + parameter \Y_WIDTH 201 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 132 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 65 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \B 1'0 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 132 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 132'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 198 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 129 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B 1'0 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 198 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 198'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_21.core.trial1" +module \trial1$277 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 input 1 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 input 2 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 input 3 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 input 4 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 output 5 \trial_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:288" + wire width 66 \dr_times_trial_bits_sqrd + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + wire width 66 $1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:289" + cell $mul $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 66 + connect \A \divisor_radicand + connect \B 2'01 + connect \Y $1 + end + process $group_0 + assign \dr_times_trial_bits_sqrd 66'000000000000000000000000000000000000000000000000000000000000000000 + assign \dr_times_trial_bits_sqrd $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:294" + wire width 65 \dr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + wire width 65 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:295" + cell $mul $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B 1'1 + connect \Y $3 + end + process $group_1 + assign \dr_times_trial_bits 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \dr_times_trial_bits $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 193 $5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 192 $6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $sshl $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 192 + connect \A \dr_times_trial_bits + connect \B 7'1000000 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + wire width 193 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:301" + cell $add $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_rhs + connect \B $6 + connect \Y $8 + end + connect $5 $8 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $10 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:307" + wire width 132 \qr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 259 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $sshl $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 132 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 259 + connect \A \qr_times_trial_bits + connect \B 7'1000001 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + wire width 260 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:314" + cell $add $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 259 + parameter \Y_WIDTH 260 + connect \A \compare_rhs + connect \B $11 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 129 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $sshl $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 129 + connect \A 2'01 + connect \B 7'1000000 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + wire width 261 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:318" + cell $add $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 260 + parameter \B_SIGNED 0 + parameter \B_WIDTH 129 + parameter \Y_WIDTH 261 + connect \A $13 + connect \B $15 + connect \Y $17 + end + connect $10 $17 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 201 $19 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:324" + wire width 198 \rr_times_trial_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 199 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $sshl $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 198 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 199 + connect \A \rr_times_trial_bits + connect \B 1'1 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + wire width 200 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:330" + cell $add $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 199 + parameter \Y_WIDTH 200 + connect \A \compare_rhs + connect \B $20 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 67 $24 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $sshl $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 66 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 67 + connect \A \dr_times_trial_bits_sqrd + connect \B 1'0 + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + wire width 201 $26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:333" + cell $add $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 200 + parameter \B_SIGNED 0 + parameter \B_WIDTH 67 + parameter \Y_WIDTH 201 + connect \A $22 + connect \B $24 + connect \Y $26 + end + connect $19 $26 + process $group_2 + assign \trial_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + assign \trial_compare_rhs $5 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \trial_compare_rhs $10 [191:0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \trial_compare_rhs $19 [191:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 132 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + wire width 65 $29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $mul $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \B 1'1 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:308" + cell $pos $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 132 + connect \A $29 + connect \Y $28 + end + process $group_3 + assign \qr_times_trial_bits 132'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + assign \qr_times_trial_bits $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 198 $32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + wire width 129 $33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $mul $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B 1'1 + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:325" + cell $pos $35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 198 + connect \A $33 + connect \Y $32 + end + process $group_4 + assign \rr_times_trial_bits 198'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:291" + switch \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:293" + attribute \nmigen.decoding "DivPipeCoreOperation.UDivRem" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:306" + attribute \nmigen.decoding "DivPipeCoreOperation.SqrtRem" + case 2'00 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:323" + attribute \nmigen.decoding "DivPipeCoreOperation.RSqrtRem" + case 2'10 + assign \rr_times_trial_bits $32 + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_21.core.pe" +module \pe$278 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 input 0 \i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 output 2 \o + process $group_0 + assign \o 1'0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'1 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 1'0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_21.core" +module \core$275 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 0 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 1 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 2 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 3 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 4 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 5 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 6 \divisor_radicand$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 7 \operation$2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 8 \quotient_root$3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 9 \root_times_radicand$4 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 10 \compare_lhs$5 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 11 \compare_rhs$6 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial0_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial0_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial0_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial0_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial0_trial_compare_rhs + cell \trial0$276 \trial0 + connect \divisor_radicand \trial0_divisor_radicand + connect \quotient_root \trial0_quotient_root + connect \root_times_radicand \trial0_root_times_radicand + connect \compare_rhs \trial0_compare_rhs + connect \operation \trial0_operation + connect \trial_compare_rhs \trial0_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:266" + wire width 64 \trial1_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:267" + wire width 64 \trial1_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:268" + wire width 128 \trial1_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:269" + wire width 192 \trial1_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:271" + wire width 2 \trial1_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:270" + wire width 192 \trial1_trial_compare_rhs + cell \trial1$277 \trial1 + connect \divisor_radicand \trial1_divisor_radicand + connect \quotient_root \trial1_quotient_root + connect \root_times_radicand \trial1_root_times_radicand + connect \compare_rhs \trial1_compare_rhs + connect \operation \trial1_operation + connect \trial_compare_rhs \trial1_trial_compare_rhs + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire width 2 \pe_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire width 1 \pe_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire width 1 \pe_o + cell \pe$278 \pe + connect \i \pe_i + connect \n \pe_n + connect \o \pe_o + end + process $group_0 + assign \divisor_radicand$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$1 \divisor_radicand + sync init + end + process $group_1 + assign \operation$2 2'00 + assign \operation$2 \operation + sync init + end + process $group_2 + assign \compare_lhs$5 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$5 \compare_lhs + sync init + end + process $group_3 + assign \trial0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_divisor_radicand \divisor_radicand + sync init + end + process $group_4 + assign \trial0_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_quotient_root \quotient_root + sync init + end + process $group_5 + assign \trial0_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_root_times_radicand \root_times_radicand + sync init + end + process $group_6 + assign \trial0_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial0_compare_rhs \compare_rhs + sync init + end + process $group_7 + assign \trial0_operation 2'00 + assign \trial0_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial0_trial_compare_rhs + connect \Y $7 + end + process $group_8 + assign \pass_flag_0 1'0 + assign \pass_flag_0 $7 + sync init + end + process $group_9 + assign \trial1_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_divisor_radicand \divisor_radicand + sync init + end + process $group_10 + assign \trial1_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_quotient_root \quotient_root + sync init + end + process $group_11 + assign \trial1_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_root_times_radicand \root_times_radicand + sync init + end + process $group_12 + assign \trial1_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \trial1_compare_rhs \compare_rhs + sync init + end + process $group_13 + assign \trial1_operation 2'00 + assign \trial1_operation \operation + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:412" + wire width 1 \pass_flag_1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:413" + cell $ge $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 1 + connect \A \compare_lhs + connect \B \trial1_trial_compare_rhs + connect \Y $9 + end + process $group_14 + assign \pass_flag_1 1'0 + assign \pass_flag_1 $9 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:417" + wire width 2 \pass_flags + process $group_15 + assign \pass_flags 2'00 + assign \pass_flags { \pass_flag_1 \pass_flag_0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + wire width 2 $11 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:430" + cell $not $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \pass_flags + connect \Y $11 + end + process $group_16 + assign \pe_i 2'00 + assign \pe_i $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:429" + wire width 1 \next_bits + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pe_n + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 2 $15 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + wire width 2 $16 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:432" + cell $sub $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \pe_o + connect \B 1'1 + connect \Y $16 + end + connect $15 $16 + process $group_17 + assign \next_bits 1'0 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + switch { $13 } + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:431" + case 1'1 + assign \next_bits $15 [0] + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:433" + case + assign \next_bits 1'1 + end + sync init + end + process $group_18 + assign \compare_rhs$6 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:438" + switch \next_bits + case 1'0 + assign \compare_rhs$6 \trial0_trial_compare_rhs + case 1'- + assign \compare_rhs$6 \trial1_trial_compare_rhs + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 2 $18 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $sshl $19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \next_bits + connect \B 1'0 + connect \Y $18 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + wire width 64 $20 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:441" + cell $or $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 64 + connect \A \quotient_root + connect \B $18 + connect \Y $20 + end + process $group_19 + assign \quotient_root$3 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$3 $20 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $22 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + wire width 65 $23 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:442" + cell $mul $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \divisor_radicand + connect \B \next_bits + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 66 $25 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $sshl $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 66 + connect \A $23 + connect \B 1'0 + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + wire width 129 $27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:443" + cell $add $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 129 + connect \A \root_times_radicand + connect \B $25 + connect \Y $27 + end + connect $22 $27 + process $group_20 + assign \root_times_radicand$4 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$4 $22 [127:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22.core_calculate_stage_21" +module \core_calculate_stage_21 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 58 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 59 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 60 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 61 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 62 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 63 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_divisor_radicand$33 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_operation$34 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root$35 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_root_times_radicand$36 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs$37 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs$38 + cell \core$275 \core + connect \divisor_radicand \core_divisor_radicand + connect \operation \core_operation + connect \quotient_root \core_quotient_root + connect \root_times_radicand \core_root_times_radicand + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \divisor_radicand$1 \core_divisor_radicand$33 + connect \operation$2 \core_operation$34 + connect \quotient_root$3 \core_quotient_root$35 + connect \root_times_radicand$4 \core_root_times_radicand$36 + connect \compare_lhs$5 \core_compare_lhs$37 + connect \compare_rhs$6 \core_compare_rhs$38 + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + process $group_26 + assign \core_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_operation 2'00 + assign \core_operation \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$27 \core_divisor_radicand$33 + sync init + end + process $group_33 + assign \operation$28 2'00 + assign \operation$28 \core_operation$34 + sync init + end + process $group_34 + assign \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$29 \core_quotient_root$35 + sync init + end + process $group_35 + assign \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$30 \core_root_times_radicand$36 + sync init + end + process $group_36 + assign \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$31 \core_compare_lhs$37 + sync init + end + process $group_37 + assign \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$32 \core_compare_rhs$38 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_20_to_22" +module \pipe_20_to_22 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 4 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 5 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 7 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 16 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 18 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 20 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 21 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 22 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 23 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 24 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 25 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 26 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 28 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 29 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 30 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 31 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 32 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 33 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 34 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 35 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 36 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 37 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 38 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$1$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 39 \op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 40 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 41 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 46 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 50 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 51 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 52 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 53 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 54 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 55 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 56 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 57 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 58 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 59 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 60 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 61 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 62 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 63 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$26$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 output 64 \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$27$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 output 65 \operation$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$28$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 output 66 \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$29$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 output 67 \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$30$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 output 68 \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$31$next + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 output 69 \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$32$next + cell \p$263 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$264 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_20_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_20_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_20_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_20_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_20_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_20_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_20_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_20_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_20_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_20_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_20_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_20_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_20_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_20_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_20_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_20_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_20_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_20_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_20_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_20_muxid$33 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_20_op__insn_type$34 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_20_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_20_op__imm_data__imm$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__imm_data__imm_ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__lk$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__rc__rc_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__oe__oe_ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__invert_a$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__zero_a$44 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_20_op__input_carry$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__invert_out$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_20_op__write_cr__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__write_cr__ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__output_carry$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__is_32bit$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_20_op__is_signed$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_20_op__data_len$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_20_op__insn$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_20_ra$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_20_rb$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_20_xer_so$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_20_divisor_neg$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_20_dividend_neg$58 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_20_divisor_radicand$59 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_20_operation$60 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_20_quotient_root$61 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_20_root_times_radicand$62 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_20_compare_lhs$63 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_20_compare_rhs$64 + cell \core_calculate_stage_20 \core_calculate_stage_20 + connect \muxid \core_calculate_stage_20_muxid + connect \op__insn_type \core_calculate_stage_20_op__insn_type + connect \op__fn_unit \core_calculate_stage_20_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_20_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_20_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_20_op__lk + connect \op__rc__rc \core_calculate_stage_20_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_20_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_20_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_20_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_20_op__invert_a + connect \op__zero_a \core_calculate_stage_20_op__zero_a + connect \op__input_carry \core_calculate_stage_20_op__input_carry + connect \op__invert_out \core_calculate_stage_20_op__invert_out + connect \op__write_cr__data \core_calculate_stage_20_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_20_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_20_op__output_carry + connect \op__is_32bit \core_calculate_stage_20_op__is_32bit + connect \op__is_signed \core_calculate_stage_20_op__is_signed + connect \op__data_len \core_calculate_stage_20_op__data_len + connect \op__insn \core_calculate_stage_20_op__insn + connect \ra \core_calculate_stage_20_ra + connect \rb \core_calculate_stage_20_rb + connect \xer_so \core_calculate_stage_20_xer_so + connect \divisor_neg \core_calculate_stage_20_divisor_neg + connect \dividend_neg \core_calculate_stage_20_dividend_neg + connect \divisor_radicand \core_calculate_stage_20_divisor_radicand + connect \operation \core_calculate_stage_20_operation + connect \quotient_root \core_calculate_stage_20_quotient_root + connect \root_times_radicand \core_calculate_stage_20_root_times_radicand + connect \compare_lhs \core_calculate_stage_20_compare_lhs + connect \compare_rhs \core_calculate_stage_20_compare_rhs + connect \muxid$1 \core_calculate_stage_20_muxid$33 + connect \op__insn_type$2 \core_calculate_stage_20_op__insn_type$34 + connect \op__fn_unit$3 \core_calculate_stage_20_op__fn_unit$35 + connect \op__imm_data__imm$4 \core_calculate_stage_20_op__imm_data__imm$36 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_20_op__imm_data__imm_ok$37 + connect \op__lk$6 \core_calculate_stage_20_op__lk$38 + connect \op__rc__rc$7 \core_calculate_stage_20_op__rc__rc$39 + connect \op__rc__rc_ok$8 \core_calculate_stage_20_op__rc__rc_ok$40 + connect \op__oe__oe$9 \core_calculate_stage_20_op__oe__oe$41 + connect \op__oe__oe_ok$10 \core_calculate_stage_20_op__oe__oe_ok$42 + connect \op__invert_a$11 \core_calculate_stage_20_op__invert_a$43 + connect \op__zero_a$12 \core_calculate_stage_20_op__zero_a$44 + connect \op__input_carry$13 \core_calculate_stage_20_op__input_carry$45 + connect \op__invert_out$14 \core_calculate_stage_20_op__invert_out$46 + connect \op__write_cr__data$15 \core_calculate_stage_20_op__write_cr__data$47 + connect \op__write_cr__ok$16 \core_calculate_stage_20_op__write_cr__ok$48 + connect \op__output_carry$17 \core_calculate_stage_20_op__output_carry$49 + connect \op__is_32bit$18 \core_calculate_stage_20_op__is_32bit$50 + connect \op__is_signed$19 \core_calculate_stage_20_op__is_signed$51 + connect \op__data_len$20 \core_calculate_stage_20_op__data_len$52 + connect \op__insn$21 \core_calculate_stage_20_op__insn$53 + connect \ra$22 \core_calculate_stage_20_ra$54 + connect \rb$23 \core_calculate_stage_20_rb$55 + connect \xer_so$24 \core_calculate_stage_20_xer_so$56 + connect \divisor_neg$25 \core_calculate_stage_20_divisor_neg$57 + connect \dividend_neg$26 \core_calculate_stage_20_dividend_neg$58 + connect \divisor_radicand$27 \core_calculate_stage_20_divisor_radicand$59 + connect \operation$28 \core_calculate_stage_20_operation$60 + connect \quotient_root$29 \core_calculate_stage_20_quotient_root$61 + connect \root_times_radicand$30 \core_calculate_stage_20_root_times_radicand$62 + connect \compare_lhs$31 \core_calculate_stage_20_compare_lhs$63 + connect \compare_rhs$32 \core_calculate_stage_20_compare_rhs$64 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_21_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_21_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_21_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_21_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_21_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_21_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_21_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_21_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_21_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_21_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_21_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_21_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_21_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_21_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_21_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_21_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_21_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_21_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_21_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_calculate_stage_21_muxid$65 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_calculate_stage_21_op__insn_type$66 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_calculate_stage_21_op__fn_unit$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_calculate_stage_21_op__imm_data__imm$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__imm_data__imm_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__lk$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__rc__rc_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__oe__oe_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__invert_a$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__zero_a$76 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_calculate_stage_21_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_calculate_stage_21_op__write_cr__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__write_cr__ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__output_carry$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_calculate_stage_21_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_calculate_stage_21_op__data_len$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_calculate_stage_21_op__insn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_21_ra$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_calculate_stage_21_rb$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_calculate_stage_21_xer_so$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_calculate_stage_21_divisor_neg$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_calculate_stage_21_dividend_neg$90 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_calculate_stage_21_divisor_radicand$91 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_calculate_stage_21_operation$92 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_calculate_stage_21_quotient_root$93 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_calculate_stage_21_root_times_radicand$94 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_calculate_stage_21_compare_lhs$95 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_calculate_stage_21_compare_rhs$96 + cell \core_calculate_stage_21 \core_calculate_stage_21 + connect \muxid \core_calculate_stage_21_muxid + connect \op__insn_type \core_calculate_stage_21_op__insn_type + connect \op__fn_unit \core_calculate_stage_21_op__fn_unit + connect \op__imm_data__imm \core_calculate_stage_21_op__imm_data__imm + connect \op__imm_data__imm_ok \core_calculate_stage_21_op__imm_data__imm_ok + connect \op__lk \core_calculate_stage_21_op__lk + connect \op__rc__rc \core_calculate_stage_21_op__rc__rc + connect \op__rc__rc_ok \core_calculate_stage_21_op__rc__rc_ok + connect \op__oe__oe \core_calculate_stage_21_op__oe__oe + connect \op__oe__oe_ok \core_calculate_stage_21_op__oe__oe_ok + connect \op__invert_a \core_calculate_stage_21_op__invert_a + connect \op__zero_a \core_calculate_stage_21_op__zero_a + connect \op__input_carry \core_calculate_stage_21_op__input_carry + connect \op__invert_out \core_calculate_stage_21_op__invert_out + connect \op__write_cr__data \core_calculate_stage_21_op__write_cr__data + connect \op__write_cr__ok \core_calculate_stage_21_op__write_cr__ok + connect \op__output_carry \core_calculate_stage_21_op__output_carry + connect \op__is_32bit \core_calculate_stage_21_op__is_32bit + connect \op__is_signed \core_calculate_stage_21_op__is_signed + connect \op__data_len \core_calculate_stage_21_op__data_len + connect \op__insn \core_calculate_stage_21_op__insn + connect \ra \core_calculate_stage_21_ra + connect \rb \core_calculate_stage_21_rb + connect \xer_so \core_calculate_stage_21_xer_so + connect \divisor_neg \core_calculate_stage_21_divisor_neg + connect \dividend_neg \core_calculate_stage_21_dividend_neg + connect \divisor_radicand \core_calculate_stage_21_divisor_radicand + connect \operation \core_calculate_stage_21_operation + connect \quotient_root \core_calculate_stage_21_quotient_root + connect \root_times_radicand \core_calculate_stage_21_root_times_radicand + connect \compare_lhs \core_calculate_stage_21_compare_lhs + connect \compare_rhs \core_calculate_stage_21_compare_rhs + connect \muxid$1 \core_calculate_stage_21_muxid$65 + connect \op__insn_type$2 \core_calculate_stage_21_op__insn_type$66 + connect \op__fn_unit$3 \core_calculate_stage_21_op__fn_unit$67 + connect \op__imm_data__imm$4 \core_calculate_stage_21_op__imm_data__imm$68 + connect \op__imm_data__imm_ok$5 \core_calculate_stage_21_op__imm_data__imm_ok$69 + connect \op__lk$6 \core_calculate_stage_21_op__lk$70 + connect \op__rc__rc$7 \core_calculate_stage_21_op__rc__rc$71 + connect \op__rc__rc_ok$8 \core_calculate_stage_21_op__rc__rc_ok$72 + connect \op__oe__oe$9 \core_calculate_stage_21_op__oe__oe$73 + connect \op__oe__oe_ok$10 \core_calculate_stage_21_op__oe__oe_ok$74 + connect \op__invert_a$11 \core_calculate_stage_21_op__invert_a$75 + connect \op__zero_a$12 \core_calculate_stage_21_op__zero_a$76 + connect \op__input_carry$13 \core_calculate_stage_21_op__input_carry$77 + connect \op__invert_out$14 \core_calculate_stage_21_op__invert_out$78 + connect \op__write_cr__data$15 \core_calculate_stage_21_op__write_cr__data$79 + connect \op__write_cr__ok$16 \core_calculate_stage_21_op__write_cr__ok$80 + connect \op__output_carry$17 \core_calculate_stage_21_op__output_carry$81 + connect \op__is_32bit$18 \core_calculate_stage_21_op__is_32bit$82 + connect \op__is_signed$19 \core_calculate_stage_21_op__is_signed$83 + connect \op__data_len$20 \core_calculate_stage_21_op__data_len$84 + connect \op__insn$21 \core_calculate_stage_21_op__insn$85 + connect \ra$22 \core_calculate_stage_21_ra$86 + connect \rb$23 \core_calculate_stage_21_rb$87 + connect \xer_so$24 \core_calculate_stage_21_xer_so$88 + connect \divisor_neg$25 \core_calculate_stage_21_divisor_neg$89 + connect \dividend_neg$26 \core_calculate_stage_21_dividend_neg$90 + connect \divisor_radicand$27 \core_calculate_stage_21_divisor_radicand$91 + connect \operation$28 \core_calculate_stage_21_operation$92 + connect \quotient_root$29 \core_calculate_stage_21_quotient_root$93 + connect \root_times_radicand$30 \core_calculate_stage_21_root_times_radicand$94 + connect \compare_lhs$31 \core_calculate_stage_21_compare_lhs$95 + connect \compare_rhs$32 \core_calculate_stage_21_compare_rhs$96 + end + process $group_0 + assign \core_calculate_stage_20_muxid 2'00 + assign \core_calculate_stage_20_muxid \muxid + sync init + end + process $group_1 + assign \core_calculate_stage_20_op__insn_type 7'0000000 + assign \core_calculate_stage_20_op__fn_unit 10'0000000000 + assign \core_calculate_stage_20_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_20_op__lk 1'0 + assign \core_calculate_stage_20_op__rc__rc 1'0 + assign \core_calculate_stage_20_op__rc__rc_ok 1'0 + assign \core_calculate_stage_20_op__oe__oe 1'0 + assign \core_calculate_stage_20_op__oe__oe_ok 1'0 + assign \core_calculate_stage_20_op__invert_a 1'0 + assign \core_calculate_stage_20_op__zero_a 1'0 + assign \core_calculate_stage_20_op__input_carry 2'00 + assign \core_calculate_stage_20_op__invert_out 1'0 + assign \core_calculate_stage_20_op__write_cr__data 3'000 + assign \core_calculate_stage_20_op__write_cr__ok 1'0 + assign \core_calculate_stage_20_op__output_carry 1'0 + assign \core_calculate_stage_20_op__is_32bit 1'0 + assign \core_calculate_stage_20_op__is_signed 1'0 + assign \core_calculate_stage_20_op__data_len 4'0000 + assign \core_calculate_stage_20_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_20_op__insn \core_calculate_stage_20_op__data_len \core_calculate_stage_20_op__is_signed \core_calculate_stage_20_op__is_32bit \core_calculate_stage_20_op__output_carry { \core_calculate_stage_20_op__write_cr__ok \core_calculate_stage_20_op__write_cr__data } \core_calculate_stage_20_op__invert_out \core_calculate_stage_20_op__input_carry \core_calculate_stage_20_op__zero_a \core_calculate_stage_20_op__invert_a { \core_calculate_stage_20_op__oe__oe_ok \core_calculate_stage_20_op__oe__oe } { \core_calculate_stage_20_op__rc__rc_ok \core_calculate_stage_20_op__rc__rc } \core_calculate_stage_20_op__lk { \core_calculate_stage_20_op__imm_data__imm_ok \core_calculate_stage_20_op__imm_data__imm } \core_calculate_stage_20_op__fn_unit \core_calculate_stage_20_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \core_calculate_stage_20_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_ra \ra + sync init + end + process $group_22 + assign \core_calculate_stage_20_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_rb \rb + sync init + end + process $group_23 + assign \core_calculate_stage_20_xer_so 1'0 + assign \core_calculate_stage_20_xer_so \xer_so + sync init + end + process $group_24 + assign \core_calculate_stage_20_divisor_neg 1'0 + assign \core_calculate_stage_20_divisor_neg \divisor_neg + sync init + end + process $group_25 + assign \core_calculate_stage_20_dividend_neg 1'0 + assign \core_calculate_stage_20_dividend_neg \dividend_neg + sync init + end + process $group_26 + assign \core_calculate_stage_20_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_calculate_stage_20_operation 2'00 + assign \core_calculate_stage_20_operation \operation + sync init + end + process $group_28 + assign \core_calculate_stage_20_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_calculate_stage_20_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_calculate_stage_20_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_calculate_stage_20_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_20_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \core_calculate_stage_21_muxid 2'00 + assign \core_calculate_stage_21_muxid \core_calculate_stage_20_muxid$33 + sync init + end + process $group_33 + assign \core_calculate_stage_21_op__insn_type 7'0000000 + assign \core_calculate_stage_21_op__fn_unit 10'0000000000 + assign \core_calculate_stage_21_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_op__imm_data__imm_ok 1'0 + assign \core_calculate_stage_21_op__lk 1'0 + assign \core_calculate_stage_21_op__rc__rc 1'0 + assign \core_calculate_stage_21_op__rc__rc_ok 1'0 + assign \core_calculate_stage_21_op__oe__oe 1'0 + assign \core_calculate_stage_21_op__oe__oe_ok 1'0 + assign \core_calculate_stage_21_op__invert_a 1'0 + assign \core_calculate_stage_21_op__zero_a 1'0 + assign \core_calculate_stage_21_op__input_carry 2'00 + assign \core_calculate_stage_21_op__invert_out 1'0 + assign \core_calculate_stage_21_op__write_cr__data 3'000 + assign \core_calculate_stage_21_op__write_cr__ok 1'0 + assign \core_calculate_stage_21_op__output_carry 1'0 + assign \core_calculate_stage_21_op__is_32bit 1'0 + assign \core_calculate_stage_21_op__is_signed 1'0 + assign \core_calculate_stage_21_op__data_len 4'0000 + assign \core_calculate_stage_21_op__insn 32'00000000000000000000000000000000 + assign { \core_calculate_stage_21_op__insn \core_calculate_stage_21_op__data_len \core_calculate_stage_21_op__is_signed \core_calculate_stage_21_op__is_32bit \core_calculate_stage_21_op__output_carry { \core_calculate_stage_21_op__write_cr__ok \core_calculate_stage_21_op__write_cr__data } \core_calculate_stage_21_op__invert_out \core_calculate_stage_21_op__input_carry \core_calculate_stage_21_op__zero_a \core_calculate_stage_21_op__invert_a { \core_calculate_stage_21_op__oe__oe_ok \core_calculate_stage_21_op__oe__oe } { \core_calculate_stage_21_op__rc__rc_ok \core_calculate_stage_21_op__rc__rc } \core_calculate_stage_21_op__lk { \core_calculate_stage_21_op__imm_data__imm_ok \core_calculate_stage_21_op__imm_data__imm } \core_calculate_stage_21_op__fn_unit \core_calculate_stage_21_op__insn_type } { \core_calculate_stage_20_op__insn$53 \core_calculate_stage_20_op__data_len$52 \core_calculate_stage_20_op__is_signed$51 \core_calculate_stage_20_op__is_32bit$50 \core_calculate_stage_20_op__output_carry$49 { \core_calculate_stage_20_op__write_cr__ok$48 \core_calculate_stage_20_op__write_cr__data$47 } \core_calculate_stage_20_op__invert_out$46 \core_calculate_stage_20_op__input_carry$45 \core_calculate_stage_20_op__zero_a$44 \core_calculate_stage_20_op__invert_a$43 { \core_calculate_stage_20_op__oe__oe_ok$42 \core_calculate_stage_20_op__oe__oe$41 } { \core_calculate_stage_20_op__rc__rc_ok$40 \core_calculate_stage_20_op__rc__rc$39 } \core_calculate_stage_20_op__lk$38 { \core_calculate_stage_20_op__imm_data__imm_ok$37 \core_calculate_stage_20_op__imm_data__imm$36 } \core_calculate_stage_20_op__fn_unit$35 \core_calculate_stage_20_op__insn_type$34 } + sync init + end + process $group_53 + assign \core_calculate_stage_21_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_ra \core_calculate_stage_20_ra$54 + sync init + end + process $group_54 + assign \core_calculate_stage_21_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_rb \core_calculate_stage_20_rb$55 + sync init + end + process $group_55 + assign \core_calculate_stage_21_xer_so 1'0 + assign \core_calculate_stage_21_xer_so \core_calculate_stage_20_xer_so$56 + sync init + end + process $group_56 + assign \core_calculate_stage_21_divisor_neg 1'0 + assign \core_calculate_stage_21_divisor_neg \core_calculate_stage_20_divisor_neg$57 + sync init + end + process $group_57 + assign \core_calculate_stage_21_dividend_neg 1'0 + assign \core_calculate_stage_21_dividend_neg \core_calculate_stage_20_dividend_neg$58 + sync init + end + process $group_58 + assign \core_calculate_stage_21_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_divisor_radicand \core_calculate_stage_20_divisor_radicand$59 + sync init + end + process $group_59 + assign \core_calculate_stage_21_operation 2'00 + assign \core_calculate_stage_21_operation \core_calculate_stage_20_operation$60 + sync init + end + process $group_60 + assign \core_calculate_stage_21_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_quotient_root \core_calculate_stage_20_quotient_root$61 + sync init + end + process $group_61 + assign \core_calculate_stage_21_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_root_times_radicand \core_calculate_stage_20_root_times_radicand$62 + sync init + end + process $group_62 + assign \core_calculate_stage_21_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_compare_lhs \core_calculate_stage_20_compare_lhs$63 + sync init + end + process $group_63 + assign \core_calculate_stage_21_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_calculate_stage_21_compare_rhs \core_calculate_stage_20_compare_rhs$64 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$97 + process $group_64 + assign \p_valid_i$97 1'0 + assign \p_valid_i$97 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_65 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $98 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$97 + connect \B \p_ready_o + connect \Y $98 + end + process $group_66 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $98 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$100 + process $group_67 + assign \muxid$100 2'00 + assign \muxid$100 \core_calculate_stage_21_muxid$65 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$101 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$111 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$120 + process $group_68 + assign \op__insn_type$101 7'0000000 + assign \op__fn_unit$102 10'0000000000 + assign \op__imm_data__imm$103 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$104 1'0 + assign \op__lk$105 1'0 + assign \op__rc__rc$106 1'0 + assign \op__rc__rc_ok$107 1'0 + assign \op__oe__oe$108 1'0 + assign \op__oe__oe_ok$109 1'0 + assign \op__invert_a$110 1'0 + assign \op__zero_a$111 1'0 + assign \op__input_carry$112 2'00 + assign \op__invert_out$113 1'0 + assign \op__write_cr__data$114 3'000 + assign \op__write_cr__ok$115 1'0 + assign \op__output_carry$116 1'0 + assign \op__is_32bit$117 1'0 + assign \op__is_signed$118 1'0 + assign \op__data_len$119 4'0000 + assign \op__insn$120 32'00000000000000000000000000000000 + assign { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } { \core_calculate_stage_21_op__insn$85 \core_calculate_stage_21_op__data_len$84 \core_calculate_stage_21_op__is_signed$83 \core_calculate_stage_21_op__is_32bit$82 \core_calculate_stage_21_op__output_carry$81 { \core_calculate_stage_21_op__write_cr__ok$80 \core_calculate_stage_21_op__write_cr__data$79 } \core_calculate_stage_21_op__invert_out$78 \core_calculate_stage_21_op__input_carry$77 \core_calculate_stage_21_op__zero_a$76 \core_calculate_stage_21_op__invert_a$75 { \core_calculate_stage_21_op__oe__oe_ok$74 \core_calculate_stage_21_op__oe__oe$73 } { \core_calculate_stage_21_op__rc__rc_ok$72 \core_calculate_stage_21_op__rc__rc$71 } \core_calculate_stage_21_op__lk$70 { \core_calculate_stage_21_op__imm_data__imm_ok$69 \core_calculate_stage_21_op__imm_data__imm$68 } \core_calculate_stage_21_op__fn_unit$67 \core_calculate_stage_21_op__insn_type$66 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$121 + process $group_88 + assign \ra$121 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$121 \core_calculate_stage_21_ra$86 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$122 + process $group_89 + assign \rb$122 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$122 \core_calculate_stage_21_rb$87 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \xer_so$123 + process $group_90 + assign \xer_so$123 1'0 + assign \xer_so$123 \core_calculate_stage_21_xer_so$88 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \divisor_neg$124 + process $group_91 + assign \divisor_neg$124 1'0 + assign \divisor_neg$124 \core_calculate_stage_21_divisor_neg$89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \dividend_neg$125 + process $group_92 + assign \dividend_neg$125 1'0 + assign \dividend_neg$125 \core_calculate_stage_21_dividend_neg$90 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$126 + process $group_93 + assign \divisor_radicand$126 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$126 \core_calculate_stage_21_divisor_radicand$91 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$127 + process $group_94 + assign \operation$127 2'00 + assign \operation$127 \core_calculate_stage_21_operation$92 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \quotient_root$128 + process $group_95 + assign \quotient_root$128 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$128 \core_calculate_stage_21_quotient_root$93 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$129 + process $group_96 + assign \root_times_radicand$129 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$129 \core_calculate_stage_21_root_times_radicand$94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \compare_lhs$130 + process $group_97 + assign \compare_lhs$130 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_lhs$130 \core_calculate_stage_21_compare_lhs$95 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \compare_rhs$131 + process $group_98 + assign \compare_rhs$131 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \compare_rhs$131 \core_calculate_stage_21_compare_rhs$96 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_99 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_100 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$100 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$100 + end + sync init + update \muxid$1 2'00 + sync posedge \clk + update \muxid$1 \muxid$1$next + end + process $group_101 + assign \op__insn_type$2$next \op__insn_type$2 + assign \op__fn_unit$3$next \op__fn_unit$3 + assign \op__imm_data__imm$4$next \op__imm_data__imm$4 + assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5 + assign \op__lk$6$next \op__lk$6 + assign \op__rc__rc$7$next \op__rc__rc$7 + assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8 + assign \op__oe__oe$9$next \op__oe__oe$9 + assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10 + assign \op__invert_a$11$next \op__invert_a$11 + assign \op__zero_a$12$next \op__zero_a$12 + assign \op__input_carry$13$next \op__input_carry$13 + assign \op__invert_out$14$next \op__invert_out$14 + assign \op__write_cr__data$15$next \op__write_cr__data$15 + assign \op__write_cr__ok$16$next \op__write_cr__ok$16 + assign \op__output_carry$17$next \op__output_carry$17 + assign \op__is_32bit$18$next \op__is_32bit$18 + assign \op__is_signed$19$next \op__is_signed$19 + assign \op__data_len$20$next \op__data_len$20 + assign \op__insn$21$next \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5$next 1'0 + assign \op__rc__rc$7$next 1'0 + assign \op__rc__rc_ok$8$next 1'0 + assign \op__oe__oe$9$next 1'0 + assign \op__oe__oe_ok$10$next 1'0 + assign \op__write_cr__data$15$next 3'000 + assign \op__write_cr__ok$16$next 1'0 + assign \op__insn$21$next 32'00000000000000000000000000000000 + end + sync init + update \op__insn_type$2 7'0000000 + update \op__fn_unit$3 10'0000000000 + update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \op__imm_data__imm_ok$5 1'0 + update \op__lk$6 1'0 + update \op__rc__rc$7 1'0 + update \op__rc__rc_ok$8 1'0 + update \op__oe__oe$9 1'0 + update \op__oe__oe_ok$10 1'0 + update \op__invert_a$11 1'0 + update \op__zero_a$12 1'0 + update \op__input_carry$13 2'00 + update \op__invert_out$14 1'0 + update \op__write_cr__data$15 3'000 + update \op__write_cr__ok$16 1'0 + update \op__output_carry$17 1'0 + update \op__is_32bit$18 1'0 + update \op__is_signed$19 1'0 + update \op__data_len$20 4'0000 + update \op__insn$21 32'00000000000000000000000000000000 + sync posedge \clk + update \op__insn_type$2 \op__insn_type$2$next + update \op__fn_unit$3 \op__fn_unit$3$next + update \op__imm_data__imm$4 \op__imm_data__imm$4$next + update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next + update \op__lk$6 \op__lk$6$next + update \op__rc__rc$7 \op__rc__rc$7$next + update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next + update \op__oe__oe$9 \op__oe__oe$9$next + update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next + update \op__invert_a$11 \op__invert_a$11$next + update \op__zero_a$12 \op__zero_a$12$next + update \op__input_carry$13 \op__input_carry$13$next + update \op__invert_out$14 \op__invert_out$14$next + update \op__write_cr__data$15 \op__write_cr__data$15$next + update \op__write_cr__ok$16 \op__write_cr__ok$16$next + update \op__output_carry$17 \op__output_carry$17$next + update \op__is_32bit$18 \op__is_32bit$18$next + update \op__is_signed$19 \op__is_signed$19$next + update \op__data_len$20 \op__data_len$20$next + update \op__insn$21 \op__insn$21$next + end + process $group_121 + assign \ra$22$next \ra$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \ra$22$next \ra$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \ra$22$next \ra$121 + end + sync init + update \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \ra$22 \ra$22$next + end + process $group_122 + assign \rb$23$next \rb$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \rb$23$next \rb$122 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \rb$23$next \rb$122 + end + sync init + update \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \rb$23 \rb$23$next + end + process $group_123 + assign \xer_so$24$next \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \xer_so$24$next \xer_so$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \xer_so$24$next \xer_so$123 + end + sync init + update \xer_so$24 1'0 + sync posedge \clk + update \xer_so$24 \xer_so$24$next + end + process $group_124 + assign \divisor_neg$25$next \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_neg$25$next \divisor_neg$124 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_neg$25$next \divisor_neg$124 + end + sync init + update \divisor_neg$25 1'0 + sync posedge \clk + update \divisor_neg$25 \divisor_neg$25$next + end + process $group_125 + assign \dividend_neg$26$next \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \dividend_neg$26$next \dividend_neg$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \dividend_neg$26$next \dividend_neg$125 + end + sync init + update \dividend_neg$26 1'0 + sync posedge \clk + update \dividend_neg$26 \dividend_neg$26$next + end + process $group_126 + assign \divisor_radicand$27$next \divisor_radicand$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \divisor_radicand$27$next \divisor_radicand$126 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \divisor_radicand$27$next \divisor_radicand$126 + end + sync init + update \divisor_radicand$27 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \divisor_radicand$27 \divisor_radicand$27$next + end + process $group_127 + assign \operation$28$next \operation$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \operation$28$next \operation$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \operation$28$next \operation$127 + end + sync init + update \operation$28 2'00 + sync posedge \clk + update \operation$28 \operation$28$next + end + process $group_128 + assign \quotient_root$29$next \quotient_root$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \quotient_root$29$next \quotient_root$128 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \quotient_root$29$next \quotient_root$128 + end + sync init + update \quotient_root$29 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \quotient_root$29 \quotient_root$29$next + end + process $group_129 + assign \root_times_radicand$30$next \root_times_radicand$30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \root_times_radicand$30$next \root_times_radicand$129 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \root_times_radicand$30$next \root_times_radicand$129 + end + sync init + update \root_times_radicand$30 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \root_times_radicand$30 \root_times_radicand$30$next + end + process $group_130 + assign \compare_lhs$31$next \compare_lhs$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_lhs$31$next \compare_lhs$130 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_lhs$31$next \compare_lhs$130 + end + sync init + update \compare_lhs$31 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_lhs$31 \compare_lhs$31$next + end + process $group_131 + assign \compare_rhs$32$next \compare_rhs$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \compare_rhs$32$next \compare_rhs$131 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \compare_rhs$32$next \compare_rhs$131 + end + sync init + update \compare_rhs$32 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \compare_rhs$32 \compare_rhs$32$next + end + process $group_132 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_133 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_end.p" +module \p$279 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_end.n" +module \n$280 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_end.core_final_stage.core" +module \core$281 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 0 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 1 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 2 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:191" + wire width 64 output 3 \quotient_root$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:192" + wire width 192 output 4 \remainder + process $group_0 + assign \quotient_root$1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$1 \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:482" + wire width 193 $2 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:482" + wire width 193 $3 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:482" + cell $sub $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \B_SIGNED 0 + parameter \B_WIDTH 192 + parameter \Y_WIDTH 193 + connect \A \compare_lhs + connect \B \compare_rhs + connect \Y $3 + end + connect $2 $3 + process $group_1 + assign \remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \remainder $2 [191:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_end.core_final_stage" +module \core_final_stage + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 24 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 25 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 26 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 27 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 28 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 29 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 30 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 31 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 32 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 33 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 34 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 35 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 44 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 46 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 50 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 51 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 52 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 53 \ra$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 output 54 \rb$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 output 55 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 output 56 \divisor_neg$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 output 57 \dividend_neg$26 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:191" + wire width 64 output 58 \quotient_root$27 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:192" + wire width 192 output 59 \remainder + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:191" + wire width 64 \core_quotient_root$28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:192" + wire width 192 \core_remainder + cell \core$281 \core + connect \quotient_root \core_quotient_root + connect \compare_lhs \core_compare_lhs + connect \compare_rhs \core_compare_rhs + connect \quotient_root$1 \core_quotient_root$28 + connect \remainder \core_remainder + end + process $group_0 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_1 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$22 \ra + sync init + end + process $group_22 + assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$23 \rb + sync init + end + process $group_23 + assign \xer_so$24 1'0 + assign \xer_so$24 \xer_so + sync init + end + process $group_24 + assign \divisor_neg$25 1'0 + assign \divisor_neg$25 \divisor_neg + sync init + end + process $group_25 + assign \dividend_neg$26 1'0 + assign \dividend_neg$26 \dividend_neg + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \divisor_radicand$29 + process $group_26 + assign \divisor_radicand$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \divisor_radicand$29 \divisor_radicand + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \operation$30 + process $group_27 + assign \operation$30 2'00 + assign \operation$30 \operation + sync init + end + process $group_28 + assign \core_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_quotient_root \quotient_root + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \root_times_radicand$31 + process $group_29 + assign \root_times_radicand$31 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \root_times_radicand$31 \root_times_radicand + sync init + end + process $group_30 + assign \core_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \quotient_root$27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_root$27 \core_quotient_root$28 + sync init + end + process $group_33 + assign \remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \remainder \core_remainder + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_end.output_stage" +module \output_stage + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 22 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 23 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:191" + wire width 64 input 24 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:192" + wire width 192 input 25 \remainder + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 26 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 27 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 28 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 29 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 30 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 31 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 32 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 33 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 34 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 35 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 38 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 39 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 40 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 41 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 45 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 46 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 47 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 49 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:21" + wire width 1 \quotient_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:49" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:49" + cell $xor $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dividend_neg + connect \B \divisor_neg + connect \Y $23 + end + process $group_0 + assign \quotient_neg 1'0 + assign \quotient_neg $23 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:22" + wire width 1 \remainder_neg + process $group_1 + assign \remainder_neg 1'0 + assign \remainder_neg \dividend_neg + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:23" + wire width 64 \quotient_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:58" + wire width 65 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:58" + wire width 65 $26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:58" + cell $neg $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $26 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:191" + wire width 65 $28 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:191" + cell $pos $29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $28 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:58" + wire width 65 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:58" + cell $mux $31 + parameter \WIDTH 65 + connect \A $28 + connect \B $26 + connect \S \quotient_neg + connect \Y $30 + end + connect $25 $30 + process $group_2 + assign \quotient_64 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \quotient_64 $25 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" + wire width 64 \remainder_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:60" + wire width 65 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:60" + wire width 65 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:60" + cell $neg $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251" + wire width 65 $35 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251" + cell $pos $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $35 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:60" + wire width 65 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:60" + cell $mux $38 + parameter \WIDTH 65 + connect \A $35 + connect \B $33 + connect \S \remainder_neg + connect \Y $37 + end + connect $32 $37 + process $group_3 + assign \remainder_64 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \remainder_64 $32 [63:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + wire width 2 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:41" + wire width 1 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:36" + wire width 1 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $or $41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dive_abs_ov32 + connect \B \div_by_zero + connect \Y $40 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:71" + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:71" + cell $gt $43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \quotient_root + connect \B 32'10000000000000000000000000000000 + connect \Y $42 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:71" + wire width 1 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:71" + cell $or $45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $40 + connect \B $42 + connect \Y $44 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:71" + wire width 1 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:71" + cell $eq $47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \quotient_root + connect \B 32'10000000000000000000000000000000 + connect \Y $46 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + wire width 1 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + cell $not $49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_neg + connect \Y $48 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + wire width 1 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + cell $and $51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $46 + connect \B $48 + connect \Y $50 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + wire width 1 $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + cell $or $53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $44 + connect \B $50 + connect \Y $52 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + cell $pos $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A $52 + connect \Y $39 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 2 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 1 $56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $or $57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dive_abs_ov32 + connect \B \div_by_zero + connect \Y $56 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $pos $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A $56 + connect \Y $55 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + wire width 2 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:42" + wire width 1 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 1 $60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $or $61 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dive_abs_ov64 + connect \B \div_by_zero + connect \Y $60 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:71" + wire width 1 $62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:71" + cell $gt $63 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \quotient_root + connect \B 64'1000000000000000000000000000000000000000000000000000000000000000 + connect \Y $62 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:71" + wire width 1 $64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:71" + cell $or $65 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $60 + connect \B $62 + connect \Y $64 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:71" + wire width 1 $66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:71" + cell $eq $67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \quotient_root + connect \B 64'1000000000000000000000000000000000000000000000000000000000000000 + connect \Y $66 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + wire width 1 $68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + cell $not $69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_neg + connect \Y $68 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + wire width 1 $70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + cell $and $71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $66 + connect \B $68 + connect \Y $70 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + wire width 1 $72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + cell $or $73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $64 + connect \B $70 + connect \Y $72 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:72" + cell $pos $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A $72 + connect \Y $59 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 2 $75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + wire width 1 $76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $or $77 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dive_abs_ov64 + connect \B \div_by_zero + connect \Y $76 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $pos $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A $76 + connect \Y $75 + end + process $group_4 + assign \xer_ov 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" + switch { \op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:68" + switch { \op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:68" + case 1'1 + assign \xer_ov $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:73" + case + assign \xer_ov $55 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + case + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:68" + switch { \op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:68" + case 1'1 + assign \xer_ov $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:73" + case + assign \xer_ov $75 + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:91" + wire width 64 $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:91" + cell $pos $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_64 [31:0] + connect \Y $79 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:93" + wire width 64 $81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:93" + cell $pos $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_64 [31:0] + connect \Y $81 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" + wire width 64 $83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" + cell $pos $84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_64 [31:0] + connect \Y $83 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + wire width 64 $85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + cell $pos $86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_64 [31:0] + connect \Y $85 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" + wire width 64 $87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" + cell $pos $88 + parameter \A_SIGNED 1 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \remainder_64 [31:0] + connect \Y $87 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" + wire width 64 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" + cell $pos $90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \remainder_64 [31:0] + connect \Y $89 + end + process $group_5 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:86" + switch \op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:87" + attribute \nmigen.decoding "OP_DIVE/30" + case 7'0011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:88" + switch { \op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:88" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:89" + switch { \op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:89" + case 1'1 + assign \o $79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:92" + case + assign \o $81 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:94" + case + assign \o \quotient_64 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + attribute \nmigen.decoding "OP_DIV/29" + case 7'0011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + switch { \op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:98" + switch { \op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:98" + case 1'1 + assign \o $83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:101" + case + assign \o $85 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" + case + assign \o \quotient_64 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" + attribute \nmigen.decoding "OP_MOD/47" + case 7'0101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" + switch { \op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:107" + switch { \op__is_signed } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:107" + case 1'1 + assign \o $87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" + case + assign \o $89 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:112" + case + assign \o \remainder_64 + end + end + sync init + end + process $group_6 + assign \xer_so$22 1'0 + assign \xer_so$22 \xer_so + sync init + end + process $group_7 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_8 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + connect \dive_abs_ov32 1'0 + connect \div_by_zero 1'0 + connect \dive_abs_ov64 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_end.output" +module \output$282 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 3 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 4 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 12 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 14 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 19 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 20 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 input 21 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 input 22 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 4 input 23 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 input 24 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 input 25 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 input 26 \xer_so + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 27 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 28 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 29 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 30 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 31 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 32 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 33 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 34 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 35 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 36 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 37 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 38 \op__zero_a$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 39 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 40 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 41 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 46 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 47 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 48 \o$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 49 \o_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 4 output 50 \cr_a$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 51 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 52 \xer_ca$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 53 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 54 \xer_ov$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 55 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 56 \xer_so$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 57 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:19" + wire width 65 \o$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22" + wire width 65 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22" + wire width 64 $30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22" + cell $not $31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $30 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22" + cell $pos $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A $30 + connect \Y $29 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 65 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + cell $pos $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $33 + end + process $group_0 + assign \o$28 65'00000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:21" + switch { \op__invert_out } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:21" + case 1'1 + assign \o$28 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23" + case + assign \o$28 $33 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251" + wire width 64 $35 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251" + cell $pos $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \o$28 [31:0] + connect \Y $35 + end + process $group_1 + assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch { \op__is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + case 1'1 + assign \target $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" + case + assign \target \o$28 [63:0] + end + sync init + end + process $group_2 + assign \xer_ca$25 2'00 + assign \xer_ca$25 \xer_ca + sync init + end + process $group_3 + assign \xer_ca_ok 1'0 + assign \xer_ca_ok \op__output_carry + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:44" + wire width 1 \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53" + cell $eq $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \op__insn_type + connect \B 7'0001010 + connect \Y $37 + end + process $group_4 + assign \is_cmp 1'0 + assign \is_cmp $37 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:45" + wire width 1 \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54" + cell $eq $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \op__insn_type + connect \B 7'0001100 + connect \Y $39 + end + process $group_5 + assign \is_cmpeqb 1'0 + assign \is_cmpeqb $39 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:43" + wire width 1 \msb_test + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55" + cell $xor $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \target [63] + connect \B \is_cmp + connect \Y $41 + end + process $group_6 + assign \msb_test 1'0 + assign \msb_test $41 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + wire width 1 \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56" + cell $reduce_bool $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $43 + end + process $group_7 + assign \is_nzero 1'0 + assign \is_nzero $43 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 1 \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" + cell $not $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $45 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57" + cell $and $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B $45 + connect \Y $47 + end + process $group_8 + assign \is_positive 1'0 + assign \is_positive $47 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" + wire width 1 \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58" + cell $and $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \msb_test + connect \Y $49 + end + process $group_9 + assign \is_negative 1'0 + assign \is_negative $49 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:47" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:46" + wire width 1 \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63" + cell $not $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $51 + end + process $group_10 + assign \cr0 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60" + switch { \is_cmpeqb } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60" + case 1'1 + assign \cr0 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:62" + case + assign \cr0 { \is_negative \is_positive $51 \so } + end + sync init + end + process $group_11 + assign \o$22 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o$22 \o$28 [63:0] + sync init + end + process $group_12 + assign \o_ok$23 1'0 + assign \o_ok$23 \o_ok + sync init + end + process $group_13 + assign \cr_a$24 4'0000 + assign \cr_a$24 \cr0 + sync init + end + process $group_14 + assign \cr_a_ok 1'0 + assign \cr_a_ok \op__write_cr__ok + sync init + end + process $group_15 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_16 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 10'0000000000 + assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5 1'0 + assign \op__lk$6 1'0 + assign \op__rc__rc$7 1'0 + assign \op__rc__rc_ok$8 1'0 + assign \op__oe__oe$9 1'0 + assign \op__oe__oe_ok$10 1'0 + assign \op__invert_a$11 1'0 + assign \op__zero_a$12 1'0 + assign \op__input_carry$13 2'00 + assign \op__invert_out$14 1'0 + assign \op__write_cr__data$15 3'000 + assign \op__write_cr__ok$16 1'0 + assign \op__output_carry$17 1'0 + assign \op__is_32bit$18 1'0 + assign \op__is_signed$19 1'0 + assign \op__data_len$20 4'0000 + assign \op__insn$21 32'00000000000000000000000000000000 + assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:26" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:26" + cell $or $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $53 + end + process $group_36 + assign \so 1'0 + assign \so $53 + sync init + end + process $group_37 + assign \xer_so$27 1'0 + assign \xer_so$27 \so + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \op__oe__oe + connect \B \op__oe__oe_ok + connect \Y $55 + end + process $group_38 + assign \xer_so_ok 1'0 + assign \xer_so_ok $55 + sync init + end + process $group_39 + assign \xer_ov$26 2'00 + assign \xer_ov$26 \xer_ov + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32" + cell $and $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \op__oe__oe + connect \B \op__oe__oe_ok + connect \Y $57 + end + process $group_40 + assign \xer_ov_ok 1'0 + assign \xer_ov_ok $57 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu.pipe_end" +module \pipe_end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 4 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 5 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 7 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 13 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 15 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 16 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 18 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 20 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 21 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 22 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 23 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 24 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 25 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 26 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 input 28 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 input 29 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 input 30 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 input 31 \operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 input 32 \quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 input 33 \root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 input 34 \compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 input 35 \compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 36 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 37 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 38 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$1$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 39 \op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 40 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 output 41 \op__imm_data__imm$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 42 \op__imm_data__imm_ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 43 \op__lk$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 44 \op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 45 \op__rc__rc_ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 46 \op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 47 \op__oe__oe_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 48 \op__invert_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 49 \op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 50 \op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 51 \op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 output 52 \op__write_cr__data$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 53 \op__write_cr__ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 54 \op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 55 \op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 56 \op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 57 \op__data_len$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 output 58 \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 59 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 60 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 4 output 61 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 62 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 63 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 64 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 65 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 66 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 67 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_so$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 68 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_so_ok$next + cell \p$279 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$280 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_final_stage_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_final_stage_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_final_stage_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_final_stage_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_final_stage_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_final_stage_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_final_stage_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_final_stage_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_final_stage_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_final_stage_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_final_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_final_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_final_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \core_final_stage_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \core_final_stage_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \core_final_stage_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \core_final_stage_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \core_final_stage_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \core_final_stage_compare_rhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \core_final_stage_muxid$23 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \core_final_stage_op__insn_type$24 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \core_final_stage_op__fn_unit$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \core_final_stage_op__imm_data__imm$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__imm_data__imm_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__lk$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__rc__rc_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__oe__oe_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__invert_a$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__zero_a$34 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \core_final_stage_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \core_final_stage_op__write_cr__data$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__write_cr__ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__output_carry$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__is_32bit$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \core_final_stage_op__is_signed$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \core_final_stage_op__data_len$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \core_final_stage_op__insn$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_final_stage_ra$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \core_final_stage_rb$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \core_final_stage_xer_so$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \core_final_stage_divisor_neg$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \core_final_stage_dividend_neg$48 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:191" + wire width 64 \core_final_stage_quotient_root$49 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:192" + wire width 192 \core_final_stage_remainder + cell \core_final_stage \core_final_stage + connect \muxid \core_final_stage_muxid + connect \op__insn_type \core_final_stage_op__insn_type + connect \op__fn_unit \core_final_stage_op__fn_unit + connect \op__imm_data__imm \core_final_stage_op__imm_data__imm + connect \op__imm_data__imm_ok \core_final_stage_op__imm_data__imm_ok + connect \op__lk \core_final_stage_op__lk + connect \op__rc__rc \core_final_stage_op__rc__rc + connect \op__rc__rc_ok \core_final_stage_op__rc__rc_ok + connect \op__oe__oe \core_final_stage_op__oe__oe + connect \op__oe__oe_ok \core_final_stage_op__oe__oe_ok + connect \op__invert_a \core_final_stage_op__invert_a + connect \op__zero_a \core_final_stage_op__zero_a + connect \op__input_carry \core_final_stage_op__input_carry + connect \op__invert_out \core_final_stage_op__invert_out + connect \op__write_cr__data \core_final_stage_op__write_cr__data + connect \op__write_cr__ok \core_final_stage_op__write_cr__ok + connect \op__output_carry \core_final_stage_op__output_carry + connect \op__is_32bit \core_final_stage_op__is_32bit + connect \op__is_signed \core_final_stage_op__is_signed + connect \op__data_len \core_final_stage_op__data_len + connect \op__insn \core_final_stage_op__insn + connect \ra \core_final_stage_ra + connect \rb \core_final_stage_rb + connect \xer_so \core_final_stage_xer_so + connect \divisor_neg \core_final_stage_divisor_neg + connect \dividend_neg \core_final_stage_dividend_neg + connect \divisor_radicand \core_final_stage_divisor_radicand + connect \operation \core_final_stage_operation + connect \quotient_root \core_final_stage_quotient_root + connect \root_times_radicand \core_final_stage_root_times_radicand + connect \compare_lhs \core_final_stage_compare_lhs + connect \compare_rhs \core_final_stage_compare_rhs + connect \muxid$1 \core_final_stage_muxid$23 + connect \op__insn_type$2 \core_final_stage_op__insn_type$24 + connect \op__fn_unit$3 \core_final_stage_op__fn_unit$25 + connect \op__imm_data__imm$4 \core_final_stage_op__imm_data__imm$26 + connect \op__imm_data__imm_ok$5 \core_final_stage_op__imm_data__imm_ok$27 + connect \op__lk$6 \core_final_stage_op__lk$28 + connect \op__rc__rc$7 \core_final_stage_op__rc__rc$29 + connect \op__rc__rc_ok$8 \core_final_stage_op__rc__rc_ok$30 + connect \op__oe__oe$9 \core_final_stage_op__oe__oe$31 + connect \op__oe__oe_ok$10 \core_final_stage_op__oe__oe_ok$32 + connect \op__invert_a$11 \core_final_stage_op__invert_a$33 + connect \op__zero_a$12 \core_final_stage_op__zero_a$34 + connect \op__input_carry$13 \core_final_stage_op__input_carry$35 + connect \op__invert_out$14 \core_final_stage_op__invert_out$36 + connect \op__write_cr__data$15 \core_final_stage_op__write_cr__data$37 + connect \op__write_cr__ok$16 \core_final_stage_op__write_cr__ok$38 + connect \op__output_carry$17 \core_final_stage_op__output_carry$39 + connect \op__is_32bit$18 \core_final_stage_op__is_32bit$40 + connect \op__is_signed$19 \core_final_stage_op__is_signed$41 + connect \op__data_len$20 \core_final_stage_op__data_len$42 + connect \op__insn$21 \core_final_stage_op__insn$43 + connect \ra$22 \core_final_stage_ra$44 + connect \rb$23 \core_final_stage_rb$45 + connect \xer_so$24 \core_final_stage_xer_so$46 + connect \divisor_neg$25 \core_final_stage_divisor_neg$47 + connect \dividend_neg$26 \core_final_stage_dividend_neg$48 + connect \quotient_root$27 \core_final_stage_quotient_root$49 + connect \remainder \core_final_stage_remainder + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \output_stage_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \output_stage_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \output_stage_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \output_stage_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \output_stage_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \output_stage_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \output_stage_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \output_stage_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \output_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \output_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \output_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:191" + wire width 64 \output_stage_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:192" + wire width 192 \output_stage_remainder + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \output_stage_muxid$50 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \output_stage_op__insn_type$51 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \output_stage_op__fn_unit$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \output_stage_op__imm_data__imm$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__imm_data__imm_ok$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__lk$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__rc__rc_ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__oe__oe_ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__invert_a$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__zero_a$61 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \output_stage_op__input_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__invert_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \output_stage_op__write_cr__data$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__write_cr__ok$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__output_carry$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__is_32bit$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_stage_op__is_signed$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \output_stage_op__data_len$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \output_stage_op__insn$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \output_stage_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \output_stage_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \output_stage_xer_so$71 + cell \output_stage \output_stage + connect \muxid \output_stage_muxid + connect \op__insn_type \output_stage_op__insn_type + connect \op__fn_unit \output_stage_op__fn_unit + connect \op__imm_data__imm \output_stage_op__imm_data__imm + connect \op__imm_data__imm_ok \output_stage_op__imm_data__imm_ok + connect \op__lk \output_stage_op__lk + connect \op__rc__rc \output_stage_op__rc__rc + connect \op__rc__rc_ok \output_stage_op__rc__rc_ok + connect \op__oe__oe \output_stage_op__oe__oe + connect \op__oe__oe_ok \output_stage_op__oe__oe_ok + connect \op__invert_a \output_stage_op__invert_a + connect \op__zero_a \output_stage_op__zero_a + connect \op__input_carry \output_stage_op__input_carry + connect \op__invert_out \output_stage_op__invert_out + connect \op__write_cr__data \output_stage_op__write_cr__data + connect \op__write_cr__ok \output_stage_op__write_cr__ok + connect \op__output_carry \output_stage_op__output_carry + connect \op__is_32bit \output_stage_op__is_32bit + connect \op__is_signed \output_stage_op__is_signed + connect \op__data_len \output_stage_op__data_len + connect \op__insn \output_stage_op__insn + connect \xer_so \output_stage_xer_so + connect \divisor_neg \output_stage_divisor_neg + connect \dividend_neg \output_stage_dividend_neg + connect \quotient_root \output_stage_quotient_root + connect \remainder \output_stage_remainder + connect \muxid$1 \output_stage_muxid$50 + connect \op__insn_type$2 \output_stage_op__insn_type$51 + connect \op__fn_unit$3 \output_stage_op__fn_unit$52 + connect \op__imm_data__imm$4 \output_stage_op__imm_data__imm$53 + connect \op__imm_data__imm_ok$5 \output_stage_op__imm_data__imm_ok$54 + connect \op__lk$6 \output_stage_op__lk$55 + connect \op__rc__rc$7 \output_stage_op__rc__rc$56 + connect \op__rc__rc_ok$8 \output_stage_op__rc__rc_ok$57 + connect \op__oe__oe$9 \output_stage_op__oe__oe$58 + connect \op__oe__oe_ok$10 \output_stage_op__oe__oe_ok$59 + connect \op__invert_a$11 \output_stage_op__invert_a$60 + connect \op__zero_a$12 \output_stage_op__zero_a$61 + connect \op__input_carry$13 \output_stage_op__input_carry$62 + connect \op__invert_out$14 \output_stage_op__invert_out$63 + connect \op__write_cr__data$15 \output_stage_op__write_cr__data$64 + connect \op__write_cr__ok$16 \output_stage_op__write_cr__ok$65 + connect \op__output_carry$17 \output_stage_op__output_carry$66 + connect \op__is_32bit$18 \output_stage_op__is_32bit$67 + connect \op__is_signed$19 \output_stage_op__is_signed$68 + connect \op__data_len$20 \output_stage_op__data_len$69 + connect \op__insn$21 \output_stage_op__insn$70 + connect \o \output_stage_o + connect \xer_ov \output_stage_xer_ov + connect \xer_so$22 \output_stage_xer_so$71 + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \output_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \output_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \output_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \output_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \output_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \output_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \output_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \output_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \output_xer_so + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \output_muxid$72 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \output_op__insn_type$73 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \output_op__fn_unit$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \output_op__imm_data__imm$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__imm_data__imm_ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__lk$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__rc__rc$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__rc__rc_ok$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__oe__oe$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__oe__oe_ok$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__invert_a$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__zero_a$83 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \output_op__input_carry$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__invert_out$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \output_op__write_cr__data$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__write_cr__ok$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__output_carry$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__is_32bit$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \output_op__is_signed$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \output_op__data_len$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \output_op__insn$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \output_o$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \output_o_ok$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 4 \output_cr_a$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \output_xer_ca$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \output_xer_ov$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \output_xer_so$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \output_xer_so_ok + cell \output$282 \output + connect \muxid \output_muxid + connect \op__insn_type \output_op__insn_type + connect \op__fn_unit \output_op__fn_unit + connect \op__imm_data__imm \output_op__imm_data__imm + connect \op__imm_data__imm_ok \output_op__imm_data__imm_ok + connect \op__lk \output_op__lk + connect \op__rc__rc \output_op__rc__rc + connect \op__rc__rc_ok \output_op__rc__rc_ok + connect \op__oe__oe \output_op__oe__oe + connect \op__oe__oe_ok \output_op__oe__oe_ok + connect \op__invert_a \output_op__invert_a + connect \op__zero_a \output_op__zero_a + connect \op__input_carry \output_op__input_carry + connect \op__invert_out \output_op__invert_out + connect \op__write_cr__data \output_op__write_cr__data + connect \op__write_cr__ok \output_op__write_cr__ok + connect \op__output_carry \output_op__output_carry + connect \op__is_32bit \output_op__is_32bit + connect \op__is_signed \output_op__is_signed + connect \op__data_len \output_op__data_len + connect \op__insn \output_op__insn + connect \o \output_o + connect \o_ok \output_o_ok + connect \cr_a \output_cr_a + connect \xer_ca \output_xer_ca + connect \xer_ov \output_xer_ov + connect \xer_so \output_xer_so + connect \muxid$1 \output_muxid$72 + connect \op__insn_type$2 \output_op__insn_type$73 + connect \op__fn_unit$3 \output_op__fn_unit$74 + connect \op__imm_data__imm$4 \output_op__imm_data__imm$75 + connect \op__imm_data__imm_ok$5 \output_op__imm_data__imm_ok$76 + connect \op__lk$6 \output_op__lk$77 + connect \op__rc__rc$7 \output_op__rc__rc$78 + connect \op__rc__rc_ok$8 \output_op__rc__rc_ok$79 + connect \op__oe__oe$9 \output_op__oe__oe$80 + connect \op__oe__oe_ok$10 \output_op__oe__oe_ok$81 + connect \op__invert_a$11 \output_op__invert_a$82 + connect \op__zero_a$12 \output_op__zero_a$83 + connect \op__input_carry$13 \output_op__input_carry$84 + connect \op__invert_out$14 \output_op__invert_out$85 + connect \op__write_cr__data$15 \output_op__write_cr__data$86 + connect \op__write_cr__ok$16 \output_op__write_cr__ok$87 + connect \op__output_carry$17 \output_op__output_carry$88 + connect \op__is_32bit$18 \output_op__is_32bit$89 + connect \op__is_signed$19 \output_op__is_signed$90 + connect \op__data_len$20 \output_op__data_len$91 + connect \op__insn$21 \output_op__insn$92 + connect \o$22 \output_o$93 + connect \o_ok$23 \output_o_ok$94 + connect \cr_a$24 \output_cr_a$95 + connect \cr_a_ok \output_cr_a_ok + connect \xer_ca$25 \output_xer_ca$96 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_ov$26 \output_xer_ov$97 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so$27 \output_xer_so$98 + connect \xer_so_ok \output_xer_so_ok + end + process $group_0 + assign \core_final_stage_muxid 2'00 + assign \core_final_stage_muxid \muxid + sync init + end + process $group_1 + assign \core_final_stage_op__insn_type 7'0000000 + assign \core_final_stage_op__fn_unit 10'0000000000 + assign \core_final_stage_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_op__imm_data__imm_ok 1'0 + assign \core_final_stage_op__lk 1'0 + assign \core_final_stage_op__rc__rc 1'0 + assign \core_final_stage_op__rc__rc_ok 1'0 + assign \core_final_stage_op__oe__oe 1'0 + assign \core_final_stage_op__oe__oe_ok 1'0 + assign \core_final_stage_op__invert_a 1'0 + assign \core_final_stage_op__zero_a 1'0 + assign \core_final_stage_op__input_carry 2'00 + assign \core_final_stage_op__invert_out 1'0 + assign \core_final_stage_op__write_cr__data 3'000 + assign \core_final_stage_op__write_cr__ok 1'0 + assign \core_final_stage_op__output_carry 1'0 + assign \core_final_stage_op__is_32bit 1'0 + assign \core_final_stage_op__is_signed 1'0 + assign \core_final_stage_op__data_len 4'0000 + assign \core_final_stage_op__insn 32'00000000000000000000000000000000 + assign { \core_final_stage_op__insn \core_final_stage_op__data_len \core_final_stage_op__is_signed \core_final_stage_op__is_32bit \core_final_stage_op__output_carry { \core_final_stage_op__write_cr__ok \core_final_stage_op__write_cr__data } \core_final_stage_op__invert_out \core_final_stage_op__input_carry \core_final_stage_op__zero_a \core_final_stage_op__invert_a { \core_final_stage_op__oe__oe_ok \core_final_stage_op__oe__oe } { \core_final_stage_op__rc__rc_ok \core_final_stage_op__rc__rc } \core_final_stage_op__lk { \core_final_stage_op__imm_data__imm_ok \core_final_stage_op__imm_data__imm } \core_final_stage_op__fn_unit \core_final_stage_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_21 + assign \core_final_stage_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_ra \ra + sync init + end + process $group_22 + assign \core_final_stage_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_rb \rb + sync init + end + process $group_23 + assign \core_final_stage_xer_so 1'0 + assign \core_final_stage_xer_so \xer_so + sync init + end + process $group_24 + assign \core_final_stage_divisor_neg 1'0 + assign \core_final_stage_divisor_neg \divisor_neg + sync init + end + process $group_25 + assign \core_final_stage_dividend_neg 1'0 + assign \core_final_stage_dividend_neg \dividend_neg + sync init + end + process $group_26 + assign \core_final_stage_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_divisor_radicand \divisor_radicand + sync init + end + process $group_27 + assign \core_final_stage_operation 2'00 + assign \core_final_stage_operation \operation + sync init + end + process $group_28 + assign \core_final_stage_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_quotient_root \quotient_root + sync init + end + process $group_29 + assign \core_final_stage_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_root_times_radicand \root_times_radicand + sync init + end + process $group_30 + assign \core_final_stage_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_compare_lhs \compare_lhs + sync init + end + process $group_31 + assign \core_final_stage_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \core_final_stage_compare_rhs \compare_rhs + sync init + end + process $group_32 + assign \output_stage_muxid 2'00 + assign \output_stage_muxid \core_final_stage_muxid$23 + sync init + end + process $group_33 + assign \output_stage_op__insn_type 7'0000000 + assign \output_stage_op__fn_unit 10'0000000000 + assign \output_stage_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_stage_op__imm_data__imm_ok 1'0 + assign \output_stage_op__lk 1'0 + assign \output_stage_op__rc__rc 1'0 + assign \output_stage_op__rc__rc_ok 1'0 + assign \output_stage_op__oe__oe 1'0 + assign \output_stage_op__oe__oe_ok 1'0 + assign \output_stage_op__invert_a 1'0 + assign \output_stage_op__zero_a 1'0 + assign \output_stage_op__input_carry 2'00 + assign \output_stage_op__invert_out 1'0 + assign \output_stage_op__write_cr__data 3'000 + assign \output_stage_op__write_cr__ok 1'0 + assign \output_stage_op__output_carry 1'0 + assign \output_stage_op__is_32bit 1'0 + assign \output_stage_op__is_signed 1'0 + assign \output_stage_op__data_len 4'0000 + assign \output_stage_op__insn 32'00000000000000000000000000000000 + assign { \output_stage_op__insn \output_stage_op__data_len \output_stage_op__is_signed \output_stage_op__is_32bit \output_stage_op__output_carry { \output_stage_op__write_cr__ok \output_stage_op__write_cr__data } \output_stage_op__invert_out \output_stage_op__input_carry \output_stage_op__zero_a \output_stage_op__invert_a { \output_stage_op__oe__oe_ok \output_stage_op__oe__oe } { \output_stage_op__rc__rc_ok \output_stage_op__rc__rc } \output_stage_op__lk { \output_stage_op__imm_data__imm_ok \output_stage_op__imm_data__imm } \output_stage_op__fn_unit \output_stage_op__insn_type } { \core_final_stage_op__insn$43 \core_final_stage_op__data_len$42 \core_final_stage_op__is_signed$41 \core_final_stage_op__is_32bit$40 \core_final_stage_op__output_carry$39 { \core_final_stage_op__write_cr__ok$38 \core_final_stage_op__write_cr__data$37 } \core_final_stage_op__invert_out$36 \core_final_stage_op__input_carry$35 \core_final_stage_op__zero_a$34 \core_final_stage_op__invert_a$33 { \core_final_stage_op__oe__oe_ok$32 \core_final_stage_op__oe__oe$31 } { \core_final_stage_op__rc__rc_ok$30 \core_final_stage_op__rc__rc$29 } \core_final_stage_op__lk$28 { \core_final_stage_op__imm_data__imm_ok$27 \core_final_stage_op__imm_data__imm$26 } \core_final_stage_op__fn_unit$25 \core_final_stage_op__insn_type$24 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \ra$99 + process $group_53 + assign \ra$99 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \ra$99 \core_final_stage_ra$44 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \rb$100 + process $group_54 + assign \rb$100 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \rb$100 \core_final_stage_rb$45 + sync init + end + process $group_55 + assign \output_stage_xer_so 1'0 + assign \output_stage_xer_so \core_final_stage_xer_so$46 + sync init + end + process $group_56 + assign \output_stage_divisor_neg 1'0 + assign \output_stage_divisor_neg \core_final_stage_divisor_neg$47 + sync init + end + process $group_57 + assign \output_stage_dividend_neg 1'0 + assign \output_stage_dividend_neg \core_final_stage_dividend_neg$48 + sync init + end + process $group_58 + assign \output_stage_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_stage_quotient_root \core_final_stage_quotient_root$49 + sync init + end + process $group_59 + assign \output_stage_remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \output_stage_remainder \core_final_stage_remainder + sync init + end + process $group_60 + assign \output_muxid 2'00 + assign \output_muxid \output_stage_muxid$50 + sync init + end + process $group_61 + assign \output_op__insn_type 7'0000000 + assign \output_op__fn_unit 10'0000000000 + assign \output_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_op__imm_data__imm_ok 1'0 + assign \output_op__lk 1'0 + assign \output_op__rc__rc 1'0 + assign \output_op__rc__rc_ok 1'0 + assign \output_op__oe__oe 1'0 + assign \output_op__oe__oe_ok 1'0 + assign \output_op__invert_a 1'0 + assign \output_op__zero_a 1'0 + assign \output_op__input_carry 2'00 + assign \output_op__invert_out 1'0 + assign \output_op__write_cr__data 3'000 + assign \output_op__write_cr__ok 1'0 + assign \output_op__output_carry 1'0 + assign \output_op__is_32bit 1'0 + assign \output_op__is_signed 1'0 + assign \output_op__data_len 4'0000 + assign \output_op__insn 32'00000000000000000000000000000000 + assign { \output_op__insn \output_op__data_len \output_op__is_signed \output_op__is_32bit \output_op__output_carry { \output_op__write_cr__ok \output_op__write_cr__data } \output_op__invert_out \output_op__input_carry \output_op__zero_a \output_op__invert_a { \output_op__oe__oe_ok \output_op__oe__oe } { \output_op__rc__rc_ok \output_op__rc__rc } \output_op__lk { \output_op__imm_data__imm_ok \output_op__imm_data__imm } \output_op__fn_unit \output_op__insn_type } { \output_stage_op__insn$70 \output_stage_op__data_len$69 \output_stage_op__is_signed$68 \output_stage_op__is_32bit$67 \output_stage_op__output_carry$66 { \output_stage_op__write_cr__ok$65 \output_stage_op__write_cr__data$64 } \output_stage_op__invert_out$63 \output_stage_op__input_carry$62 \output_stage_op__zero_a$61 \output_stage_op__invert_a$60 { \output_stage_op__oe__oe_ok$59 \output_stage_op__oe__oe$58 } { \output_stage_op__rc__rc_ok$57 \output_stage_op__rc__rc$56 } \output_stage_op__lk$55 { \output_stage_op__imm_data__imm_ok$54 \output_stage_op__imm_data__imm$53 } \output_stage_op__fn_unit$52 \output_stage_op__insn_type$51 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \o_ok$101 + process $group_81 + assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \output_o_ok 1'0 + assign { \output_o_ok \output_o } { \o_ok$101 \output_stage_o } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \cr_a_ok$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 4 \cr_a$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \cr_a_ok$104 + process $group_83 + assign \output_cr_a 4'0000 + assign \cr_a_ok$102 1'0 + assign { \cr_a_ok$102 \output_cr_a } { \cr_a_ok$104 \cr_a$103 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_ca_ok$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \xer_ca$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_ca_ok$107 + process $group_85 + assign \output_xer_ca 2'00 + assign \xer_ca_ok$105 1'0 + assign { \xer_ca_ok$105 \output_xer_ca } { \xer_ca_ok$107 \xer_ca$106 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_ov_ok$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_ov_ok$109 + process $group_87 + assign \output_xer_ov 2'00 + assign \xer_ov_ok$108 1'0 + assign { \xer_ov_ok$108 \output_xer_ov } { \xer_ov_ok$109 \output_stage_xer_ov } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_so_ok$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_so_ok$111 + process $group_89 + assign \output_xer_so 1'0 + assign \xer_so_ok$110 1'0 + assign { \xer_so_ok$110 \output_xer_so } { \xer_so_ok$111 \output_stage_xer_so$71 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$112 + process $group_91 + assign \p_valid_i$112 1'0 + assign \p_valid_i$112 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_92 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$112 + connect \B \p_ready_o + connect \Y $113 + end + process $group_93 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $113 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$115 + process $group_94 + assign \muxid$115 2'00 + assign \muxid$115 \output_muxid$72 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$116 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$126 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$135 + process $group_95 + assign \op__insn_type$116 7'0000000 + assign \op__fn_unit$117 10'0000000000 + assign \op__imm_data__imm$118 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$119 1'0 + assign \op__lk$120 1'0 + assign \op__rc__rc$121 1'0 + assign \op__rc__rc_ok$122 1'0 + assign \op__oe__oe$123 1'0 + assign \op__oe__oe_ok$124 1'0 + assign \op__invert_a$125 1'0 + assign \op__zero_a$126 1'0 + assign \op__input_carry$127 2'00 + assign \op__invert_out$128 1'0 + assign \op__write_cr__data$129 3'000 + assign \op__write_cr__ok$130 1'0 + assign \op__output_carry$131 1'0 + assign \op__is_32bit$132 1'0 + assign \op__is_signed$133 1'0 + assign \op__data_len$134 4'0000 + assign \op__insn$135 32'00000000000000000000000000000000 + assign { \op__insn$135 \op__data_len$134 \op__is_signed$133 \op__is_32bit$132 \op__output_carry$131 { \op__write_cr__ok$130 \op__write_cr__data$129 } \op__invert_out$128 \op__input_carry$127 \op__zero_a$126 \op__invert_a$125 { \op__oe__oe_ok$124 \op__oe__oe$123 } { \op__rc__rc_ok$122 \op__rc__rc$121 } \op__lk$120 { \op__imm_data__imm_ok$119 \op__imm_data__imm$118 } \op__fn_unit$117 \op__insn_type$116 } { \output_op__insn$92 \output_op__data_len$91 \output_op__is_signed$90 \output_op__is_32bit$89 \output_op__output_carry$88 { \output_op__write_cr__ok$87 \output_op__write_cr__data$86 } \output_op__invert_out$85 \output_op__input_carry$84 \output_op__zero_a$83 \output_op__invert_a$82 { \output_op__oe__oe_ok$81 \output_op__oe__oe$80 } { \output_op__rc__rc_ok$79 \output_op__rc__rc$78 } \output_op__lk$77 { \output_op__imm_data__imm_ok$76 \output_op__imm_data__imm$75 } \output_op__fn_unit$74 \output_op__insn_type$73 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \o$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \o_ok$137 + process $group_115 + assign \o$136 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$137 1'0 + assign { \o_ok$137 \o$136 } { \output_o_ok$94 \output_o$93 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 4 \cr_a$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \cr_a_ok$139 + process $group_117 + assign \cr_a$138 4'0000 + assign \cr_a_ok$139 1'0 + assign { \cr_a_ok$139 \cr_a$138 } { \output_cr_a_ok \output_cr_a$95 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \xer_ca$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_ca_ok$141 + process $group_119 + assign \xer_ca$140 2'00 + assign \xer_ca_ok$141 1'0 + assign { \xer_ca_ok$141 \xer_ca$140 } { \output_xer_ca_ok \output_xer_ca$96 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \xer_ov$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_ov_ok$143 + process $group_121 + assign \xer_ov$142 2'00 + assign \xer_ov_ok$143 1'0 + assign { \xer_ov_ok$143 \xer_ov$142 } { \output_xer_ov_ok \output_xer_ov$97 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_so$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_so_ok$145 + process $group_123 + assign \xer_so$144 1'0 + assign \xer_so_ok$145 1'0 + assign { \xer_so_ok$145 \xer_so$144 } { \output_xer_so_ok \output_xer_so$98 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_125 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_126 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$115 + end + sync init + update \muxid$1 2'00 + sync posedge \clk + update \muxid$1 \muxid$1$next + end + process $group_127 + assign \op__insn_type$2$next \op__insn_type$2 + assign \op__fn_unit$3$next \op__fn_unit$3 + assign \op__imm_data__imm$4$next \op__imm_data__imm$4 + assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5 + assign \op__lk$6$next \op__lk$6 + assign \op__rc__rc$7$next \op__rc__rc$7 + assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8 + assign \op__oe__oe$9$next \op__oe__oe$9 + assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10 + assign \op__invert_a$11$next \op__invert_a$11 + assign \op__zero_a$12$next \op__zero_a$12 + assign \op__input_carry$13$next \op__input_carry$13 + assign \op__invert_out$14$next \op__invert_out$14 + assign \op__write_cr__data$15$next \op__write_cr__data$15 + assign \op__write_cr__ok$16$next \op__write_cr__ok$16 + assign \op__output_carry$17$next \op__output_carry$17 + assign \op__is_32bit$18$next \op__is_32bit$18 + assign \op__is_signed$19$next \op__is_signed$19 + assign \op__data_len$20$next \op__data_len$20 + assign \op__insn$21$next \op__insn$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$135 \op__data_len$134 \op__is_signed$133 \op__is_32bit$132 \op__output_carry$131 { \op__write_cr__ok$130 \op__write_cr__data$129 } \op__invert_out$128 \op__input_carry$127 \op__zero_a$126 \op__invert_a$125 { \op__oe__oe_ok$124 \op__oe__oe$123 } { \op__rc__rc_ok$122 \op__rc__rc$121 } \op__lk$120 { \op__imm_data__imm_ok$119 \op__imm_data__imm$118 } \op__fn_unit$117 \op__insn_type$116 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$135 \op__data_len$134 \op__is_signed$133 \op__is_32bit$132 \op__output_carry$131 { \op__write_cr__ok$130 \op__write_cr__data$129 } \op__invert_out$128 \op__input_carry$127 \op__zero_a$126 \op__invert_a$125 { \op__oe__oe_ok$124 \op__oe__oe$123 } { \op__rc__rc_ok$122 \op__rc__rc$121 } \op__lk$120 { \op__imm_data__imm_ok$119 \op__imm_data__imm$118 } \op__fn_unit$117 \op__insn_type$116 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$5$next 1'0 + assign \op__rc__rc$7$next 1'0 + assign \op__rc__rc_ok$8$next 1'0 + assign \op__oe__oe$9$next 1'0 + assign \op__oe__oe_ok$10$next 1'0 + assign \op__write_cr__data$15$next 3'000 + assign \op__write_cr__ok$16$next 1'0 + assign \op__insn$21$next 32'00000000000000000000000000000000 + end + sync init + update \op__insn_type$2 7'0000000 + update \op__fn_unit$3 10'0000000000 + update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 + update \op__imm_data__imm_ok$5 1'0 + update \op__lk$6 1'0 + update \op__rc__rc$7 1'0 + update \op__rc__rc_ok$8 1'0 + update \op__oe__oe$9 1'0 + update \op__oe__oe_ok$10 1'0 + update \op__invert_a$11 1'0 + update \op__zero_a$12 1'0 + update \op__input_carry$13 2'00 + update \op__invert_out$14 1'0 + update \op__write_cr__data$15 3'000 + update \op__write_cr__ok$16 1'0 + update \op__output_carry$17 1'0 + update \op__is_32bit$18 1'0 + update \op__is_signed$19 1'0 + update \op__data_len$20 4'0000 + update \op__insn$21 32'00000000000000000000000000000000 + sync posedge \clk + update \op__insn_type$2 \op__insn_type$2$next + update \op__fn_unit$3 \op__fn_unit$3$next + update \op__imm_data__imm$4 \op__imm_data__imm$4$next + update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next + update \op__lk$6 \op__lk$6$next + update \op__rc__rc$7 \op__rc__rc$7$next + update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next + update \op__oe__oe$9 \op__oe__oe$9$next + update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next + update \op__invert_a$11 \op__invert_a$11$next + update \op__zero_a$12 \op__zero_a$12$next + update \op__input_carry$13 \op__input_carry$13$next + update \op__invert_out$14 \op__invert_out$14$next + update \op__write_cr__data$15 \op__write_cr__data$15$next + update \op__write_cr__ok$16 \op__write_cr__ok$16$next + update \op__output_carry$17 \op__output_carry$17$next + update \op__is_32bit$18 \op__is_32bit$18$next + update \op__is_signed$19 \op__is_signed$19$next + update \op__data_len$20 \op__data_len$20$next + update \op__insn$21 \op__insn$21$next + end + process $group_147 + assign \o$next \o + assign \o_ok$next \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$next \o$next } { \o_ok$137 \o$136 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$next \o$next } { \o_ok$137 \o$136 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \o_ok$next 1'0 + end + sync init + update \o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok 1'0 + sync posedge \clk + update \o \o$next + update \o_ok \o_ok$next + end + process $group_149 + assign \cr_a$next \cr_a + assign \cr_a_ok$next \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$139 \cr_a$138 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$139 \cr_a$138 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \cr_a_ok$next 1'0 + end + sync init + update \cr_a 4'0000 + update \cr_a_ok 1'0 + sync posedge \clk + update \cr_a \cr_a$next + update \cr_a_ok \cr_a_ok$next + end + process $group_151 + assign \xer_ca$next \xer_ca + assign \xer_ca_ok$next \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$141 \xer_ca$140 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$141 \xer_ca$140 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \xer_ca_ok$next 1'0 + end + sync init + update \xer_ca 2'00 + update \xer_ca_ok 1'0 + sync posedge \clk + update \xer_ca \xer_ca$next + update \xer_ca_ok \xer_ca_ok$next + end + process $group_153 + assign \xer_ov$next \xer_ov + assign \xer_ov_ok$next \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$143 \xer_ov$142 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$143 \xer_ov$142 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \xer_ov_ok$next 1'0 + end + sync init + update \xer_ov 2'00 + update \xer_ov_ok 1'0 + sync posedge \clk + update \xer_ov \xer_ov$next + update \xer_ov_ok \xer_ov_ok$next + end + process $group_155 + assign \xer_so$22$next \xer_so$22 + assign \xer_so_ok$next \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_so_ok$next \xer_so$22$next } { \xer_so_ok$145 \xer_so$144 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_so_ok$next \xer_so$22$next } { \xer_so_ok$145 \xer_so$144 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \xer_so_ok$next 1'0 + end + sync init + update \xer_so$22 1'0 + update \xer_so_ok 1'0 + sync posedge \clk + update \xer_so$22 \xer_so$22$next + update \xer_so_ok \xer_so_ok$next + end + process $group_157 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_158 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end + connect \o_ok$101 1'0 + connect \cr_a$103 4'0000 + connect \cr_a_ok$104 1'0 + connect \xer_ca$106 2'00 + connect \xer_ca_ok$107 1'0 + connect \xer_ov_ok$109 1'0 + connect \xer_so_ok$111 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu" +module \alu$45 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 3 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 4 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 4 output 5 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 6 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 7 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 8 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 9 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 10 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 11 \xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 12 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 13 \n_ready_i + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 14 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 15 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 16 \op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 20 \op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 21 \op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 22 \op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 23 \op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 24 \op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 25 \op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 26 \op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 27 \op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 28 \op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 29 \op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 30 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 31 \op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 32 \op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 33 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 34 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 35 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 36 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 37 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 38 \p_ready_o + cell \p$46 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$47 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_start_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_start_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_start_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_start_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_start_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_start_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_start_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_start_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_start_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_start_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_start_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_start_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_start_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_start_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_start_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_start_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_start_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_start_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_start_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_start_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_start_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_start_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_start_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_start_muxid$2 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_start_op__insn_type$3 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_start_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_start_op__imm_data__imm$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__imm_data__imm_ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__lk$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__rc__rc$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__rc__rc_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__oe__oe$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__oe__oe_ok$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__invert_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__zero_a$13 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_start_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__invert_out$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_start_op__write_cr__data$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__write_cr__ok$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__output_carry$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__is_32bit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_start_op__is_signed$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_start_op__data_len$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_start_op__insn$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_start_ra$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_start_rb$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_start_xer_so$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 \pipe_start_xer_ca + cell \pipe_start \pipe_start + connect \rst \rst + connect \clk \clk + connect \n_valid_o \pipe_start_n_valid_o + connect \n_ready_i \pipe_start_n_ready_i + connect \muxid \pipe_start_muxid + connect \op__insn_type \pipe_start_op__insn_type + connect \op__fn_unit \pipe_start_op__fn_unit + connect \op__imm_data__imm \pipe_start_op__imm_data__imm + connect \op__imm_data__imm_ok \pipe_start_op__imm_data__imm_ok + connect \op__lk \pipe_start_op__lk + connect \op__rc__rc \pipe_start_op__rc__rc + connect \op__rc__rc_ok \pipe_start_op__rc__rc_ok + connect \op__oe__oe \pipe_start_op__oe__oe + connect \op__oe__oe_ok \pipe_start_op__oe__oe_ok + connect \op__invert_a \pipe_start_op__invert_a + connect \op__zero_a \pipe_start_op__zero_a + connect \op__input_carry \pipe_start_op__input_carry + connect \op__invert_out \pipe_start_op__invert_out + connect \op__write_cr__data \pipe_start_op__write_cr__data + connect \op__write_cr__ok \pipe_start_op__write_cr__ok + connect \op__output_carry \pipe_start_op__output_carry + connect \op__is_32bit \pipe_start_op__is_32bit + connect \op__is_signed \pipe_start_op__is_signed + connect \op__data_len \pipe_start_op__data_len + connect \op__insn \pipe_start_op__insn + connect \ra \pipe_start_ra + connect \rb \pipe_start_rb + connect \xer_so \pipe_start_xer_so + connect \divisor_neg \pipe_start_divisor_neg + connect \dividend_neg \pipe_start_dividend_neg + connect \divisor_radicand \pipe_start_divisor_radicand + connect \operation \pipe_start_operation + connect \quotient_root \pipe_start_quotient_root + connect \root_times_radicand \pipe_start_root_times_radicand + connect \compare_lhs \pipe_start_compare_lhs + connect \compare_rhs \pipe_start_compare_rhs + connect \p_valid_i \pipe_start_p_valid_i + connect \p_ready_o \pipe_start_p_ready_o + connect \muxid$1 \pipe_start_muxid$2 + connect \op__insn_type$2 \pipe_start_op__insn_type$3 + connect \op__fn_unit$3 \pipe_start_op__fn_unit$4 + connect \op__imm_data__imm$4 \pipe_start_op__imm_data__imm$5 + connect \op__imm_data__imm_ok$5 \pipe_start_op__imm_data__imm_ok$6 + connect \op__lk$6 \pipe_start_op__lk$7 + connect \op__rc__rc$7 \pipe_start_op__rc__rc$8 + connect \op__rc__rc_ok$8 \pipe_start_op__rc__rc_ok$9 + connect \op__oe__oe$9 \pipe_start_op__oe__oe$10 + connect \op__oe__oe_ok$10 \pipe_start_op__oe__oe_ok$11 + connect \op__invert_a$11 \pipe_start_op__invert_a$12 + connect \op__zero_a$12 \pipe_start_op__zero_a$13 + connect \op__input_carry$13 \pipe_start_op__input_carry$14 + connect \op__invert_out$14 \pipe_start_op__invert_out$15 + connect \op__write_cr__data$15 \pipe_start_op__write_cr__data$16 + connect \op__write_cr__ok$16 \pipe_start_op__write_cr__ok$17 + connect \op__output_carry$17 \pipe_start_op__output_carry$18 + connect \op__is_32bit$18 \pipe_start_op__is_32bit$19 + connect \op__is_signed$19 \pipe_start_op__is_signed$20 + connect \op__data_len$20 \pipe_start_op__data_len$21 + connect \op__insn$21 \pipe_start_op__insn$22 + connect \ra$22 \pipe_start_ra$23 + connect \rb$23 \pipe_start_rb$24 + connect \xer_so$24 \pipe_start_xer_so$25 + connect \xer_ca \pipe_start_xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_0_to_2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_0_to_2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_0_to_2_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_0_to_2_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_0_to_2_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_0_to_2_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_0_to_2_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_0_to_2_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_0_to_2_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_0_to_2_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_0_to_2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_0_to_2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_0_to_2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_0_to_2_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_0_to_2_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_0_to_2_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_0_to_2_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_0_to_2_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_0_to_2_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_0_to_2_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_0_to_2_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_0_to_2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_0_to_2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_0_to_2_muxid$26 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_0_to_2_op__insn_type$27 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_0_to_2_op__fn_unit$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_0_to_2_op__imm_data__imm$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__imm_data__imm_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__lk$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__rc__rc$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__rc__rc_ok$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__oe__oe$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__oe__oe_ok$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__invert_a$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__zero_a$37 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_0_to_2_op__input_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__invert_out$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_0_to_2_op__write_cr__data$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__write_cr__ok$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__output_carry$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_0_to_2_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_0_to_2_op__data_len$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_0_to_2_op__insn$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_0_to_2_ra$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_0_to_2_rb$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_0_to_2_xer_so$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_0_to_2_divisor_neg$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_0_to_2_dividend_neg$51 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_0_to_2_divisor_radicand$52 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_0_to_2_operation$53 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_0_to_2_quotient_root$54 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_0_to_2_root_times_radicand$55 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_0_to_2_compare_lhs$56 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_0_to_2_compare_rhs$57 + cell \pipe_0_to_2 \pipe_0_to_2 + connect \rst \rst + connect \clk \clk + connect \p_valid_i \pipe_0_to_2_p_valid_i + connect \p_ready_o \pipe_0_to_2_p_ready_o + connect \muxid \pipe_0_to_2_muxid + connect \op__insn_type \pipe_0_to_2_op__insn_type + connect \op__fn_unit \pipe_0_to_2_op__fn_unit + connect \op__imm_data__imm \pipe_0_to_2_op__imm_data__imm + connect \op__imm_data__imm_ok \pipe_0_to_2_op__imm_data__imm_ok + connect \op__lk \pipe_0_to_2_op__lk + connect \op__rc__rc \pipe_0_to_2_op__rc__rc + connect \op__rc__rc_ok \pipe_0_to_2_op__rc__rc_ok + connect \op__oe__oe \pipe_0_to_2_op__oe__oe + connect \op__oe__oe_ok \pipe_0_to_2_op__oe__oe_ok + connect \op__invert_a \pipe_0_to_2_op__invert_a + connect \op__zero_a \pipe_0_to_2_op__zero_a + connect \op__input_carry \pipe_0_to_2_op__input_carry + connect \op__invert_out \pipe_0_to_2_op__invert_out + connect \op__write_cr__data \pipe_0_to_2_op__write_cr__data + connect \op__write_cr__ok \pipe_0_to_2_op__write_cr__ok + connect \op__output_carry \pipe_0_to_2_op__output_carry + connect \op__is_32bit \pipe_0_to_2_op__is_32bit + connect \op__is_signed \pipe_0_to_2_op__is_signed + connect \op__data_len \pipe_0_to_2_op__data_len + connect \op__insn \pipe_0_to_2_op__insn + connect \ra \pipe_0_to_2_ra + connect \rb \pipe_0_to_2_rb + connect \xer_so \pipe_0_to_2_xer_so + connect \divisor_neg \pipe_0_to_2_divisor_neg + connect \dividend_neg \pipe_0_to_2_dividend_neg + connect \divisor_radicand \pipe_0_to_2_divisor_radicand + connect \operation \pipe_0_to_2_operation + connect \quotient_root \pipe_0_to_2_quotient_root + connect \root_times_radicand \pipe_0_to_2_root_times_radicand + connect \compare_lhs \pipe_0_to_2_compare_lhs + connect \compare_rhs \pipe_0_to_2_compare_rhs + connect \n_valid_o \pipe_0_to_2_n_valid_o + connect \n_ready_i \pipe_0_to_2_n_ready_i + connect \muxid$1 \pipe_0_to_2_muxid$26 + connect \op__insn_type$2 \pipe_0_to_2_op__insn_type$27 + connect \op__fn_unit$3 \pipe_0_to_2_op__fn_unit$28 + connect \op__imm_data__imm$4 \pipe_0_to_2_op__imm_data__imm$29 + connect \op__imm_data__imm_ok$5 \pipe_0_to_2_op__imm_data__imm_ok$30 + connect \op__lk$6 \pipe_0_to_2_op__lk$31 + connect \op__rc__rc$7 \pipe_0_to_2_op__rc__rc$32 + connect \op__rc__rc_ok$8 \pipe_0_to_2_op__rc__rc_ok$33 + connect \op__oe__oe$9 \pipe_0_to_2_op__oe__oe$34 + connect \op__oe__oe_ok$10 \pipe_0_to_2_op__oe__oe_ok$35 + connect \op__invert_a$11 \pipe_0_to_2_op__invert_a$36 + connect \op__zero_a$12 \pipe_0_to_2_op__zero_a$37 + connect \op__input_carry$13 \pipe_0_to_2_op__input_carry$38 + connect \op__invert_out$14 \pipe_0_to_2_op__invert_out$39 + connect \op__write_cr__data$15 \pipe_0_to_2_op__write_cr__data$40 + connect \op__write_cr__ok$16 \pipe_0_to_2_op__write_cr__ok$41 + connect \op__output_carry$17 \pipe_0_to_2_op__output_carry$42 + connect \op__is_32bit$18 \pipe_0_to_2_op__is_32bit$43 + connect \op__is_signed$19 \pipe_0_to_2_op__is_signed$44 + connect \op__data_len$20 \pipe_0_to_2_op__data_len$45 + connect \op__insn$21 \pipe_0_to_2_op__insn$46 + connect \ra$22 \pipe_0_to_2_ra$47 + connect \rb$23 \pipe_0_to_2_rb$48 + connect \xer_so$24 \pipe_0_to_2_xer_so$49 + connect \divisor_neg$25 \pipe_0_to_2_divisor_neg$50 + connect \dividend_neg$26 \pipe_0_to_2_dividend_neg$51 + connect \divisor_radicand$27 \pipe_0_to_2_divisor_radicand$52 + connect \operation$28 \pipe_0_to_2_operation$53 + connect \quotient_root$29 \pipe_0_to_2_quotient_root$54 + connect \root_times_radicand$30 \pipe_0_to_2_root_times_radicand$55 + connect \compare_lhs$31 \pipe_0_to_2_compare_lhs$56 + connect \compare_rhs$32 \pipe_0_to_2_compare_rhs$57 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_2_to_4_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_2_to_4_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_2_to_4_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_2_to_4_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_2_to_4_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_2_to_4_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_2_to_4_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_2_to_4_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_2_to_4_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_2_to_4_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_2_to_4_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_2_to_4_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_2_to_4_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_2_to_4_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_2_to_4_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_2_to_4_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_2_to_4_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_2_to_4_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_2_to_4_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_2_to_4_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_2_to_4_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_2_to_4_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_2_to_4_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_2_to_4_muxid$58 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_2_to_4_op__insn_type$59 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_2_to_4_op__fn_unit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_2_to_4_op__imm_data__imm$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__imm_data__imm_ok$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__lk$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__rc__rc$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__rc__rc_ok$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__oe__oe$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__oe__oe_ok$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__invert_a$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__zero_a$69 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_2_to_4_op__input_carry$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__invert_out$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_2_to_4_op__write_cr__data$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__write_cr__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__output_carry$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__is_32bit$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_2_to_4_op__is_signed$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_2_to_4_op__data_len$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_2_to_4_op__insn$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_2_to_4_ra$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_2_to_4_rb$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_2_to_4_xer_so$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_2_to_4_divisor_neg$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_2_to_4_dividend_neg$83 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_2_to_4_divisor_radicand$84 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_2_to_4_operation$85 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_2_to_4_quotient_root$86 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_2_to_4_root_times_radicand$87 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_2_to_4_compare_lhs$88 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_2_to_4_compare_rhs$89 + cell \pipe_2_to_4 \pipe_2_to_4 + connect \rst \rst + connect \clk \clk + connect \p_valid_i \pipe_2_to_4_p_valid_i + connect \p_ready_o \pipe_2_to_4_p_ready_o + connect \muxid \pipe_2_to_4_muxid + connect \op__insn_type \pipe_2_to_4_op__insn_type + connect \op__fn_unit \pipe_2_to_4_op__fn_unit + connect \op__imm_data__imm \pipe_2_to_4_op__imm_data__imm + connect \op__imm_data__imm_ok \pipe_2_to_4_op__imm_data__imm_ok + connect \op__lk \pipe_2_to_4_op__lk + connect \op__rc__rc \pipe_2_to_4_op__rc__rc + connect \op__rc__rc_ok \pipe_2_to_4_op__rc__rc_ok + connect \op__oe__oe \pipe_2_to_4_op__oe__oe + connect \op__oe__oe_ok \pipe_2_to_4_op__oe__oe_ok + connect \op__invert_a \pipe_2_to_4_op__invert_a + connect \op__zero_a \pipe_2_to_4_op__zero_a + connect \op__input_carry \pipe_2_to_4_op__input_carry + connect \op__invert_out \pipe_2_to_4_op__invert_out + connect \op__write_cr__data \pipe_2_to_4_op__write_cr__data + connect \op__write_cr__ok \pipe_2_to_4_op__write_cr__ok + connect \op__output_carry \pipe_2_to_4_op__output_carry + connect \op__is_32bit \pipe_2_to_4_op__is_32bit + connect \op__is_signed \pipe_2_to_4_op__is_signed + connect \op__data_len \pipe_2_to_4_op__data_len + connect \op__insn \pipe_2_to_4_op__insn + connect \ra \pipe_2_to_4_ra + connect \rb \pipe_2_to_4_rb + connect \xer_so \pipe_2_to_4_xer_so + connect \divisor_neg \pipe_2_to_4_divisor_neg + connect \dividend_neg \pipe_2_to_4_dividend_neg + connect \divisor_radicand \pipe_2_to_4_divisor_radicand + connect \operation \pipe_2_to_4_operation + connect \quotient_root \pipe_2_to_4_quotient_root + connect \root_times_radicand \pipe_2_to_4_root_times_radicand + connect \compare_lhs \pipe_2_to_4_compare_lhs + connect \compare_rhs \pipe_2_to_4_compare_rhs + connect \n_valid_o \pipe_2_to_4_n_valid_o + connect \n_ready_i \pipe_2_to_4_n_ready_i + connect \muxid$1 \pipe_2_to_4_muxid$58 + connect \op__insn_type$2 \pipe_2_to_4_op__insn_type$59 + connect \op__fn_unit$3 \pipe_2_to_4_op__fn_unit$60 + connect \op__imm_data__imm$4 \pipe_2_to_4_op__imm_data__imm$61 + connect \op__imm_data__imm_ok$5 \pipe_2_to_4_op__imm_data__imm_ok$62 + connect \op__lk$6 \pipe_2_to_4_op__lk$63 + connect \op__rc__rc$7 \pipe_2_to_4_op__rc__rc$64 + connect \op__rc__rc_ok$8 \pipe_2_to_4_op__rc__rc_ok$65 + connect \op__oe__oe$9 \pipe_2_to_4_op__oe__oe$66 + connect \op__oe__oe_ok$10 \pipe_2_to_4_op__oe__oe_ok$67 + connect \op__invert_a$11 \pipe_2_to_4_op__invert_a$68 + connect \op__zero_a$12 \pipe_2_to_4_op__zero_a$69 + connect \op__input_carry$13 \pipe_2_to_4_op__input_carry$70 + connect \op__invert_out$14 \pipe_2_to_4_op__invert_out$71 + connect \op__write_cr__data$15 \pipe_2_to_4_op__write_cr__data$72 + connect \op__write_cr__ok$16 \pipe_2_to_4_op__write_cr__ok$73 + connect \op__output_carry$17 \pipe_2_to_4_op__output_carry$74 + connect \op__is_32bit$18 \pipe_2_to_4_op__is_32bit$75 + connect \op__is_signed$19 \pipe_2_to_4_op__is_signed$76 + connect \op__data_len$20 \pipe_2_to_4_op__data_len$77 + connect \op__insn$21 \pipe_2_to_4_op__insn$78 + connect \ra$22 \pipe_2_to_4_ra$79 + connect \rb$23 \pipe_2_to_4_rb$80 + connect \xer_so$24 \pipe_2_to_4_xer_so$81 + connect \divisor_neg$25 \pipe_2_to_4_divisor_neg$82 + connect \dividend_neg$26 \pipe_2_to_4_dividend_neg$83 + connect \divisor_radicand$27 \pipe_2_to_4_divisor_radicand$84 + connect \operation$28 \pipe_2_to_4_operation$85 + connect \quotient_root$29 \pipe_2_to_4_quotient_root$86 + connect \root_times_radicand$30 \pipe_2_to_4_root_times_radicand$87 + connect \compare_lhs$31 \pipe_2_to_4_compare_lhs$88 + connect \compare_rhs$32 \pipe_2_to_4_compare_rhs$89 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_4_to_6_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_4_to_6_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_4_to_6_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_4_to_6_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_4_to_6_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_4_to_6_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_4_to_6_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_4_to_6_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_4_to_6_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_4_to_6_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_4_to_6_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_4_to_6_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_4_to_6_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_4_to_6_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_4_to_6_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_4_to_6_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_4_to_6_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_4_to_6_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_4_to_6_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_4_to_6_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_4_to_6_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_4_to_6_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_4_to_6_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_4_to_6_muxid$90 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_4_to_6_op__insn_type$91 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_4_to_6_op__fn_unit$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_4_to_6_op__imm_data__imm$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__imm_data__imm_ok$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__lk$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__rc__rc$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__rc__rc_ok$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__oe__oe$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__oe__oe_ok$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__invert_a$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__zero_a$101 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_4_to_6_op__input_carry$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__invert_out$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_4_to_6_op__write_cr__data$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__write_cr__ok$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__output_carry$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__is_32bit$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_4_to_6_op__is_signed$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_4_to_6_op__data_len$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_4_to_6_op__insn$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_4_to_6_ra$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_4_to_6_rb$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_4_to_6_xer_so$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_4_to_6_divisor_neg$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_4_to_6_dividend_neg$115 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_4_to_6_divisor_radicand$116 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_4_to_6_operation$117 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_4_to_6_quotient_root$118 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_4_to_6_root_times_radicand$119 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_4_to_6_compare_lhs$120 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_4_to_6_compare_rhs$121 + cell \pipe_4_to_6 \pipe_4_to_6 + connect \rst \rst + connect \clk \clk + connect \p_valid_i \pipe_4_to_6_p_valid_i + connect \p_ready_o \pipe_4_to_6_p_ready_o + connect \muxid \pipe_4_to_6_muxid + connect \op__insn_type \pipe_4_to_6_op__insn_type + connect \op__fn_unit \pipe_4_to_6_op__fn_unit + connect \op__imm_data__imm \pipe_4_to_6_op__imm_data__imm + connect \op__imm_data__imm_ok \pipe_4_to_6_op__imm_data__imm_ok + connect \op__lk \pipe_4_to_6_op__lk + connect \op__rc__rc \pipe_4_to_6_op__rc__rc + connect \op__rc__rc_ok \pipe_4_to_6_op__rc__rc_ok + connect \op__oe__oe \pipe_4_to_6_op__oe__oe + connect \op__oe__oe_ok \pipe_4_to_6_op__oe__oe_ok + connect \op__invert_a \pipe_4_to_6_op__invert_a + connect \op__zero_a \pipe_4_to_6_op__zero_a + connect \op__input_carry \pipe_4_to_6_op__input_carry + connect \op__invert_out \pipe_4_to_6_op__invert_out + connect \op__write_cr__data \pipe_4_to_6_op__write_cr__data + connect \op__write_cr__ok \pipe_4_to_6_op__write_cr__ok + connect \op__output_carry \pipe_4_to_6_op__output_carry + connect \op__is_32bit \pipe_4_to_6_op__is_32bit + connect \op__is_signed \pipe_4_to_6_op__is_signed + connect \op__data_len \pipe_4_to_6_op__data_len + connect \op__insn \pipe_4_to_6_op__insn + connect \ra \pipe_4_to_6_ra + connect \rb \pipe_4_to_6_rb + connect \xer_so \pipe_4_to_6_xer_so + connect \divisor_neg \pipe_4_to_6_divisor_neg + connect \dividend_neg \pipe_4_to_6_dividend_neg + connect \divisor_radicand \pipe_4_to_6_divisor_radicand + connect \operation \pipe_4_to_6_operation + connect \quotient_root \pipe_4_to_6_quotient_root + connect \root_times_radicand \pipe_4_to_6_root_times_radicand + connect \compare_lhs \pipe_4_to_6_compare_lhs + connect \compare_rhs \pipe_4_to_6_compare_rhs + connect \n_valid_o \pipe_4_to_6_n_valid_o + connect \n_ready_i \pipe_4_to_6_n_ready_i + connect \muxid$1 \pipe_4_to_6_muxid$90 + connect \op__insn_type$2 \pipe_4_to_6_op__insn_type$91 + connect \op__fn_unit$3 \pipe_4_to_6_op__fn_unit$92 + connect \op__imm_data__imm$4 \pipe_4_to_6_op__imm_data__imm$93 + connect \op__imm_data__imm_ok$5 \pipe_4_to_6_op__imm_data__imm_ok$94 + connect \op__lk$6 \pipe_4_to_6_op__lk$95 + connect \op__rc__rc$7 \pipe_4_to_6_op__rc__rc$96 + connect \op__rc__rc_ok$8 \pipe_4_to_6_op__rc__rc_ok$97 + connect \op__oe__oe$9 \pipe_4_to_6_op__oe__oe$98 + connect \op__oe__oe_ok$10 \pipe_4_to_6_op__oe__oe_ok$99 + connect \op__invert_a$11 \pipe_4_to_6_op__invert_a$100 + connect \op__zero_a$12 \pipe_4_to_6_op__zero_a$101 + connect \op__input_carry$13 \pipe_4_to_6_op__input_carry$102 + connect \op__invert_out$14 \pipe_4_to_6_op__invert_out$103 + connect \op__write_cr__data$15 \pipe_4_to_6_op__write_cr__data$104 + connect \op__write_cr__ok$16 \pipe_4_to_6_op__write_cr__ok$105 + connect \op__output_carry$17 \pipe_4_to_6_op__output_carry$106 + connect \op__is_32bit$18 \pipe_4_to_6_op__is_32bit$107 + connect \op__is_signed$19 \pipe_4_to_6_op__is_signed$108 + connect \op__data_len$20 \pipe_4_to_6_op__data_len$109 + connect \op__insn$21 \pipe_4_to_6_op__insn$110 + connect \ra$22 \pipe_4_to_6_ra$111 + connect \rb$23 \pipe_4_to_6_rb$112 + connect \xer_so$24 \pipe_4_to_6_xer_so$113 + connect \divisor_neg$25 \pipe_4_to_6_divisor_neg$114 + connect \dividend_neg$26 \pipe_4_to_6_dividend_neg$115 + connect \divisor_radicand$27 \pipe_4_to_6_divisor_radicand$116 + connect \operation$28 \pipe_4_to_6_operation$117 + connect \quotient_root$29 \pipe_4_to_6_quotient_root$118 + connect \root_times_radicand$30 \pipe_4_to_6_root_times_radicand$119 + connect \compare_lhs$31 \pipe_4_to_6_compare_lhs$120 + connect \compare_rhs$32 \pipe_4_to_6_compare_rhs$121 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_6_to_8_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_6_to_8_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_6_to_8_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_6_to_8_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_6_to_8_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_6_to_8_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_6_to_8_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_6_to_8_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_6_to_8_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_6_to_8_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_6_to_8_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_6_to_8_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_6_to_8_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_6_to_8_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_6_to_8_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_6_to_8_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_6_to_8_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_6_to_8_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_6_to_8_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_6_to_8_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_6_to_8_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_6_to_8_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_6_to_8_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_6_to_8_muxid$122 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_6_to_8_op__insn_type$123 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_6_to_8_op__fn_unit$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_6_to_8_op__imm_data__imm$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__imm_data__imm_ok$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__lk$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__rc__rc$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__rc__rc_ok$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__oe__oe$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__oe__oe_ok$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__invert_a$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__zero_a$133 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_6_to_8_op__input_carry$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__invert_out$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_6_to_8_op__write_cr__data$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__write_cr__ok$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__output_carry$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__is_32bit$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_6_to_8_op__is_signed$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_6_to_8_op__data_len$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_6_to_8_op__insn$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_6_to_8_ra$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_6_to_8_rb$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_6_to_8_xer_so$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_6_to_8_divisor_neg$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_6_to_8_dividend_neg$147 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_6_to_8_divisor_radicand$148 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_6_to_8_operation$149 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_6_to_8_quotient_root$150 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_6_to_8_root_times_radicand$151 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_6_to_8_compare_lhs$152 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_6_to_8_compare_rhs$153 + cell \pipe_6_to_8 \pipe_6_to_8 + connect \rst \rst + connect \clk \clk + connect \p_valid_i \pipe_6_to_8_p_valid_i + connect \p_ready_o \pipe_6_to_8_p_ready_o + connect \muxid \pipe_6_to_8_muxid + connect \op__insn_type \pipe_6_to_8_op__insn_type + connect \op__fn_unit \pipe_6_to_8_op__fn_unit + connect \op__imm_data__imm \pipe_6_to_8_op__imm_data__imm + connect \op__imm_data__imm_ok \pipe_6_to_8_op__imm_data__imm_ok + connect \op__lk \pipe_6_to_8_op__lk + connect \op__rc__rc \pipe_6_to_8_op__rc__rc + connect \op__rc__rc_ok \pipe_6_to_8_op__rc__rc_ok + connect \op__oe__oe \pipe_6_to_8_op__oe__oe + connect \op__oe__oe_ok \pipe_6_to_8_op__oe__oe_ok + connect \op__invert_a \pipe_6_to_8_op__invert_a + connect \op__zero_a \pipe_6_to_8_op__zero_a + connect \op__input_carry \pipe_6_to_8_op__input_carry + connect \op__invert_out \pipe_6_to_8_op__invert_out + connect \op__write_cr__data \pipe_6_to_8_op__write_cr__data + connect \op__write_cr__ok \pipe_6_to_8_op__write_cr__ok + connect \op__output_carry \pipe_6_to_8_op__output_carry + connect \op__is_32bit \pipe_6_to_8_op__is_32bit + connect \op__is_signed \pipe_6_to_8_op__is_signed + connect \op__data_len \pipe_6_to_8_op__data_len + connect \op__insn \pipe_6_to_8_op__insn + connect \ra \pipe_6_to_8_ra + connect \rb \pipe_6_to_8_rb + connect \xer_so \pipe_6_to_8_xer_so + connect \divisor_neg \pipe_6_to_8_divisor_neg + connect \dividend_neg \pipe_6_to_8_dividend_neg + connect \divisor_radicand \pipe_6_to_8_divisor_radicand + connect \operation \pipe_6_to_8_operation + connect \quotient_root \pipe_6_to_8_quotient_root + connect \root_times_radicand \pipe_6_to_8_root_times_radicand + connect \compare_lhs \pipe_6_to_8_compare_lhs + connect \compare_rhs \pipe_6_to_8_compare_rhs + connect \n_valid_o \pipe_6_to_8_n_valid_o + connect \n_ready_i \pipe_6_to_8_n_ready_i + connect \muxid$1 \pipe_6_to_8_muxid$122 + connect \op__insn_type$2 \pipe_6_to_8_op__insn_type$123 + connect \op__fn_unit$3 \pipe_6_to_8_op__fn_unit$124 + connect \op__imm_data__imm$4 \pipe_6_to_8_op__imm_data__imm$125 + connect \op__imm_data__imm_ok$5 \pipe_6_to_8_op__imm_data__imm_ok$126 + connect \op__lk$6 \pipe_6_to_8_op__lk$127 + connect \op__rc__rc$7 \pipe_6_to_8_op__rc__rc$128 + connect \op__rc__rc_ok$8 \pipe_6_to_8_op__rc__rc_ok$129 + connect \op__oe__oe$9 \pipe_6_to_8_op__oe__oe$130 + connect \op__oe__oe_ok$10 \pipe_6_to_8_op__oe__oe_ok$131 + connect \op__invert_a$11 \pipe_6_to_8_op__invert_a$132 + connect \op__zero_a$12 \pipe_6_to_8_op__zero_a$133 + connect \op__input_carry$13 \pipe_6_to_8_op__input_carry$134 + connect \op__invert_out$14 \pipe_6_to_8_op__invert_out$135 + connect \op__write_cr__data$15 \pipe_6_to_8_op__write_cr__data$136 + connect \op__write_cr__ok$16 \pipe_6_to_8_op__write_cr__ok$137 + connect \op__output_carry$17 \pipe_6_to_8_op__output_carry$138 + connect \op__is_32bit$18 \pipe_6_to_8_op__is_32bit$139 + connect \op__is_signed$19 \pipe_6_to_8_op__is_signed$140 + connect \op__data_len$20 \pipe_6_to_8_op__data_len$141 + connect \op__insn$21 \pipe_6_to_8_op__insn$142 + connect \ra$22 \pipe_6_to_8_ra$143 + connect \rb$23 \pipe_6_to_8_rb$144 + connect \xer_so$24 \pipe_6_to_8_xer_so$145 + connect \divisor_neg$25 \pipe_6_to_8_divisor_neg$146 + connect \dividend_neg$26 \pipe_6_to_8_dividend_neg$147 + connect \divisor_radicand$27 \pipe_6_to_8_divisor_radicand$148 + connect \operation$28 \pipe_6_to_8_operation$149 + connect \quotient_root$29 \pipe_6_to_8_quotient_root$150 + connect \root_times_radicand$30 \pipe_6_to_8_root_times_radicand$151 + connect \compare_lhs$31 \pipe_6_to_8_compare_lhs$152 + connect \compare_rhs$32 \pipe_6_to_8_compare_rhs$153 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_8_to_10_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_8_to_10_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_8_to_10_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_8_to_10_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_8_to_10_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_8_to_10_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_8_to_10_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_8_to_10_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_8_to_10_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_8_to_10_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_8_to_10_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_8_to_10_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_8_to_10_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_8_to_10_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_8_to_10_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_8_to_10_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_8_to_10_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_8_to_10_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_8_to_10_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_8_to_10_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_8_to_10_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_8_to_10_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_8_to_10_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_8_to_10_muxid$154 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_8_to_10_op__insn_type$155 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_8_to_10_op__fn_unit$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_8_to_10_op__imm_data__imm$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__imm_data__imm_ok$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__lk$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__rc__rc$160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__rc__rc_ok$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__oe__oe$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__oe__oe_ok$163 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__invert_a$164 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__zero_a$165 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_8_to_10_op__input_carry$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__invert_out$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_8_to_10_op__write_cr__data$168 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__write_cr__ok$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__output_carry$170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__is_32bit$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_8_to_10_op__is_signed$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_8_to_10_op__data_len$173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_8_to_10_op__insn$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_8_to_10_ra$175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_8_to_10_rb$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_8_to_10_xer_so$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_8_to_10_divisor_neg$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_8_to_10_dividend_neg$179 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_8_to_10_divisor_radicand$180 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_8_to_10_operation$181 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_8_to_10_quotient_root$182 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_8_to_10_root_times_radicand$183 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_8_to_10_compare_lhs$184 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_8_to_10_compare_rhs$185 + cell \pipe_8_to_10 \pipe_8_to_10 + connect \rst \rst + connect \clk \clk + connect \p_valid_i \pipe_8_to_10_p_valid_i + connect \p_ready_o \pipe_8_to_10_p_ready_o + connect \muxid \pipe_8_to_10_muxid + connect \op__insn_type \pipe_8_to_10_op__insn_type + connect \op__fn_unit \pipe_8_to_10_op__fn_unit + connect \op__imm_data__imm \pipe_8_to_10_op__imm_data__imm + connect \op__imm_data__imm_ok \pipe_8_to_10_op__imm_data__imm_ok + connect \op__lk \pipe_8_to_10_op__lk + connect \op__rc__rc \pipe_8_to_10_op__rc__rc + connect \op__rc__rc_ok \pipe_8_to_10_op__rc__rc_ok + connect \op__oe__oe \pipe_8_to_10_op__oe__oe + connect \op__oe__oe_ok \pipe_8_to_10_op__oe__oe_ok + connect \op__invert_a \pipe_8_to_10_op__invert_a + connect \op__zero_a \pipe_8_to_10_op__zero_a + connect \op__input_carry \pipe_8_to_10_op__input_carry + connect \op__invert_out \pipe_8_to_10_op__invert_out + connect \op__write_cr__data \pipe_8_to_10_op__write_cr__data + connect \op__write_cr__ok \pipe_8_to_10_op__write_cr__ok + connect \op__output_carry \pipe_8_to_10_op__output_carry + connect \op__is_32bit \pipe_8_to_10_op__is_32bit + connect \op__is_signed \pipe_8_to_10_op__is_signed + connect \op__data_len \pipe_8_to_10_op__data_len + connect \op__insn \pipe_8_to_10_op__insn + connect \ra \pipe_8_to_10_ra + connect \rb \pipe_8_to_10_rb + connect \xer_so \pipe_8_to_10_xer_so + connect \divisor_neg \pipe_8_to_10_divisor_neg + connect \dividend_neg \pipe_8_to_10_dividend_neg + connect \divisor_radicand \pipe_8_to_10_divisor_radicand + connect \operation \pipe_8_to_10_operation + connect \quotient_root \pipe_8_to_10_quotient_root + connect \root_times_radicand \pipe_8_to_10_root_times_radicand + connect \compare_lhs \pipe_8_to_10_compare_lhs + connect \compare_rhs \pipe_8_to_10_compare_rhs + connect \n_valid_o \pipe_8_to_10_n_valid_o + connect \n_ready_i \pipe_8_to_10_n_ready_i + connect \muxid$1 \pipe_8_to_10_muxid$154 + connect \op__insn_type$2 \pipe_8_to_10_op__insn_type$155 + connect \op__fn_unit$3 \pipe_8_to_10_op__fn_unit$156 + connect \op__imm_data__imm$4 \pipe_8_to_10_op__imm_data__imm$157 + connect \op__imm_data__imm_ok$5 \pipe_8_to_10_op__imm_data__imm_ok$158 + connect \op__lk$6 \pipe_8_to_10_op__lk$159 + connect \op__rc__rc$7 \pipe_8_to_10_op__rc__rc$160 + connect \op__rc__rc_ok$8 \pipe_8_to_10_op__rc__rc_ok$161 + connect \op__oe__oe$9 \pipe_8_to_10_op__oe__oe$162 + connect \op__oe__oe_ok$10 \pipe_8_to_10_op__oe__oe_ok$163 + connect \op__invert_a$11 \pipe_8_to_10_op__invert_a$164 + connect \op__zero_a$12 \pipe_8_to_10_op__zero_a$165 + connect \op__input_carry$13 \pipe_8_to_10_op__input_carry$166 + connect \op__invert_out$14 \pipe_8_to_10_op__invert_out$167 + connect \op__write_cr__data$15 \pipe_8_to_10_op__write_cr__data$168 + connect \op__write_cr__ok$16 \pipe_8_to_10_op__write_cr__ok$169 + connect \op__output_carry$17 \pipe_8_to_10_op__output_carry$170 + connect \op__is_32bit$18 \pipe_8_to_10_op__is_32bit$171 + connect \op__is_signed$19 \pipe_8_to_10_op__is_signed$172 + connect \op__data_len$20 \pipe_8_to_10_op__data_len$173 + connect \op__insn$21 \pipe_8_to_10_op__insn$174 + connect \ra$22 \pipe_8_to_10_ra$175 + connect \rb$23 \pipe_8_to_10_rb$176 + connect \xer_so$24 \pipe_8_to_10_xer_so$177 + connect \divisor_neg$25 \pipe_8_to_10_divisor_neg$178 + connect \dividend_neg$26 \pipe_8_to_10_dividend_neg$179 + connect \divisor_radicand$27 \pipe_8_to_10_divisor_radicand$180 + connect \operation$28 \pipe_8_to_10_operation$181 + connect \quotient_root$29 \pipe_8_to_10_quotient_root$182 + connect \root_times_radicand$30 \pipe_8_to_10_root_times_radicand$183 + connect \compare_lhs$31 \pipe_8_to_10_compare_lhs$184 + connect \compare_rhs$32 \pipe_8_to_10_compare_rhs$185 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_10_to_12_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_10_to_12_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_10_to_12_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_10_to_12_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_10_to_12_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_10_to_12_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_10_to_12_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_10_to_12_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_10_to_12_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_10_to_12_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_10_to_12_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_10_to_12_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_10_to_12_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_10_to_12_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_10_to_12_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_10_to_12_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_10_to_12_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_10_to_12_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_10_to_12_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_10_to_12_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_10_to_12_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_10_to_12_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_10_to_12_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_10_to_12_muxid$186 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_10_to_12_op__insn_type$187 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_10_to_12_op__fn_unit$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_10_to_12_op__imm_data__imm$189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__imm_data__imm_ok$190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__lk$191 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__rc__rc$192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__rc__rc_ok$193 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__oe__oe$194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__oe__oe_ok$195 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__invert_a$196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__zero_a$197 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_10_to_12_op__input_carry$198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__invert_out$199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_10_to_12_op__write_cr__data$200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__write_cr__ok$201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__output_carry$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__is_32bit$203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_10_to_12_op__is_signed$204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_10_to_12_op__data_len$205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_10_to_12_op__insn$206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_10_to_12_ra$207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_10_to_12_rb$208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_10_to_12_xer_so$209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_10_to_12_divisor_neg$210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_10_to_12_dividend_neg$211 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_10_to_12_divisor_radicand$212 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_10_to_12_operation$213 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_10_to_12_quotient_root$214 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_10_to_12_root_times_radicand$215 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_10_to_12_compare_lhs$216 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_10_to_12_compare_rhs$217 + cell \pipe_10_to_12 \pipe_10_to_12 + connect \rst \rst + connect \clk \clk + connect \p_valid_i \pipe_10_to_12_p_valid_i + connect \p_ready_o \pipe_10_to_12_p_ready_o + connect \muxid \pipe_10_to_12_muxid + connect \op__insn_type \pipe_10_to_12_op__insn_type + connect \op__fn_unit \pipe_10_to_12_op__fn_unit + connect \op__imm_data__imm \pipe_10_to_12_op__imm_data__imm + connect \op__imm_data__imm_ok \pipe_10_to_12_op__imm_data__imm_ok + connect \op__lk \pipe_10_to_12_op__lk + connect \op__rc__rc \pipe_10_to_12_op__rc__rc + connect \op__rc__rc_ok \pipe_10_to_12_op__rc__rc_ok + connect \op__oe__oe \pipe_10_to_12_op__oe__oe + connect \op__oe__oe_ok \pipe_10_to_12_op__oe__oe_ok + connect \op__invert_a \pipe_10_to_12_op__invert_a + connect \op__zero_a \pipe_10_to_12_op__zero_a + connect \op__input_carry \pipe_10_to_12_op__input_carry + connect \op__invert_out \pipe_10_to_12_op__invert_out + connect \op__write_cr__data \pipe_10_to_12_op__write_cr__data + connect \op__write_cr__ok \pipe_10_to_12_op__write_cr__ok + connect \op__output_carry \pipe_10_to_12_op__output_carry + connect \op__is_32bit \pipe_10_to_12_op__is_32bit + connect \op__is_signed \pipe_10_to_12_op__is_signed + connect \op__data_len \pipe_10_to_12_op__data_len + connect \op__insn \pipe_10_to_12_op__insn + connect \ra \pipe_10_to_12_ra + connect \rb \pipe_10_to_12_rb + connect \xer_so \pipe_10_to_12_xer_so + connect \divisor_neg \pipe_10_to_12_divisor_neg + connect \dividend_neg \pipe_10_to_12_dividend_neg + connect \divisor_radicand \pipe_10_to_12_divisor_radicand + connect \operation \pipe_10_to_12_operation + connect \quotient_root \pipe_10_to_12_quotient_root + connect \root_times_radicand \pipe_10_to_12_root_times_radicand + connect \compare_lhs \pipe_10_to_12_compare_lhs + connect \compare_rhs \pipe_10_to_12_compare_rhs + connect \n_valid_o \pipe_10_to_12_n_valid_o + connect \n_ready_i \pipe_10_to_12_n_ready_i + connect \muxid$1 \pipe_10_to_12_muxid$186 + connect \op__insn_type$2 \pipe_10_to_12_op__insn_type$187 + connect \op__fn_unit$3 \pipe_10_to_12_op__fn_unit$188 + connect \op__imm_data__imm$4 \pipe_10_to_12_op__imm_data__imm$189 + connect \op__imm_data__imm_ok$5 \pipe_10_to_12_op__imm_data__imm_ok$190 + connect \op__lk$6 \pipe_10_to_12_op__lk$191 + connect \op__rc__rc$7 \pipe_10_to_12_op__rc__rc$192 + connect \op__rc__rc_ok$8 \pipe_10_to_12_op__rc__rc_ok$193 + connect \op__oe__oe$9 \pipe_10_to_12_op__oe__oe$194 + connect \op__oe__oe_ok$10 \pipe_10_to_12_op__oe__oe_ok$195 + connect \op__invert_a$11 \pipe_10_to_12_op__invert_a$196 + connect \op__zero_a$12 \pipe_10_to_12_op__zero_a$197 + connect \op__input_carry$13 \pipe_10_to_12_op__input_carry$198 + connect \op__invert_out$14 \pipe_10_to_12_op__invert_out$199 + connect \op__write_cr__data$15 \pipe_10_to_12_op__write_cr__data$200 + connect \op__write_cr__ok$16 \pipe_10_to_12_op__write_cr__ok$201 + connect \op__output_carry$17 \pipe_10_to_12_op__output_carry$202 + connect \op__is_32bit$18 \pipe_10_to_12_op__is_32bit$203 + connect \op__is_signed$19 \pipe_10_to_12_op__is_signed$204 + connect \op__data_len$20 \pipe_10_to_12_op__data_len$205 + connect \op__insn$21 \pipe_10_to_12_op__insn$206 + connect \ra$22 \pipe_10_to_12_ra$207 + connect \rb$23 \pipe_10_to_12_rb$208 + connect \xer_so$24 \pipe_10_to_12_xer_so$209 + connect \divisor_neg$25 \pipe_10_to_12_divisor_neg$210 + connect \dividend_neg$26 \pipe_10_to_12_dividend_neg$211 + connect \divisor_radicand$27 \pipe_10_to_12_divisor_radicand$212 + connect \operation$28 \pipe_10_to_12_operation$213 + connect \quotient_root$29 \pipe_10_to_12_quotient_root$214 + connect \root_times_radicand$30 \pipe_10_to_12_root_times_radicand$215 + connect \compare_lhs$31 \pipe_10_to_12_compare_lhs$216 + connect \compare_rhs$32 \pipe_10_to_12_compare_rhs$217 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_12_to_14_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_12_to_14_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_12_to_14_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_12_to_14_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_12_to_14_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_12_to_14_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_12_to_14_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_12_to_14_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_12_to_14_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_12_to_14_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_12_to_14_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_12_to_14_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_12_to_14_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_12_to_14_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_12_to_14_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_12_to_14_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_12_to_14_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_12_to_14_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_12_to_14_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_12_to_14_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_12_to_14_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_12_to_14_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_12_to_14_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_12_to_14_muxid$218 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_12_to_14_op__insn_type$219 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_12_to_14_op__fn_unit$220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_12_to_14_op__imm_data__imm$221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__imm_data__imm_ok$222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__lk$223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__rc__rc$224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__rc__rc_ok$225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__oe__oe$226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__oe__oe_ok$227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__invert_a$228 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__zero_a$229 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_12_to_14_op__input_carry$230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__invert_out$231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_12_to_14_op__write_cr__data$232 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__write_cr__ok$233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__output_carry$234 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__is_32bit$235 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_12_to_14_op__is_signed$236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_12_to_14_op__data_len$237 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_12_to_14_op__insn$238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_12_to_14_ra$239 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_12_to_14_rb$240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_12_to_14_xer_so$241 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_12_to_14_divisor_neg$242 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_12_to_14_dividend_neg$243 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_12_to_14_divisor_radicand$244 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_12_to_14_operation$245 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_12_to_14_quotient_root$246 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_12_to_14_root_times_radicand$247 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_12_to_14_compare_lhs$248 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_12_to_14_compare_rhs$249 + cell \pipe_12_to_14 \pipe_12_to_14 + connect \rst \rst + connect \clk \clk + connect \p_valid_i \pipe_12_to_14_p_valid_i + connect \p_ready_o \pipe_12_to_14_p_ready_o + connect \muxid \pipe_12_to_14_muxid + connect \op__insn_type \pipe_12_to_14_op__insn_type + connect \op__fn_unit \pipe_12_to_14_op__fn_unit + connect \op__imm_data__imm \pipe_12_to_14_op__imm_data__imm + connect \op__imm_data__imm_ok \pipe_12_to_14_op__imm_data__imm_ok + connect \op__lk \pipe_12_to_14_op__lk + connect \op__rc__rc \pipe_12_to_14_op__rc__rc + connect \op__rc__rc_ok \pipe_12_to_14_op__rc__rc_ok + connect \op__oe__oe \pipe_12_to_14_op__oe__oe + connect \op__oe__oe_ok \pipe_12_to_14_op__oe__oe_ok + connect \op__invert_a \pipe_12_to_14_op__invert_a + connect \op__zero_a \pipe_12_to_14_op__zero_a + connect \op__input_carry \pipe_12_to_14_op__input_carry + connect \op__invert_out \pipe_12_to_14_op__invert_out + connect \op__write_cr__data \pipe_12_to_14_op__write_cr__data + connect \op__write_cr__ok \pipe_12_to_14_op__write_cr__ok + connect \op__output_carry \pipe_12_to_14_op__output_carry + connect \op__is_32bit \pipe_12_to_14_op__is_32bit + connect \op__is_signed \pipe_12_to_14_op__is_signed + connect \op__data_len \pipe_12_to_14_op__data_len + connect \op__insn \pipe_12_to_14_op__insn + connect \ra \pipe_12_to_14_ra + connect \rb \pipe_12_to_14_rb + connect \xer_so \pipe_12_to_14_xer_so + connect \divisor_neg \pipe_12_to_14_divisor_neg + connect \dividend_neg \pipe_12_to_14_dividend_neg + connect \divisor_radicand \pipe_12_to_14_divisor_radicand + connect \operation \pipe_12_to_14_operation + connect \quotient_root \pipe_12_to_14_quotient_root + connect \root_times_radicand \pipe_12_to_14_root_times_radicand + connect \compare_lhs \pipe_12_to_14_compare_lhs + connect \compare_rhs \pipe_12_to_14_compare_rhs + connect \n_valid_o \pipe_12_to_14_n_valid_o + connect \n_ready_i \pipe_12_to_14_n_ready_i + connect \muxid$1 \pipe_12_to_14_muxid$218 + connect \op__insn_type$2 \pipe_12_to_14_op__insn_type$219 + connect \op__fn_unit$3 \pipe_12_to_14_op__fn_unit$220 + connect \op__imm_data__imm$4 \pipe_12_to_14_op__imm_data__imm$221 + connect \op__imm_data__imm_ok$5 \pipe_12_to_14_op__imm_data__imm_ok$222 + connect \op__lk$6 \pipe_12_to_14_op__lk$223 + connect \op__rc__rc$7 \pipe_12_to_14_op__rc__rc$224 + connect \op__rc__rc_ok$8 \pipe_12_to_14_op__rc__rc_ok$225 + connect \op__oe__oe$9 \pipe_12_to_14_op__oe__oe$226 + connect \op__oe__oe_ok$10 \pipe_12_to_14_op__oe__oe_ok$227 + connect \op__invert_a$11 \pipe_12_to_14_op__invert_a$228 + connect \op__zero_a$12 \pipe_12_to_14_op__zero_a$229 + connect \op__input_carry$13 \pipe_12_to_14_op__input_carry$230 + connect \op__invert_out$14 \pipe_12_to_14_op__invert_out$231 + connect \op__write_cr__data$15 \pipe_12_to_14_op__write_cr__data$232 + connect \op__write_cr__ok$16 \pipe_12_to_14_op__write_cr__ok$233 + connect \op__output_carry$17 \pipe_12_to_14_op__output_carry$234 + connect \op__is_32bit$18 \pipe_12_to_14_op__is_32bit$235 + connect \op__is_signed$19 \pipe_12_to_14_op__is_signed$236 + connect \op__data_len$20 \pipe_12_to_14_op__data_len$237 + connect \op__insn$21 \pipe_12_to_14_op__insn$238 + connect \ra$22 \pipe_12_to_14_ra$239 + connect \rb$23 \pipe_12_to_14_rb$240 + connect \xer_so$24 \pipe_12_to_14_xer_so$241 + connect \divisor_neg$25 \pipe_12_to_14_divisor_neg$242 + connect \dividend_neg$26 \pipe_12_to_14_dividend_neg$243 + connect \divisor_radicand$27 \pipe_12_to_14_divisor_radicand$244 + connect \operation$28 \pipe_12_to_14_operation$245 + connect \quotient_root$29 \pipe_12_to_14_quotient_root$246 + connect \root_times_radicand$30 \pipe_12_to_14_root_times_radicand$247 + connect \compare_lhs$31 \pipe_12_to_14_compare_lhs$248 + connect \compare_rhs$32 \pipe_12_to_14_compare_rhs$249 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_14_to_16_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_14_to_16_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_14_to_16_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_14_to_16_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_14_to_16_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_14_to_16_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_14_to_16_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_14_to_16_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_14_to_16_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_14_to_16_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_14_to_16_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_14_to_16_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_14_to_16_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_14_to_16_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_14_to_16_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_14_to_16_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_14_to_16_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_14_to_16_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_14_to_16_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_14_to_16_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_14_to_16_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_14_to_16_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_14_to_16_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_14_to_16_muxid$250 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_14_to_16_op__insn_type$251 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_14_to_16_op__fn_unit$252 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_14_to_16_op__imm_data__imm$253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__imm_data__imm_ok$254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__lk$255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__rc__rc$256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__rc__rc_ok$257 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__oe__oe$258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__oe__oe_ok$259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__invert_a$260 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__zero_a$261 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_14_to_16_op__input_carry$262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__invert_out$263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_14_to_16_op__write_cr__data$264 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__write_cr__ok$265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__output_carry$266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__is_32bit$267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_14_to_16_op__is_signed$268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_14_to_16_op__data_len$269 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_14_to_16_op__insn$270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_14_to_16_ra$271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_14_to_16_rb$272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_14_to_16_xer_so$273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_14_to_16_divisor_neg$274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_14_to_16_dividend_neg$275 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_14_to_16_divisor_radicand$276 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_14_to_16_operation$277 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_14_to_16_quotient_root$278 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_14_to_16_root_times_radicand$279 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_14_to_16_compare_lhs$280 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_14_to_16_compare_rhs$281 + cell \pipe_14_to_16 \pipe_14_to_16 + connect \rst \rst + connect \clk \clk + connect \p_valid_i \pipe_14_to_16_p_valid_i + connect \p_ready_o \pipe_14_to_16_p_ready_o + connect \muxid \pipe_14_to_16_muxid + connect \op__insn_type \pipe_14_to_16_op__insn_type + connect \op__fn_unit \pipe_14_to_16_op__fn_unit + connect \op__imm_data__imm \pipe_14_to_16_op__imm_data__imm + connect \op__imm_data__imm_ok \pipe_14_to_16_op__imm_data__imm_ok + connect \op__lk \pipe_14_to_16_op__lk + connect \op__rc__rc \pipe_14_to_16_op__rc__rc + connect \op__rc__rc_ok \pipe_14_to_16_op__rc__rc_ok + connect \op__oe__oe \pipe_14_to_16_op__oe__oe + connect \op__oe__oe_ok \pipe_14_to_16_op__oe__oe_ok + connect \op__invert_a \pipe_14_to_16_op__invert_a + connect \op__zero_a \pipe_14_to_16_op__zero_a + connect \op__input_carry \pipe_14_to_16_op__input_carry + connect \op__invert_out \pipe_14_to_16_op__invert_out + connect \op__write_cr__data \pipe_14_to_16_op__write_cr__data + connect \op__write_cr__ok \pipe_14_to_16_op__write_cr__ok + connect \op__output_carry \pipe_14_to_16_op__output_carry + connect \op__is_32bit \pipe_14_to_16_op__is_32bit + connect \op__is_signed \pipe_14_to_16_op__is_signed + connect \op__data_len \pipe_14_to_16_op__data_len + connect \op__insn \pipe_14_to_16_op__insn + connect \ra \pipe_14_to_16_ra + connect \rb \pipe_14_to_16_rb + connect \xer_so \pipe_14_to_16_xer_so + connect \divisor_neg \pipe_14_to_16_divisor_neg + connect \dividend_neg \pipe_14_to_16_dividend_neg + connect \divisor_radicand \pipe_14_to_16_divisor_radicand + connect \operation \pipe_14_to_16_operation + connect \quotient_root \pipe_14_to_16_quotient_root + connect \root_times_radicand \pipe_14_to_16_root_times_radicand + connect \compare_lhs \pipe_14_to_16_compare_lhs + connect \compare_rhs \pipe_14_to_16_compare_rhs + connect \n_valid_o \pipe_14_to_16_n_valid_o + connect \n_ready_i \pipe_14_to_16_n_ready_i + connect \muxid$1 \pipe_14_to_16_muxid$250 + connect \op__insn_type$2 \pipe_14_to_16_op__insn_type$251 + connect \op__fn_unit$3 \pipe_14_to_16_op__fn_unit$252 + connect \op__imm_data__imm$4 \pipe_14_to_16_op__imm_data__imm$253 + connect \op__imm_data__imm_ok$5 \pipe_14_to_16_op__imm_data__imm_ok$254 + connect \op__lk$6 \pipe_14_to_16_op__lk$255 + connect \op__rc__rc$7 \pipe_14_to_16_op__rc__rc$256 + connect \op__rc__rc_ok$8 \pipe_14_to_16_op__rc__rc_ok$257 + connect \op__oe__oe$9 \pipe_14_to_16_op__oe__oe$258 + connect \op__oe__oe_ok$10 \pipe_14_to_16_op__oe__oe_ok$259 + connect \op__invert_a$11 \pipe_14_to_16_op__invert_a$260 + connect \op__zero_a$12 \pipe_14_to_16_op__zero_a$261 + connect \op__input_carry$13 \pipe_14_to_16_op__input_carry$262 + connect \op__invert_out$14 \pipe_14_to_16_op__invert_out$263 + connect \op__write_cr__data$15 \pipe_14_to_16_op__write_cr__data$264 + connect \op__write_cr__ok$16 \pipe_14_to_16_op__write_cr__ok$265 + connect \op__output_carry$17 \pipe_14_to_16_op__output_carry$266 + connect \op__is_32bit$18 \pipe_14_to_16_op__is_32bit$267 + connect \op__is_signed$19 \pipe_14_to_16_op__is_signed$268 + connect \op__data_len$20 \pipe_14_to_16_op__data_len$269 + connect \op__insn$21 \pipe_14_to_16_op__insn$270 + connect \ra$22 \pipe_14_to_16_ra$271 + connect \rb$23 \pipe_14_to_16_rb$272 + connect \xer_so$24 \pipe_14_to_16_xer_so$273 + connect \divisor_neg$25 \pipe_14_to_16_divisor_neg$274 + connect \dividend_neg$26 \pipe_14_to_16_dividend_neg$275 + connect \divisor_radicand$27 \pipe_14_to_16_divisor_radicand$276 + connect \operation$28 \pipe_14_to_16_operation$277 + connect \quotient_root$29 \pipe_14_to_16_quotient_root$278 + connect \root_times_radicand$30 \pipe_14_to_16_root_times_radicand$279 + connect \compare_lhs$31 \pipe_14_to_16_compare_lhs$280 + connect \compare_rhs$32 \pipe_14_to_16_compare_rhs$281 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_16_to_18_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_16_to_18_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_16_to_18_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_16_to_18_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_16_to_18_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_16_to_18_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_16_to_18_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_16_to_18_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_16_to_18_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_16_to_18_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_16_to_18_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_16_to_18_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_16_to_18_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_16_to_18_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_16_to_18_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_16_to_18_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_16_to_18_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_16_to_18_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_16_to_18_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_16_to_18_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_16_to_18_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_16_to_18_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_16_to_18_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_16_to_18_muxid$282 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_16_to_18_op__insn_type$283 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_16_to_18_op__fn_unit$284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_16_to_18_op__imm_data__imm$285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__imm_data__imm_ok$286 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__lk$287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__rc__rc$288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__rc__rc_ok$289 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__oe__oe$290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__oe__oe_ok$291 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__invert_a$292 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__zero_a$293 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_16_to_18_op__input_carry$294 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__invert_out$295 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_16_to_18_op__write_cr__data$296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__write_cr__ok$297 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__output_carry$298 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__is_32bit$299 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_16_to_18_op__is_signed$300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_16_to_18_op__data_len$301 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_16_to_18_op__insn$302 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_16_to_18_ra$303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_16_to_18_rb$304 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_16_to_18_xer_so$305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_16_to_18_divisor_neg$306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_16_to_18_dividend_neg$307 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_16_to_18_divisor_radicand$308 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_16_to_18_operation$309 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_16_to_18_quotient_root$310 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_16_to_18_root_times_radicand$311 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_16_to_18_compare_lhs$312 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_16_to_18_compare_rhs$313 + cell \pipe_16_to_18 \pipe_16_to_18 + connect \rst \rst + connect \clk \clk + connect \p_valid_i \pipe_16_to_18_p_valid_i + connect \p_ready_o \pipe_16_to_18_p_ready_o + connect \muxid \pipe_16_to_18_muxid + connect \op__insn_type \pipe_16_to_18_op__insn_type + connect \op__fn_unit \pipe_16_to_18_op__fn_unit + connect \op__imm_data__imm \pipe_16_to_18_op__imm_data__imm + connect \op__imm_data__imm_ok \pipe_16_to_18_op__imm_data__imm_ok + connect \op__lk \pipe_16_to_18_op__lk + connect \op__rc__rc \pipe_16_to_18_op__rc__rc + connect \op__rc__rc_ok \pipe_16_to_18_op__rc__rc_ok + connect \op__oe__oe \pipe_16_to_18_op__oe__oe + connect \op__oe__oe_ok \pipe_16_to_18_op__oe__oe_ok + connect \op__invert_a \pipe_16_to_18_op__invert_a + connect \op__zero_a \pipe_16_to_18_op__zero_a + connect \op__input_carry \pipe_16_to_18_op__input_carry + connect \op__invert_out \pipe_16_to_18_op__invert_out + connect \op__write_cr__data \pipe_16_to_18_op__write_cr__data + connect \op__write_cr__ok \pipe_16_to_18_op__write_cr__ok + connect \op__output_carry \pipe_16_to_18_op__output_carry + connect \op__is_32bit \pipe_16_to_18_op__is_32bit + connect \op__is_signed \pipe_16_to_18_op__is_signed + connect \op__data_len \pipe_16_to_18_op__data_len + connect \op__insn \pipe_16_to_18_op__insn + connect \ra \pipe_16_to_18_ra + connect \rb \pipe_16_to_18_rb + connect \xer_so \pipe_16_to_18_xer_so + connect \divisor_neg \pipe_16_to_18_divisor_neg + connect \dividend_neg \pipe_16_to_18_dividend_neg + connect \divisor_radicand \pipe_16_to_18_divisor_radicand + connect \operation \pipe_16_to_18_operation + connect \quotient_root \pipe_16_to_18_quotient_root + connect \root_times_radicand \pipe_16_to_18_root_times_radicand + connect \compare_lhs \pipe_16_to_18_compare_lhs + connect \compare_rhs \pipe_16_to_18_compare_rhs + connect \n_valid_o \pipe_16_to_18_n_valid_o + connect \n_ready_i \pipe_16_to_18_n_ready_i + connect \muxid$1 \pipe_16_to_18_muxid$282 + connect \op__insn_type$2 \pipe_16_to_18_op__insn_type$283 + connect \op__fn_unit$3 \pipe_16_to_18_op__fn_unit$284 + connect \op__imm_data__imm$4 \pipe_16_to_18_op__imm_data__imm$285 + connect \op__imm_data__imm_ok$5 \pipe_16_to_18_op__imm_data__imm_ok$286 + connect \op__lk$6 \pipe_16_to_18_op__lk$287 + connect \op__rc__rc$7 \pipe_16_to_18_op__rc__rc$288 + connect \op__rc__rc_ok$8 \pipe_16_to_18_op__rc__rc_ok$289 + connect \op__oe__oe$9 \pipe_16_to_18_op__oe__oe$290 + connect \op__oe__oe_ok$10 \pipe_16_to_18_op__oe__oe_ok$291 + connect \op__invert_a$11 \pipe_16_to_18_op__invert_a$292 + connect \op__zero_a$12 \pipe_16_to_18_op__zero_a$293 + connect \op__input_carry$13 \pipe_16_to_18_op__input_carry$294 + connect \op__invert_out$14 \pipe_16_to_18_op__invert_out$295 + connect \op__write_cr__data$15 \pipe_16_to_18_op__write_cr__data$296 + connect \op__write_cr__ok$16 \pipe_16_to_18_op__write_cr__ok$297 + connect \op__output_carry$17 \pipe_16_to_18_op__output_carry$298 + connect \op__is_32bit$18 \pipe_16_to_18_op__is_32bit$299 + connect \op__is_signed$19 \pipe_16_to_18_op__is_signed$300 + connect \op__data_len$20 \pipe_16_to_18_op__data_len$301 + connect \op__insn$21 \pipe_16_to_18_op__insn$302 + connect \ra$22 \pipe_16_to_18_ra$303 + connect \rb$23 \pipe_16_to_18_rb$304 + connect \xer_so$24 \pipe_16_to_18_xer_so$305 + connect \divisor_neg$25 \pipe_16_to_18_divisor_neg$306 + connect \dividend_neg$26 \pipe_16_to_18_dividend_neg$307 + connect \divisor_radicand$27 \pipe_16_to_18_divisor_radicand$308 + connect \operation$28 \pipe_16_to_18_operation$309 + connect \quotient_root$29 \pipe_16_to_18_quotient_root$310 + connect \root_times_radicand$30 \pipe_16_to_18_root_times_radicand$311 + connect \compare_lhs$31 \pipe_16_to_18_compare_lhs$312 + connect \compare_rhs$32 \pipe_16_to_18_compare_rhs$313 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_18_to_20_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_18_to_20_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_18_to_20_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_18_to_20_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_18_to_20_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_18_to_20_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_18_to_20_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_18_to_20_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_18_to_20_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_18_to_20_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_18_to_20_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_18_to_20_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_18_to_20_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_18_to_20_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_18_to_20_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_18_to_20_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_18_to_20_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_18_to_20_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_18_to_20_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_18_to_20_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_18_to_20_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_18_to_20_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_18_to_20_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_18_to_20_muxid$314 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_18_to_20_op__insn_type$315 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_18_to_20_op__fn_unit$316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_18_to_20_op__imm_data__imm$317 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__imm_data__imm_ok$318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__lk$319 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__rc__rc$320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__rc__rc_ok$321 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__oe__oe$322 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__oe__oe_ok$323 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__invert_a$324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__zero_a$325 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_18_to_20_op__input_carry$326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__invert_out$327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_18_to_20_op__write_cr__data$328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__write_cr__ok$329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__output_carry$330 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__is_32bit$331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_18_to_20_op__is_signed$332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_18_to_20_op__data_len$333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_18_to_20_op__insn$334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_18_to_20_ra$335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_18_to_20_rb$336 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_18_to_20_xer_so$337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_18_to_20_divisor_neg$338 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_18_to_20_dividend_neg$339 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_18_to_20_divisor_radicand$340 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_18_to_20_operation$341 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_18_to_20_quotient_root$342 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_18_to_20_root_times_radicand$343 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_18_to_20_compare_lhs$344 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_18_to_20_compare_rhs$345 + cell \pipe_18_to_20 \pipe_18_to_20 + connect \rst \rst + connect \clk \clk + connect \p_valid_i \pipe_18_to_20_p_valid_i + connect \p_ready_o \pipe_18_to_20_p_ready_o + connect \muxid \pipe_18_to_20_muxid + connect \op__insn_type \pipe_18_to_20_op__insn_type + connect \op__fn_unit \pipe_18_to_20_op__fn_unit + connect \op__imm_data__imm \pipe_18_to_20_op__imm_data__imm + connect \op__imm_data__imm_ok \pipe_18_to_20_op__imm_data__imm_ok + connect \op__lk \pipe_18_to_20_op__lk + connect \op__rc__rc \pipe_18_to_20_op__rc__rc + connect \op__rc__rc_ok \pipe_18_to_20_op__rc__rc_ok + connect \op__oe__oe \pipe_18_to_20_op__oe__oe + connect \op__oe__oe_ok \pipe_18_to_20_op__oe__oe_ok + connect \op__invert_a \pipe_18_to_20_op__invert_a + connect \op__zero_a \pipe_18_to_20_op__zero_a + connect \op__input_carry \pipe_18_to_20_op__input_carry + connect \op__invert_out \pipe_18_to_20_op__invert_out + connect \op__write_cr__data \pipe_18_to_20_op__write_cr__data + connect \op__write_cr__ok \pipe_18_to_20_op__write_cr__ok + connect \op__output_carry \pipe_18_to_20_op__output_carry + connect \op__is_32bit \pipe_18_to_20_op__is_32bit + connect \op__is_signed \pipe_18_to_20_op__is_signed + connect \op__data_len \pipe_18_to_20_op__data_len + connect \op__insn \pipe_18_to_20_op__insn + connect \ra \pipe_18_to_20_ra + connect \rb \pipe_18_to_20_rb + connect \xer_so \pipe_18_to_20_xer_so + connect \divisor_neg \pipe_18_to_20_divisor_neg + connect \dividend_neg \pipe_18_to_20_dividend_neg + connect \divisor_radicand \pipe_18_to_20_divisor_radicand + connect \operation \pipe_18_to_20_operation + connect \quotient_root \pipe_18_to_20_quotient_root + connect \root_times_radicand \pipe_18_to_20_root_times_radicand + connect \compare_lhs \pipe_18_to_20_compare_lhs + connect \compare_rhs \pipe_18_to_20_compare_rhs + connect \n_valid_o \pipe_18_to_20_n_valid_o + connect \n_ready_i \pipe_18_to_20_n_ready_i + connect \muxid$1 \pipe_18_to_20_muxid$314 + connect \op__insn_type$2 \pipe_18_to_20_op__insn_type$315 + connect \op__fn_unit$3 \pipe_18_to_20_op__fn_unit$316 + connect \op__imm_data__imm$4 \pipe_18_to_20_op__imm_data__imm$317 + connect \op__imm_data__imm_ok$5 \pipe_18_to_20_op__imm_data__imm_ok$318 + connect \op__lk$6 \pipe_18_to_20_op__lk$319 + connect \op__rc__rc$7 \pipe_18_to_20_op__rc__rc$320 + connect \op__rc__rc_ok$8 \pipe_18_to_20_op__rc__rc_ok$321 + connect \op__oe__oe$9 \pipe_18_to_20_op__oe__oe$322 + connect \op__oe__oe_ok$10 \pipe_18_to_20_op__oe__oe_ok$323 + connect \op__invert_a$11 \pipe_18_to_20_op__invert_a$324 + connect \op__zero_a$12 \pipe_18_to_20_op__zero_a$325 + connect \op__input_carry$13 \pipe_18_to_20_op__input_carry$326 + connect \op__invert_out$14 \pipe_18_to_20_op__invert_out$327 + connect \op__write_cr__data$15 \pipe_18_to_20_op__write_cr__data$328 + connect \op__write_cr__ok$16 \pipe_18_to_20_op__write_cr__ok$329 + connect \op__output_carry$17 \pipe_18_to_20_op__output_carry$330 + connect \op__is_32bit$18 \pipe_18_to_20_op__is_32bit$331 + connect \op__is_signed$19 \pipe_18_to_20_op__is_signed$332 + connect \op__data_len$20 \pipe_18_to_20_op__data_len$333 + connect \op__insn$21 \pipe_18_to_20_op__insn$334 + connect \ra$22 \pipe_18_to_20_ra$335 + connect \rb$23 \pipe_18_to_20_rb$336 + connect \xer_so$24 \pipe_18_to_20_xer_so$337 + connect \divisor_neg$25 \pipe_18_to_20_divisor_neg$338 + connect \dividend_neg$26 \pipe_18_to_20_dividend_neg$339 + connect \divisor_radicand$27 \pipe_18_to_20_divisor_radicand$340 + connect \operation$28 \pipe_18_to_20_operation$341 + connect \quotient_root$29 \pipe_18_to_20_quotient_root$342 + connect \root_times_radicand$30 \pipe_18_to_20_root_times_radicand$343 + connect \compare_lhs$31 \pipe_18_to_20_compare_lhs$344 + connect \compare_rhs$32 \pipe_18_to_20_compare_rhs$345 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_20_to_22_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_20_to_22_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_20_to_22_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_20_to_22_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_20_to_22_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_20_to_22_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_20_to_22_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_20_to_22_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_20_to_22_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_20_to_22_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_20_to_22_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_20_to_22_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_20_to_22_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_20_to_22_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_20_to_22_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_20_to_22_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_20_to_22_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_20_to_22_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_20_to_22_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_20_to_22_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_20_to_22_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_20_to_22_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_20_to_22_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_20_to_22_muxid$346 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_20_to_22_op__insn_type$347 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_20_to_22_op__fn_unit$348 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_20_to_22_op__imm_data__imm$349 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__imm_data__imm_ok$350 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__lk$351 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__rc__rc$352 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__rc__rc_ok$353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__oe__oe$354 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__oe__oe_ok$355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__invert_a$356 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__zero_a$357 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_20_to_22_op__input_carry$358 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__invert_out$359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_20_to_22_op__write_cr__data$360 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__write_cr__ok$361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__output_carry$362 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__is_32bit$363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_20_to_22_op__is_signed$364 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_20_to_22_op__data_len$365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_20_to_22_op__insn$366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_20_to_22_ra$367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_20_to_22_rb$368 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_20_to_22_xer_so$369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_20_to_22_divisor_neg$370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_20_to_22_dividend_neg$371 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_20_to_22_divisor_radicand$372 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_20_to_22_operation$373 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_20_to_22_quotient_root$374 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_20_to_22_root_times_radicand$375 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_20_to_22_compare_lhs$376 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_20_to_22_compare_rhs$377 + cell \pipe_20_to_22 \pipe_20_to_22 + connect \rst \rst + connect \clk \clk + connect \p_valid_i \pipe_20_to_22_p_valid_i + connect \p_ready_o \pipe_20_to_22_p_ready_o + connect \muxid \pipe_20_to_22_muxid + connect \op__insn_type \pipe_20_to_22_op__insn_type + connect \op__fn_unit \pipe_20_to_22_op__fn_unit + connect \op__imm_data__imm \pipe_20_to_22_op__imm_data__imm + connect \op__imm_data__imm_ok \pipe_20_to_22_op__imm_data__imm_ok + connect \op__lk \pipe_20_to_22_op__lk + connect \op__rc__rc \pipe_20_to_22_op__rc__rc + connect \op__rc__rc_ok \pipe_20_to_22_op__rc__rc_ok + connect \op__oe__oe \pipe_20_to_22_op__oe__oe + connect \op__oe__oe_ok \pipe_20_to_22_op__oe__oe_ok + connect \op__invert_a \pipe_20_to_22_op__invert_a + connect \op__zero_a \pipe_20_to_22_op__zero_a + connect \op__input_carry \pipe_20_to_22_op__input_carry + connect \op__invert_out \pipe_20_to_22_op__invert_out + connect \op__write_cr__data \pipe_20_to_22_op__write_cr__data + connect \op__write_cr__ok \pipe_20_to_22_op__write_cr__ok + connect \op__output_carry \pipe_20_to_22_op__output_carry + connect \op__is_32bit \pipe_20_to_22_op__is_32bit + connect \op__is_signed \pipe_20_to_22_op__is_signed + connect \op__data_len \pipe_20_to_22_op__data_len + connect \op__insn \pipe_20_to_22_op__insn + connect \ra \pipe_20_to_22_ra + connect \rb \pipe_20_to_22_rb + connect \xer_so \pipe_20_to_22_xer_so + connect \divisor_neg \pipe_20_to_22_divisor_neg + connect \dividend_neg \pipe_20_to_22_dividend_neg + connect \divisor_radicand \pipe_20_to_22_divisor_radicand + connect \operation \pipe_20_to_22_operation + connect \quotient_root \pipe_20_to_22_quotient_root + connect \root_times_radicand \pipe_20_to_22_root_times_radicand + connect \compare_lhs \pipe_20_to_22_compare_lhs + connect \compare_rhs \pipe_20_to_22_compare_rhs + connect \n_valid_o \pipe_20_to_22_n_valid_o + connect \n_ready_i \pipe_20_to_22_n_ready_i + connect \muxid$1 \pipe_20_to_22_muxid$346 + connect \op__insn_type$2 \pipe_20_to_22_op__insn_type$347 + connect \op__fn_unit$3 \pipe_20_to_22_op__fn_unit$348 + connect \op__imm_data__imm$4 \pipe_20_to_22_op__imm_data__imm$349 + connect \op__imm_data__imm_ok$5 \pipe_20_to_22_op__imm_data__imm_ok$350 + connect \op__lk$6 \pipe_20_to_22_op__lk$351 + connect \op__rc__rc$7 \pipe_20_to_22_op__rc__rc$352 + connect \op__rc__rc_ok$8 \pipe_20_to_22_op__rc__rc_ok$353 + connect \op__oe__oe$9 \pipe_20_to_22_op__oe__oe$354 + connect \op__oe__oe_ok$10 \pipe_20_to_22_op__oe__oe_ok$355 + connect \op__invert_a$11 \pipe_20_to_22_op__invert_a$356 + connect \op__zero_a$12 \pipe_20_to_22_op__zero_a$357 + connect \op__input_carry$13 \pipe_20_to_22_op__input_carry$358 + connect \op__invert_out$14 \pipe_20_to_22_op__invert_out$359 + connect \op__write_cr__data$15 \pipe_20_to_22_op__write_cr__data$360 + connect \op__write_cr__ok$16 \pipe_20_to_22_op__write_cr__ok$361 + connect \op__output_carry$17 \pipe_20_to_22_op__output_carry$362 + connect \op__is_32bit$18 \pipe_20_to_22_op__is_32bit$363 + connect \op__is_signed$19 \pipe_20_to_22_op__is_signed$364 + connect \op__data_len$20 \pipe_20_to_22_op__data_len$365 + connect \op__insn$21 \pipe_20_to_22_op__insn$366 + connect \ra$22 \pipe_20_to_22_ra$367 + connect \rb$23 \pipe_20_to_22_rb$368 + connect \xer_so$24 \pipe_20_to_22_xer_so$369 + connect \divisor_neg$25 \pipe_20_to_22_divisor_neg$370 + connect \dividend_neg$26 \pipe_20_to_22_dividend_neg$371 + connect \divisor_radicand$27 \pipe_20_to_22_divisor_radicand$372 + connect \operation$28 \pipe_20_to_22_operation$373 + connect \quotient_root$29 \pipe_20_to_22_quotient_root$374 + connect \root_times_radicand$30 \pipe_20_to_22_root_times_radicand$375 + connect \compare_lhs$31 \pipe_20_to_22_compare_lhs$376 + connect \compare_rhs$32 \pipe_20_to_22_compare_rhs$377 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_end_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_end_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_end_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_end_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_end_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_end_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_end_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_end_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_end_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_end_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_end_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_end_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_end_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:34" + wire width 1 \pipe_end_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:35" + wire width 1 \pipe_end_dividend_neg + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:148" + wire width 64 \pipe_end_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:149" + wire width 2 \pipe_end_operation + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:150" + wire width 64 \pipe_end_quotient_root + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:151" + wire width 128 \pipe_end_root_times_radicand + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:152" + wire width 192 \pipe_end_compare_lhs + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/div_rem_sqrt_rsqrt/core.py:153" + wire width 192 \pipe_end_compare_rhs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_end_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_end_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_end_muxid$378 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \pipe_end_op__insn_type$379 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \pipe_end_op__fn_unit$380 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \pipe_end_op__imm_data__imm$381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__imm_data__imm_ok$382 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__lk$383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__rc__rc$384 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__rc__rc_ok$385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__oe__oe$386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__oe__oe_ok$387 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__invert_a$388 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__zero_a$389 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \pipe_end_op__input_carry$390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__invert_out$391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \pipe_end_op__write_cr__data$392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__write_cr__ok$393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__output_carry$394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__is_32bit$395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \pipe_end_op__is_signed$396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \pipe_end_op__data_len$397 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \pipe_end_op__insn$398 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \pipe_end_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \pipe_end_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 4 \pipe_end_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \pipe_end_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \pipe_end_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \pipe_end_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \pipe_end_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \pipe_end_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \pipe_end_xer_so$399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \pipe_end_xer_so_ok + cell \pipe_end \pipe_end + connect \rst \rst + connect \clk \clk + connect \p_valid_i \pipe_end_p_valid_i + connect \p_ready_o \pipe_end_p_ready_o + connect \muxid \pipe_end_muxid + connect \op__insn_type \pipe_end_op__insn_type + connect \op__fn_unit \pipe_end_op__fn_unit + connect \op__imm_data__imm \pipe_end_op__imm_data__imm + connect \op__imm_data__imm_ok \pipe_end_op__imm_data__imm_ok + connect \op__lk \pipe_end_op__lk + connect \op__rc__rc \pipe_end_op__rc__rc + connect \op__rc__rc_ok \pipe_end_op__rc__rc_ok + connect \op__oe__oe \pipe_end_op__oe__oe + connect \op__oe__oe_ok \pipe_end_op__oe__oe_ok + connect \op__invert_a \pipe_end_op__invert_a + connect \op__zero_a \pipe_end_op__zero_a + connect \op__input_carry \pipe_end_op__input_carry + connect \op__invert_out \pipe_end_op__invert_out + connect \op__write_cr__data \pipe_end_op__write_cr__data + connect \op__write_cr__ok \pipe_end_op__write_cr__ok + connect \op__output_carry \pipe_end_op__output_carry + connect \op__is_32bit \pipe_end_op__is_32bit + connect \op__is_signed \pipe_end_op__is_signed + connect \op__data_len \pipe_end_op__data_len + connect \op__insn \pipe_end_op__insn + connect \ra \pipe_end_ra + connect \rb \pipe_end_rb + connect \xer_so \pipe_end_xer_so + connect \divisor_neg \pipe_end_divisor_neg + connect \dividend_neg \pipe_end_dividend_neg + connect \divisor_radicand \pipe_end_divisor_radicand + connect \operation \pipe_end_operation + connect \quotient_root \pipe_end_quotient_root + connect \root_times_radicand \pipe_end_root_times_radicand + connect \compare_lhs \pipe_end_compare_lhs + connect \compare_rhs \pipe_end_compare_rhs + connect \n_valid_o \pipe_end_n_valid_o + connect \n_ready_i \pipe_end_n_ready_i + connect \muxid$1 \pipe_end_muxid$378 + connect \op__insn_type$2 \pipe_end_op__insn_type$379 + connect \op__fn_unit$3 \pipe_end_op__fn_unit$380 + connect \op__imm_data__imm$4 \pipe_end_op__imm_data__imm$381 + connect \op__imm_data__imm_ok$5 \pipe_end_op__imm_data__imm_ok$382 + connect \op__lk$6 \pipe_end_op__lk$383 + connect \op__rc__rc$7 \pipe_end_op__rc__rc$384 + connect \op__rc__rc_ok$8 \pipe_end_op__rc__rc_ok$385 + connect \op__oe__oe$9 \pipe_end_op__oe__oe$386 + connect \op__oe__oe_ok$10 \pipe_end_op__oe__oe_ok$387 + connect \op__invert_a$11 \pipe_end_op__invert_a$388 + connect \op__zero_a$12 \pipe_end_op__zero_a$389 + connect \op__input_carry$13 \pipe_end_op__input_carry$390 + connect \op__invert_out$14 \pipe_end_op__invert_out$391 + connect \op__write_cr__data$15 \pipe_end_op__write_cr__data$392 + connect \op__write_cr__ok$16 \pipe_end_op__write_cr__ok$393 + connect \op__output_carry$17 \pipe_end_op__output_carry$394 + connect \op__is_32bit$18 \pipe_end_op__is_32bit$395 + connect \op__is_signed$19 \pipe_end_op__is_signed$396 + connect \op__data_len$20 \pipe_end_op__data_len$397 + connect \op__insn$21 \pipe_end_op__insn$398 + connect \o \pipe_end_o + connect \o_ok \pipe_end_o_ok + connect \cr_a \pipe_end_cr_a + connect \cr_a_ok \pipe_end_cr_a_ok + connect \xer_ca \pipe_end_xer_ca + connect \xer_ca_ok \pipe_end_xer_ca_ok + connect \xer_ov \pipe_end_xer_ov + connect \xer_ov_ok \pipe_end_xer_ov_ok + connect \xer_so$22 \pipe_end_xer_so$399 + connect \xer_so_ok \pipe_end_xer_so_ok + end + process $group_0 + assign \pipe_0_to_2_p_valid_i 1'0 + assign \pipe_0_to_2_p_valid_i \pipe_start_n_valid_o + sync init + end + process $group_1 + assign \pipe_start_n_ready_i 1'0 + assign \pipe_start_n_ready_i \pipe_0_to_2_p_ready_o + sync init + end + process $group_2 + assign \pipe_0_to_2_muxid 2'00 + assign \pipe_0_to_2_muxid \pipe_start_muxid + sync init + end + process $group_3 + assign \pipe_0_to_2_op__insn_type 7'0000000 + assign \pipe_0_to_2_op__fn_unit 10'0000000000 + assign \pipe_0_to_2_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_0_to_2_op__imm_data__imm_ok 1'0 + assign \pipe_0_to_2_op__lk 1'0 + assign \pipe_0_to_2_op__rc__rc 1'0 + assign \pipe_0_to_2_op__rc__rc_ok 1'0 + assign \pipe_0_to_2_op__oe__oe 1'0 + assign \pipe_0_to_2_op__oe__oe_ok 1'0 + assign \pipe_0_to_2_op__invert_a 1'0 + assign \pipe_0_to_2_op__zero_a 1'0 + assign \pipe_0_to_2_op__input_carry 2'00 + assign \pipe_0_to_2_op__invert_out 1'0 + assign \pipe_0_to_2_op__write_cr__data 3'000 + assign \pipe_0_to_2_op__write_cr__ok 1'0 + assign \pipe_0_to_2_op__output_carry 1'0 + assign \pipe_0_to_2_op__is_32bit 1'0 + assign \pipe_0_to_2_op__is_signed 1'0 + assign \pipe_0_to_2_op__data_len 4'0000 + assign \pipe_0_to_2_op__insn 32'00000000000000000000000000000000 + assign { \pipe_0_to_2_op__insn \pipe_0_to_2_op__data_len \pipe_0_to_2_op__is_signed \pipe_0_to_2_op__is_32bit \pipe_0_to_2_op__output_carry { \pipe_0_to_2_op__write_cr__ok \pipe_0_to_2_op__write_cr__data } \pipe_0_to_2_op__invert_out \pipe_0_to_2_op__input_carry \pipe_0_to_2_op__zero_a \pipe_0_to_2_op__invert_a { \pipe_0_to_2_op__oe__oe_ok \pipe_0_to_2_op__oe__oe } { \pipe_0_to_2_op__rc__rc_ok \pipe_0_to_2_op__rc__rc } \pipe_0_to_2_op__lk { \pipe_0_to_2_op__imm_data__imm_ok \pipe_0_to_2_op__imm_data__imm } \pipe_0_to_2_op__fn_unit \pipe_0_to_2_op__insn_type } { \pipe_start_op__insn \pipe_start_op__data_len \pipe_start_op__is_signed \pipe_start_op__is_32bit \pipe_start_op__output_carry { \pipe_start_op__write_cr__ok \pipe_start_op__write_cr__data } \pipe_start_op__invert_out \pipe_start_op__input_carry \pipe_start_op__zero_a \pipe_start_op__invert_a { \pipe_start_op__oe__oe_ok \pipe_start_op__oe__oe } { \pipe_start_op__rc__rc_ok \pipe_start_op__rc__rc } \pipe_start_op__lk { \pipe_start_op__imm_data__imm_ok \pipe_start_op__imm_data__imm } \pipe_start_op__fn_unit \pipe_start_op__insn_type } + sync init + end + process $group_23 + assign \pipe_0_to_2_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_0_to_2_ra \pipe_start_ra + sync init + end + process $group_24 + assign \pipe_0_to_2_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_0_to_2_rb \pipe_start_rb + sync init + end + process $group_25 + assign \pipe_0_to_2_xer_so 1'0 + assign \pipe_0_to_2_xer_so \pipe_start_xer_so + sync init + end + process $group_26 + assign \pipe_0_to_2_divisor_neg 1'0 + assign \pipe_0_to_2_divisor_neg \pipe_start_divisor_neg + sync init + end + process $group_27 + assign \pipe_0_to_2_dividend_neg 1'0 + assign \pipe_0_to_2_dividend_neg \pipe_start_dividend_neg + sync init + end + process $group_28 + assign \pipe_0_to_2_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_0_to_2_divisor_radicand \pipe_start_divisor_radicand + sync init + end + process $group_29 + assign \pipe_0_to_2_operation 2'00 + assign \pipe_0_to_2_operation \pipe_start_operation + sync init + end + process $group_30 + assign \pipe_0_to_2_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_0_to_2_quotient_root \pipe_start_quotient_root + sync init + end + process $group_31 + assign \pipe_0_to_2_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_0_to_2_root_times_radicand \pipe_start_root_times_radicand + sync init + end + process $group_32 + assign \pipe_0_to_2_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_0_to_2_compare_lhs \pipe_start_compare_lhs + sync init + end + process $group_33 + assign \pipe_0_to_2_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_0_to_2_compare_rhs \pipe_start_compare_rhs + sync init + end + process $group_34 + assign \pipe_2_to_4_p_valid_i 1'0 + assign \pipe_2_to_4_p_valid_i \pipe_0_to_2_n_valid_o + sync init + end + process $group_35 + assign \pipe_0_to_2_n_ready_i 1'0 + assign \pipe_0_to_2_n_ready_i \pipe_2_to_4_p_ready_o + sync init + end + process $group_36 + assign \pipe_2_to_4_muxid 2'00 + assign \pipe_2_to_4_muxid \pipe_0_to_2_muxid$26 + sync init + end + process $group_37 + assign \pipe_2_to_4_op__insn_type 7'0000000 + assign \pipe_2_to_4_op__fn_unit 10'0000000000 + assign \pipe_2_to_4_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_2_to_4_op__imm_data__imm_ok 1'0 + assign \pipe_2_to_4_op__lk 1'0 + assign \pipe_2_to_4_op__rc__rc 1'0 + assign \pipe_2_to_4_op__rc__rc_ok 1'0 + assign \pipe_2_to_4_op__oe__oe 1'0 + assign \pipe_2_to_4_op__oe__oe_ok 1'0 + assign \pipe_2_to_4_op__invert_a 1'0 + assign \pipe_2_to_4_op__zero_a 1'0 + assign \pipe_2_to_4_op__input_carry 2'00 + assign \pipe_2_to_4_op__invert_out 1'0 + assign \pipe_2_to_4_op__write_cr__data 3'000 + assign \pipe_2_to_4_op__write_cr__ok 1'0 + assign \pipe_2_to_4_op__output_carry 1'0 + assign \pipe_2_to_4_op__is_32bit 1'0 + assign \pipe_2_to_4_op__is_signed 1'0 + assign \pipe_2_to_4_op__data_len 4'0000 + assign \pipe_2_to_4_op__insn 32'00000000000000000000000000000000 + assign { \pipe_2_to_4_op__insn \pipe_2_to_4_op__data_len \pipe_2_to_4_op__is_signed \pipe_2_to_4_op__is_32bit \pipe_2_to_4_op__output_carry { \pipe_2_to_4_op__write_cr__ok \pipe_2_to_4_op__write_cr__data } \pipe_2_to_4_op__invert_out \pipe_2_to_4_op__input_carry \pipe_2_to_4_op__zero_a \pipe_2_to_4_op__invert_a { \pipe_2_to_4_op__oe__oe_ok \pipe_2_to_4_op__oe__oe } { \pipe_2_to_4_op__rc__rc_ok \pipe_2_to_4_op__rc__rc } \pipe_2_to_4_op__lk { \pipe_2_to_4_op__imm_data__imm_ok \pipe_2_to_4_op__imm_data__imm } \pipe_2_to_4_op__fn_unit \pipe_2_to_4_op__insn_type } { \pipe_0_to_2_op__insn$46 \pipe_0_to_2_op__data_len$45 \pipe_0_to_2_op__is_signed$44 \pipe_0_to_2_op__is_32bit$43 \pipe_0_to_2_op__output_carry$42 { \pipe_0_to_2_op__write_cr__ok$41 \pipe_0_to_2_op__write_cr__data$40 } \pipe_0_to_2_op__invert_out$39 \pipe_0_to_2_op__input_carry$38 \pipe_0_to_2_op__zero_a$37 \pipe_0_to_2_op__invert_a$36 { \pipe_0_to_2_op__oe__oe_ok$35 \pipe_0_to_2_op__oe__oe$34 } { \pipe_0_to_2_op__rc__rc_ok$33 \pipe_0_to_2_op__rc__rc$32 } \pipe_0_to_2_op__lk$31 { \pipe_0_to_2_op__imm_data__imm_ok$30 \pipe_0_to_2_op__imm_data__imm$29 } \pipe_0_to_2_op__fn_unit$28 \pipe_0_to_2_op__insn_type$27 } + sync init + end + process $group_57 + assign \pipe_2_to_4_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_2_to_4_ra \pipe_0_to_2_ra$47 + sync init + end + process $group_58 + assign \pipe_2_to_4_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_2_to_4_rb \pipe_0_to_2_rb$48 + sync init + end + process $group_59 + assign \pipe_2_to_4_xer_so 1'0 + assign \pipe_2_to_4_xer_so \pipe_0_to_2_xer_so$49 + sync init + end + process $group_60 + assign \pipe_2_to_4_divisor_neg 1'0 + assign \pipe_2_to_4_divisor_neg \pipe_0_to_2_divisor_neg$50 + sync init + end + process $group_61 + assign \pipe_2_to_4_dividend_neg 1'0 + assign \pipe_2_to_4_dividend_neg \pipe_0_to_2_dividend_neg$51 + sync init + end + process $group_62 + assign \pipe_2_to_4_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_2_to_4_divisor_radicand \pipe_0_to_2_divisor_radicand$52 + sync init + end + process $group_63 + assign \pipe_2_to_4_operation 2'00 + assign \pipe_2_to_4_operation \pipe_0_to_2_operation$53 + sync init + end + process $group_64 + assign \pipe_2_to_4_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_2_to_4_quotient_root \pipe_0_to_2_quotient_root$54 + sync init + end + process $group_65 + assign \pipe_2_to_4_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_2_to_4_root_times_radicand \pipe_0_to_2_root_times_radicand$55 + sync init + end + process $group_66 + assign \pipe_2_to_4_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_2_to_4_compare_lhs \pipe_0_to_2_compare_lhs$56 + sync init + end + process $group_67 + assign \pipe_2_to_4_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_2_to_4_compare_rhs \pipe_0_to_2_compare_rhs$57 + sync init + end + process $group_68 + assign \pipe_4_to_6_p_valid_i 1'0 + assign \pipe_4_to_6_p_valid_i \pipe_2_to_4_n_valid_o + sync init + end + process $group_69 + assign \pipe_2_to_4_n_ready_i 1'0 + assign \pipe_2_to_4_n_ready_i \pipe_4_to_6_p_ready_o + sync init + end + process $group_70 + assign \pipe_4_to_6_muxid 2'00 + assign \pipe_4_to_6_muxid \pipe_2_to_4_muxid$58 + sync init + end + process $group_71 + assign \pipe_4_to_6_op__insn_type 7'0000000 + assign \pipe_4_to_6_op__fn_unit 10'0000000000 + assign \pipe_4_to_6_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_4_to_6_op__imm_data__imm_ok 1'0 + assign \pipe_4_to_6_op__lk 1'0 + assign \pipe_4_to_6_op__rc__rc 1'0 + assign \pipe_4_to_6_op__rc__rc_ok 1'0 + assign \pipe_4_to_6_op__oe__oe 1'0 + assign \pipe_4_to_6_op__oe__oe_ok 1'0 + assign \pipe_4_to_6_op__invert_a 1'0 + assign \pipe_4_to_6_op__zero_a 1'0 + assign \pipe_4_to_6_op__input_carry 2'00 + assign \pipe_4_to_6_op__invert_out 1'0 + assign \pipe_4_to_6_op__write_cr__data 3'000 + assign \pipe_4_to_6_op__write_cr__ok 1'0 + assign \pipe_4_to_6_op__output_carry 1'0 + assign \pipe_4_to_6_op__is_32bit 1'0 + assign \pipe_4_to_6_op__is_signed 1'0 + assign \pipe_4_to_6_op__data_len 4'0000 + assign \pipe_4_to_6_op__insn 32'00000000000000000000000000000000 + assign { \pipe_4_to_6_op__insn \pipe_4_to_6_op__data_len \pipe_4_to_6_op__is_signed \pipe_4_to_6_op__is_32bit \pipe_4_to_6_op__output_carry { \pipe_4_to_6_op__write_cr__ok \pipe_4_to_6_op__write_cr__data } \pipe_4_to_6_op__invert_out \pipe_4_to_6_op__input_carry \pipe_4_to_6_op__zero_a \pipe_4_to_6_op__invert_a { \pipe_4_to_6_op__oe__oe_ok \pipe_4_to_6_op__oe__oe } { \pipe_4_to_6_op__rc__rc_ok \pipe_4_to_6_op__rc__rc } \pipe_4_to_6_op__lk { \pipe_4_to_6_op__imm_data__imm_ok \pipe_4_to_6_op__imm_data__imm } \pipe_4_to_6_op__fn_unit \pipe_4_to_6_op__insn_type } { \pipe_2_to_4_op__insn$78 \pipe_2_to_4_op__data_len$77 \pipe_2_to_4_op__is_signed$76 \pipe_2_to_4_op__is_32bit$75 \pipe_2_to_4_op__output_carry$74 { \pipe_2_to_4_op__write_cr__ok$73 \pipe_2_to_4_op__write_cr__data$72 } \pipe_2_to_4_op__invert_out$71 \pipe_2_to_4_op__input_carry$70 \pipe_2_to_4_op__zero_a$69 \pipe_2_to_4_op__invert_a$68 { \pipe_2_to_4_op__oe__oe_ok$67 \pipe_2_to_4_op__oe__oe$66 } { \pipe_2_to_4_op__rc__rc_ok$65 \pipe_2_to_4_op__rc__rc$64 } \pipe_2_to_4_op__lk$63 { \pipe_2_to_4_op__imm_data__imm_ok$62 \pipe_2_to_4_op__imm_data__imm$61 } \pipe_2_to_4_op__fn_unit$60 \pipe_2_to_4_op__insn_type$59 } + sync init + end + process $group_91 + assign \pipe_4_to_6_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_4_to_6_ra \pipe_2_to_4_ra$79 + sync init + end + process $group_92 + assign \pipe_4_to_6_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_4_to_6_rb \pipe_2_to_4_rb$80 + sync init + end + process $group_93 + assign \pipe_4_to_6_xer_so 1'0 + assign \pipe_4_to_6_xer_so \pipe_2_to_4_xer_so$81 + sync init + end + process $group_94 + assign \pipe_4_to_6_divisor_neg 1'0 + assign \pipe_4_to_6_divisor_neg \pipe_2_to_4_divisor_neg$82 + sync init + end + process $group_95 + assign \pipe_4_to_6_dividend_neg 1'0 + assign \pipe_4_to_6_dividend_neg \pipe_2_to_4_dividend_neg$83 + sync init + end + process $group_96 + assign \pipe_4_to_6_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_4_to_6_divisor_radicand \pipe_2_to_4_divisor_radicand$84 + sync init + end + process $group_97 + assign \pipe_4_to_6_operation 2'00 + assign \pipe_4_to_6_operation \pipe_2_to_4_operation$85 + sync init + end + process $group_98 + assign \pipe_4_to_6_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_4_to_6_quotient_root \pipe_2_to_4_quotient_root$86 + sync init + end + process $group_99 + assign \pipe_4_to_6_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_4_to_6_root_times_radicand \pipe_2_to_4_root_times_radicand$87 + sync init + end + process $group_100 + assign \pipe_4_to_6_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_4_to_6_compare_lhs \pipe_2_to_4_compare_lhs$88 + sync init + end + process $group_101 + assign \pipe_4_to_6_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_4_to_6_compare_rhs \pipe_2_to_4_compare_rhs$89 + sync init + end + process $group_102 + assign \pipe_6_to_8_p_valid_i 1'0 + assign \pipe_6_to_8_p_valid_i \pipe_4_to_6_n_valid_o + sync init + end + process $group_103 + assign \pipe_4_to_6_n_ready_i 1'0 + assign \pipe_4_to_6_n_ready_i \pipe_6_to_8_p_ready_o + sync init + end + process $group_104 + assign \pipe_6_to_8_muxid 2'00 + assign \pipe_6_to_8_muxid \pipe_4_to_6_muxid$90 + sync init + end + process $group_105 + assign \pipe_6_to_8_op__insn_type 7'0000000 + assign \pipe_6_to_8_op__fn_unit 10'0000000000 + assign \pipe_6_to_8_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_6_to_8_op__imm_data__imm_ok 1'0 + assign \pipe_6_to_8_op__lk 1'0 + assign \pipe_6_to_8_op__rc__rc 1'0 + assign \pipe_6_to_8_op__rc__rc_ok 1'0 + assign \pipe_6_to_8_op__oe__oe 1'0 + assign \pipe_6_to_8_op__oe__oe_ok 1'0 + assign \pipe_6_to_8_op__invert_a 1'0 + assign \pipe_6_to_8_op__zero_a 1'0 + assign \pipe_6_to_8_op__input_carry 2'00 + assign \pipe_6_to_8_op__invert_out 1'0 + assign \pipe_6_to_8_op__write_cr__data 3'000 + assign \pipe_6_to_8_op__write_cr__ok 1'0 + assign \pipe_6_to_8_op__output_carry 1'0 + assign \pipe_6_to_8_op__is_32bit 1'0 + assign \pipe_6_to_8_op__is_signed 1'0 + assign \pipe_6_to_8_op__data_len 4'0000 + assign \pipe_6_to_8_op__insn 32'00000000000000000000000000000000 + assign { \pipe_6_to_8_op__insn \pipe_6_to_8_op__data_len \pipe_6_to_8_op__is_signed \pipe_6_to_8_op__is_32bit \pipe_6_to_8_op__output_carry { \pipe_6_to_8_op__write_cr__ok \pipe_6_to_8_op__write_cr__data } \pipe_6_to_8_op__invert_out \pipe_6_to_8_op__input_carry \pipe_6_to_8_op__zero_a \pipe_6_to_8_op__invert_a { \pipe_6_to_8_op__oe__oe_ok \pipe_6_to_8_op__oe__oe } { \pipe_6_to_8_op__rc__rc_ok \pipe_6_to_8_op__rc__rc } \pipe_6_to_8_op__lk { \pipe_6_to_8_op__imm_data__imm_ok \pipe_6_to_8_op__imm_data__imm } \pipe_6_to_8_op__fn_unit \pipe_6_to_8_op__insn_type } { \pipe_4_to_6_op__insn$110 \pipe_4_to_6_op__data_len$109 \pipe_4_to_6_op__is_signed$108 \pipe_4_to_6_op__is_32bit$107 \pipe_4_to_6_op__output_carry$106 { \pipe_4_to_6_op__write_cr__ok$105 \pipe_4_to_6_op__write_cr__data$104 } \pipe_4_to_6_op__invert_out$103 \pipe_4_to_6_op__input_carry$102 \pipe_4_to_6_op__zero_a$101 \pipe_4_to_6_op__invert_a$100 { \pipe_4_to_6_op__oe__oe_ok$99 \pipe_4_to_6_op__oe__oe$98 } { \pipe_4_to_6_op__rc__rc_ok$97 \pipe_4_to_6_op__rc__rc$96 } \pipe_4_to_6_op__lk$95 { \pipe_4_to_6_op__imm_data__imm_ok$94 \pipe_4_to_6_op__imm_data__imm$93 } \pipe_4_to_6_op__fn_unit$92 \pipe_4_to_6_op__insn_type$91 } + sync init + end + process $group_125 + assign \pipe_6_to_8_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_6_to_8_ra \pipe_4_to_6_ra$111 + sync init + end + process $group_126 + assign \pipe_6_to_8_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_6_to_8_rb \pipe_4_to_6_rb$112 + sync init + end + process $group_127 + assign \pipe_6_to_8_xer_so 1'0 + assign \pipe_6_to_8_xer_so \pipe_4_to_6_xer_so$113 + sync init + end + process $group_128 + assign \pipe_6_to_8_divisor_neg 1'0 + assign \pipe_6_to_8_divisor_neg \pipe_4_to_6_divisor_neg$114 + sync init + end + process $group_129 + assign \pipe_6_to_8_dividend_neg 1'0 + assign \pipe_6_to_8_dividend_neg \pipe_4_to_6_dividend_neg$115 + sync init + end + process $group_130 + assign \pipe_6_to_8_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_6_to_8_divisor_radicand \pipe_4_to_6_divisor_radicand$116 + sync init + end + process $group_131 + assign \pipe_6_to_8_operation 2'00 + assign \pipe_6_to_8_operation \pipe_4_to_6_operation$117 + sync init + end + process $group_132 + assign \pipe_6_to_8_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_6_to_8_quotient_root \pipe_4_to_6_quotient_root$118 + sync init + end + process $group_133 + assign \pipe_6_to_8_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_6_to_8_root_times_radicand \pipe_4_to_6_root_times_radicand$119 + sync init + end + process $group_134 + assign \pipe_6_to_8_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_6_to_8_compare_lhs \pipe_4_to_6_compare_lhs$120 + sync init + end + process $group_135 + assign \pipe_6_to_8_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_6_to_8_compare_rhs \pipe_4_to_6_compare_rhs$121 + sync init + end + process $group_136 + assign \pipe_8_to_10_p_valid_i 1'0 + assign \pipe_8_to_10_p_valid_i \pipe_6_to_8_n_valid_o + sync init + end + process $group_137 + assign \pipe_6_to_8_n_ready_i 1'0 + assign \pipe_6_to_8_n_ready_i \pipe_8_to_10_p_ready_o + sync init + end + process $group_138 + assign \pipe_8_to_10_muxid 2'00 + assign \pipe_8_to_10_muxid \pipe_6_to_8_muxid$122 + sync init + end + process $group_139 + assign \pipe_8_to_10_op__insn_type 7'0000000 + assign \pipe_8_to_10_op__fn_unit 10'0000000000 + assign \pipe_8_to_10_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_8_to_10_op__imm_data__imm_ok 1'0 + assign \pipe_8_to_10_op__lk 1'0 + assign \pipe_8_to_10_op__rc__rc 1'0 + assign \pipe_8_to_10_op__rc__rc_ok 1'0 + assign \pipe_8_to_10_op__oe__oe 1'0 + assign \pipe_8_to_10_op__oe__oe_ok 1'0 + assign \pipe_8_to_10_op__invert_a 1'0 + assign \pipe_8_to_10_op__zero_a 1'0 + assign \pipe_8_to_10_op__input_carry 2'00 + assign \pipe_8_to_10_op__invert_out 1'0 + assign \pipe_8_to_10_op__write_cr__data 3'000 + assign \pipe_8_to_10_op__write_cr__ok 1'0 + assign \pipe_8_to_10_op__output_carry 1'0 + assign \pipe_8_to_10_op__is_32bit 1'0 + assign \pipe_8_to_10_op__is_signed 1'0 + assign \pipe_8_to_10_op__data_len 4'0000 + assign \pipe_8_to_10_op__insn 32'00000000000000000000000000000000 + assign { \pipe_8_to_10_op__insn \pipe_8_to_10_op__data_len \pipe_8_to_10_op__is_signed \pipe_8_to_10_op__is_32bit \pipe_8_to_10_op__output_carry { \pipe_8_to_10_op__write_cr__ok \pipe_8_to_10_op__write_cr__data } \pipe_8_to_10_op__invert_out \pipe_8_to_10_op__input_carry \pipe_8_to_10_op__zero_a \pipe_8_to_10_op__invert_a { \pipe_8_to_10_op__oe__oe_ok \pipe_8_to_10_op__oe__oe } { \pipe_8_to_10_op__rc__rc_ok \pipe_8_to_10_op__rc__rc } \pipe_8_to_10_op__lk { \pipe_8_to_10_op__imm_data__imm_ok \pipe_8_to_10_op__imm_data__imm } \pipe_8_to_10_op__fn_unit \pipe_8_to_10_op__insn_type } { \pipe_6_to_8_op__insn$142 \pipe_6_to_8_op__data_len$141 \pipe_6_to_8_op__is_signed$140 \pipe_6_to_8_op__is_32bit$139 \pipe_6_to_8_op__output_carry$138 { \pipe_6_to_8_op__write_cr__ok$137 \pipe_6_to_8_op__write_cr__data$136 } \pipe_6_to_8_op__invert_out$135 \pipe_6_to_8_op__input_carry$134 \pipe_6_to_8_op__zero_a$133 \pipe_6_to_8_op__invert_a$132 { \pipe_6_to_8_op__oe__oe_ok$131 \pipe_6_to_8_op__oe__oe$130 } { \pipe_6_to_8_op__rc__rc_ok$129 \pipe_6_to_8_op__rc__rc$128 } \pipe_6_to_8_op__lk$127 { \pipe_6_to_8_op__imm_data__imm_ok$126 \pipe_6_to_8_op__imm_data__imm$125 } \pipe_6_to_8_op__fn_unit$124 \pipe_6_to_8_op__insn_type$123 } + sync init + end + process $group_159 + assign \pipe_8_to_10_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_8_to_10_ra \pipe_6_to_8_ra$143 + sync init + end + process $group_160 + assign \pipe_8_to_10_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_8_to_10_rb \pipe_6_to_8_rb$144 + sync init + end + process $group_161 + assign \pipe_8_to_10_xer_so 1'0 + assign \pipe_8_to_10_xer_so \pipe_6_to_8_xer_so$145 + sync init + end + process $group_162 + assign \pipe_8_to_10_divisor_neg 1'0 + assign \pipe_8_to_10_divisor_neg \pipe_6_to_8_divisor_neg$146 + sync init + end + process $group_163 + assign \pipe_8_to_10_dividend_neg 1'0 + assign \pipe_8_to_10_dividend_neg \pipe_6_to_8_dividend_neg$147 + sync init + end + process $group_164 + assign \pipe_8_to_10_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_8_to_10_divisor_radicand \pipe_6_to_8_divisor_radicand$148 + sync init + end + process $group_165 + assign \pipe_8_to_10_operation 2'00 + assign \pipe_8_to_10_operation \pipe_6_to_8_operation$149 + sync init + end + process $group_166 + assign \pipe_8_to_10_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_8_to_10_quotient_root \pipe_6_to_8_quotient_root$150 + sync init + end + process $group_167 + assign \pipe_8_to_10_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_8_to_10_root_times_radicand \pipe_6_to_8_root_times_radicand$151 + sync init + end + process $group_168 + assign \pipe_8_to_10_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_8_to_10_compare_lhs \pipe_6_to_8_compare_lhs$152 + sync init + end + process $group_169 + assign \pipe_8_to_10_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_8_to_10_compare_rhs \pipe_6_to_8_compare_rhs$153 + sync init + end + process $group_170 + assign \pipe_10_to_12_p_valid_i 1'0 + assign \pipe_10_to_12_p_valid_i \pipe_8_to_10_n_valid_o + sync init + end + process $group_171 + assign \pipe_8_to_10_n_ready_i 1'0 + assign \pipe_8_to_10_n_ready_i \pipe_10_to_12_p_ready_o + sync init + end + process $group_172 + assign \pipe_10_to_12_muxid 2'00 + assign \pipe_10_to_12_muxid \pipe_8_to_10_muxid$154 + sync init + end + process $group_173 + assign \pipe_10_to_12_op__insn_type 7'0000000 + assign \pipe_10_to_12_op__fn_unit 10'0000000000 + assign \pipe_10_to_12_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_10_to_12_op__imm_data__imm_ok 1'0 + assign \pipe_10_to_12_op__lk 1'0 + assign \pipe_10_to_12_op__rc__rc 1'0 + assign \pipe_10_to_12_op__rc__rc_ok 1'0 + assign \pipe_10_to_12_op__oe__oe 1'0 + assign \pipe_10_to_12_op__oe__oe_ok 1'0 + assign \pipe_10_to_12_op__invert_a 1'0 + assign \pipe_10_to_12_op__zero_a 1'0 + assign \pipe_10_to_12_op__input_carry 2'00 + assign \pipe_10_to_12_op__invert_out 1'0 + assign \pipe_10_to_12_op__write_cr__data 3'000 + assign \pipe_10_to_12_op__write_cr__ok 1'0 + assign \pipe_10_to_12_op__output_carry 1'0 + assign \pipe_10_to_12_op__is_32bit 1'0 + assign \pipe_10_to_12_op__is_signed 1'0 + assign \pipe_10_to_12_op__data_len 4'0000 + assign \pipe_10_to_12_op__insn 32'00000000000000000000000000000000 + assign { \pipe_10_to_12_op__insn \pipe_10_to_12_op__data_len \pipe_10_to_12_op__is_signed \pipe_10_to_12_op__is_32bit \pipe_10_to_12_op__output_carry { \pipe_10_to_12_op__write_cr__ok \pipe_10_to_12_op__write_cr__data } \pipe_10_to_12_op__invert_out \pipe_10_to_12_op__input_carry \pipe_10_to_12_op__zero_a \pipe_10_to_12_op__invert_a { \pipe_10_to_12_op__oe__oe_ok \pipe_10_to_12_op__oe__oe } { \pipe_10_to_12_op__rc__rc_ok \pipe_10_to_12_op__rc__rc } \pipe_10_to_12_op__lk { \pipe_10_to_12_op__imm_data__imm_ok \pipe_10_to_12_op__imm_data__imm } \pipe_10_to_12_op__fn_unit \pipe_10_to_12_op__insn_type } { \pipe_8_to_10_op__insn$174 \pipe_8_to_10_op__data_len$173 \pipe_8_to_10_op__is_signed$172 \pipe_8_to_10_op__is_32bit$171 \pipe_8_to_10_op__output_carry$170 { \pipe_8_to_10_op__write_cr__ok$169 \pipe_8_to_10_op__write_cr__data$168 } \pipe_8_to_10_op__invert_out$167 \pipe_8_to_10_op__input_carry$166 \pipe_8_to_10_op__zero_a$165 \pipe_8_to_10_op__invert_a$164 { \pipe_8_to_10_op__oe__oe_ok$163 \pipe_8_to_10_op__oe__oe$162 } { \pipe_8_to_10_op__rc__rc_ok$161 \pipe_8_to_10_op__rc__rc$160 } \pipe_8_to_10_op__lk$159 { \pipe_8_to_10_op__imm_data__imm_ok$158 \pipe_8_to_10_op__imm_data__imm$157 } \pipe_8_to_10_op__fn_unit$156 \pipe_8_to_10_op__insn_type$155 } + sync init + end + process $group_193 + assign \pipe_10_to_12_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_10_to_12_ra \pipe_8_to_10_ra$175 + sync init + end + process $group_194 + assign \pipe_10_to_12_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_10_to_12_rb \pipe_8_to_10_rb$176 + sync init + end + process $group_195 + assign \pipe_10_to_12_xer_so 1'0 + assign \pipe_10_to_12_xer_so \pipe_8_to_10_xer_so$177 + sync init + end + process $group_196 + assign \pipe_10_to_12_divisor_neg 1'0 + assign \pipe_10_to_12_divisor_neg \pipe_8_to_10_divisor_neg$178 + sync init + end + process $group_197 + assign \pipe_10_to_12_dividend_neg 1'0 + assign \pipe_10_to_12_dividend_neg \pipe_8_to_10_dividend_neg$179 + sync init + end + process $group_198 + assign \pipe_10_to_12_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_10_to_12_divisor_radicand \pipe_8_to_10_divisor_radicand$180 + sync init + end + process $group_199 + assign \pipe_10_to_12_operation 2'00 + assign \pipe_10_to_12_operation \pipe_8_to_10_operation$181 + sync init + end + process $group_200 + assign \pipe_10_to_12_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_10_to_12_quotient_root \pipe_8_to_10_quotient_root$182 + sync init + end + process $group_201 + assign \pipe_10_to_12_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_10_to_12_root_times_radicand \pipe_8_to_10_root_times_radicand$183 + sync init + end + process $group_202 + assign \pipe_10_to_12_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_10_to_12_compare_lhs \pipe_8_to_10_compare_lhs$184 + sync init + end + process $group_203 + assign \pipe_10_to_12_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_10_to_12_compare_rhs \pipe_8_to_10_compare_rhs$185 + sync init + end + process $group_204 + assign \pipe_12_to_14_p_valid_i 1'0 + assign \pipe_12_to_14_p_valid_i \pipe_10_to_12_n_valid_o + sync init + end + process $group_205 + assign \pipe_10_to_12_n_ready_i 1'0 + assign \pipe_10_to_12_n_ready_i \pipe_12_to_14_p_ready_o + sync init + end + process $group_206 + assign \pipe_12_to_14_muxid 2'00 + assign \pipe_12_to_14_muxid \pipe_10_to_12_muxid$186 + sync init + end + process $group_207 + assign \pipe_12_to_14_op__insn_type 7'0000000 + assign \pipe_12_to_14_op__fn_unit 10'0000000000 + assign \pipe_12_to_14_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_12_to_14_op__imm_data__imm_ok 1'0 + assign \pipe_12_to_14_op__lk 1'0 + assign \pipe_12_to_14_op__rc__rc 1'0 + assign \pipe_12_to_14_op__rc__rc_ok 1'0 + assign \pipe_12_to_14_op__oe__oe 1'0 + assign \pipe_12_to_14_op__oe__oe_ok 1'0 + assign \pipe_12_to_14_op__invert_a 1'0 + assign \pipe_12_to_14_op__zero_a 1'0 + assign \pipe_12_to_14_op__input_carry 2'00 + assign \pipe_12_to_14_op__invert_out 1'0 + assign \pipe_12_to_14_op__write_cr__data 3'000 + assign \pipe_12_to_14_op__write_cr__ok 1'0 + assign \pipe_12_to_14_op__output_carry 1'0 + assign \pipe_12_to_14_op__is_32bit 1'0 + assign \pipe_12_to_14_op__is_signed 1'0 + assign \pipe_12_to_14_op__data_len 4'0000 + assign \pipe_12_to_14_op__insn 32'00000000000000000000000000000000 + assign { \pipe_12_to_14_op__insn \pipe_12_to_14_op__data_len \pipe_12_to_14_op__is_signed \pipe_12_to_14_op__is_32bit \pipe_12_to_14_op__output_carry { \pipe_12_to_14_op__write_cr__ok \pipe_12_to_14_op__write_cr__data } \pipe_12_to_14_op__invert_out \pipe_12_to_14_op__input_carry \pipe_12_to_14_op__zero_a \pipe_12_to_14_op__invert_a { \pipe_12_to_14_op__oe__oe_ok \pipe_12_to_14_op__oe__oe } { \pipe_12_to_14_op__rc__rc_ok \pipe_12_to_14_op__rc__rc } \pipe_12_to_14_op__lk { \pipe_12_to_14_op__imm_data__imm_ok \pipe_12_to_14_op__imm_data__imm } \pipe_12_to_14_op__fn_unit \pipe_12_to_14_op__insn_type } { \pipe_10_to_12_op__insn$206 \pipe_10_to_12_op__data_len$205 \pipe_10_to_12_op__is_signed$204 \pipe_10_to_12_op__is_32bit$203 \pipe_10_to_12_op__output_carry$202 { \pipe_10_to_12_op__write_cr__ok$201 \pipe_10_to_12_op__write_cr__data$200 } \pipe_10_to_12_op__invert_out$199 \pipe_10_to_12_op__input_carry$198 \pipe_10_to_12_op__zero_a$197 \pipe_10_to_12_op__invert_a$196 { \pipe_10_to_12_op__oe__oe_ok$195 \pipe_10_to_12_op__oe__oe$194 } { \pipe_10_to_12_op__rc__rc_ok$193 \pipe_10_to_12_op__rc__rc$192 } \pipe_10_to_12_op__lk$191 { \pipe_10_to_12_op__imm_data__imm_ok$190 \pipe_10_to_12_op__imm_data__imm$189 } \pipe_10_to_12_op__fn_unit$188 \pipe_10_to_12_op__insn_type$187 } + sync init + end + process $group_227 + assign \pipe_12_to_14_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_12_to_14_ra \pipe_10_to_12_ra$207 + sync init + end + process $group_228 + assign \pipe_12_to_14_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_12_to_14_rb \pipe_10_to_12_rb$208 + sync init + end + process $group_229 + assign \pipe_12_to_14_xer_so 1'0 + assign \pipe_12_to_14_xer_so \pipe_10_to_12_xer_so$209 + sync init + end + process $group_230 + assign \pipe_12_to_14_divisor_neg 1'0 + assign \pipe_12_to_14_divisor_neg \pipe_10_to_12_divisor_neg$210 + sync init + end + process $group_231 + assign \pipe_12_to_14_dividend_neg 1'0 + assign \pipe_12_to_14_dividend_neg \pipe_10_to_12_dividend_neg$211 + sync init + end + process $group_232 + assign \pipe_12_to_14_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_12_to_14_divisor_radicand \pipe_10_to_12_divisor_radicand$212 + sync init + end + process $group_233 + assign \pipe_12_to_14_operation 2'00 + assign \pipe_12_to_14_operation \pipe_10_to_12_operation$213 + sync init + end + process $group_234 + assign \pipe_12_to_14_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_12_to_14_quotient_root \pipe_10_to_12_quotient_root$214 + sync init + end + process $group_235 + assign \pipe_12_to_14_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_12_to_14_root_times_radicand \pipe_10_to_12_root_times_radicand$215 + sync init + end + process $group_236 + assign \pipe_12_to_14_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_12_to_14_compare_lhs \pipe_10_to_12_compare_lhs$216 + sync init + end + process $group_237 + assign \pipe_12_to_14_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_12_to_14_compare_rhs \pipe_10_to_12_compare_rhs$217 + sync init + end + process $group_238 + assign \pipe_14_to_16_p_valid_i 1'0 + assign \pipe_14_to_16_p_valid_i \pipe_12_to_14_n_valid_o + sync init + end + process $group_239 + assign \pipe_12_to_14_n_ready_i 1'0 + assign \pipe_12_to_14_n_ready_i \pipe_14_to_16_p_ready_o + sync init + end + process $group_240 + assign \pipe_14_to_16_muxid 2'00 + assign \pipe_14_to_16_muxid \pipe_12_to_14_muxid$218 + sync init + end + process $group_241 + assign \pipe_14_to_16_op__insn_type 7'0000000 + assign \pipe_14_to_16_op__fn_unit 10'0000000000 + assign \pipe_14_to_16_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_14_to_16_op__imm_data__imm_ok 1'0 + assign \pipe_14_to_16_op__lk 1'0 + assign \pipe_14_to_16_op__rc__rc 1'0 + assign \pipe_14_to_16_op__rc__rc_ok 1'0 + assign \pipe_14_to_16_op__oe__oe 1'0 + assign \pipe_14_to_16_op__oe__oe_ok 1'0 + assign \pipe_14_to_16_op__invert_a 1'0 + assign \pipe_14_to_16_op__zero_a 1'0 + assign \pipe_14_to_16_op__input_carry 2'00 + assign \pipe_14_to_16_op__invert_out 1'0 + assign \pipe_14_to_16_op__write_cr__data 3'000 + assign \pipe_14_to_16_op__write_cr__ok 1'0 + assign \pipe_14_to_16_op__output_carry 1'0 + assign \pipe_14_to_16_op__is_32bit 1'0 + assign \pipe_14_to_16_op__is_signed 1'0 + assign \pipe_14_to_16_op__data_len 4'0000 + assign \pipe_14_to_16_op__insn 32'00000000000000000000000000000000 + assign { \pipe_14_to_16_op__insn \pipe_14_to_16_op__data_len \pipe_14_to_16_op__is_signed \pipe_14_to_16_op__is_32bit \pipe_14_to_16_op__output_carry { \pipe_14_to_16_op__write_cr__ok \pipe_14_to_16_op__write_cr__data } \pipe_14_to_16_op__invert_out \pipe_14_to_16_op__input_carry \pipe_14_to_16_op__zero_a \pipe_14_to_16_op__invert_a { \pipe_14_to_16_op__oe__oe_ok \pipe_14_to_16_op__oe__oe } { \pipe_14_to_16_op__rc__rc_ok \pipe_14_to_16_op__rc__rc } \pipe_14_to_16_op__lk { \pipe_14_to_16_op__imm_data__imm_ok \pipe_14_to_16_op__imm_data__imm } \pipe_14_to_16_op__fn_unit \pipe_14_to_16_op__insn_type } { \pipe_12_to_14_op__insn$238 \pipe_12_to_14_op__data_len$237 \pipe_12_to_14_op__is_signed$236 \pipe_12_to_14_op__is_32bit$235 \pipe_12_to_14_op__output_carry$234 { \pipe_12_to_14_op__write_cr__ok$233 \pipe_12_to_14_op__write_cr__data$232 } \pipe_12_to_14_op__invert_out$231 \pipe_12_to_14_op__input_carry$230 \pipe_12_to_14_op__zero_a$229 \pipe_12_to_14_op__invert_a$228 { \pipe_12_to_14_op__oe__oe_ok$227 \pipe_12_to_14_op__oe__oe$226 } { \pipe_12_to_14_op__rc__rc_ok$225 \pipe_12_to_14_op__rc__rc$224 } \pipe_12_to_14_op__lk$223 { \pipe_12_to_14_op__imm_data__imm_ok$222 \pipe_12_to_14_op__imm_data__imm$221 } \pipe_12_to_14_op__fn_unit$220 \pipe_12_to_14_op__insn_type$219 } + sync init + end + process $group_261 + assign \pipe_14_to_16_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_14_to_16_ra \pipe_12_to_14_ra$239 + sync init + end + process $group_262 + assign \pipe_14_to_16_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_14_to_16_rb \pipe_12_to_14_rb$240 + sync init + end + process $group_263 + assign \pipe_14_to_16_xer_so 1'0 + assign \pipe_14_to_16_xer_so \pipe_12_to_14_xer_so$241 + sync init + end + process $group_264 + assign \pipe_14_to_16_divisor_neg 1'0 + assign \pipe_14_to_16_divisor_neg \pipe_12_to_14_divisor_neg$242 + sync init + end + process $group_265 + assign \pipe_14_to_16_dividend_neg 1'0 + assign \pipe_14_to_16_dividend_neg \pipe_12_to_14_dividend_neg$243 + sync init + end + process $group_266 + assign \pipe_14_to_16_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_14_to_16_divisor_radicand \pipe_12_to_14_divisor_radicand$244 + sync init + end + process $group_267 + assign \pipe_14_to_16_operation 2'00 + assign \pipe_14_to_16_operation \pipe_12_to_14_operation$245 + sync init + end + process $group_268 + assign \pipe_14_to_16_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_14_to_16_quotient_root \pipe_12_to_14_quotient_root$246 + sync init + end + process $group_269 + assign \pipe_14_to_16_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_14_to_16_root_times_radicand \pipe_12_to_14_root_times_radicand$247 + sync init + end + process $group_270 + assign \pipe_14_to_16_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_14_to_16_compare_lhs \pipe_12_to_14_compare_lhs$248 + sync init + end + process $group_271 + assign \pipe_14_to_16_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_14_to_16_compare_rhs \pipe_12_to_14_compare_rhs$249 + sync init + end + process $group_272 + assign \pipe_16_to_18_p_valid_i 1'0 + assign \pipe_16_to_18_p_valid_i \pipe_14_to_16_n_valid_o + sync init + end + process $group_273 + assign \pipe_14_to_16_n_ready_i 1'0 + assign \pipe_14_to_16_n_ready_i \pipe_16_to_18_p_ready_o + sync init + end + process $group_274 + assign \pipe_16_to_18_muxid 2'00 + assign \pipe_16_to_18_muxid \pipe_14_to_16_muxid$250 + sync init + end + process $group_275 + assign \pipe_16_to_18_op__insn_type 7'0000000 + assign \pipe_16_to_18_op__fn_unit 10'0000000000 + assign \pipe_16_to_18_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_16_to_18_op__imm_data__imm_ok 1'0 + assign \pipe_16_to_18_op__lk 1'0 + assign \pipe_16_to_18_op__rc__rc 1'0 + assign \pipe_16_to_18_op__rc__rc_ok 1'0 + assign \pipe_16_to_18_op__oe__oe 1'0 + assign \pipe_16_to_18_op__oe__oe_ok 1'0 + assign \pipe_16_to_18_op__invert_a 1'0 + assign \pipe_16_to_18_op__zero_a 1'0 + assign \pipe_16_to_18_op__input_carry 2'00 + assign \pipe_16_to_18_op__invert_out 1'0 + assign \pipe_16_to_18_op__write_cr__data 3'000 + assign \pipe_16_to_18_op__write_cr__ok 1'0 + assign \pipe_16_to_18_op__output_carry 1'0 + assign \pipe_16_to_18_op__is_32bit 1'0 + assign \pipe_16_to_18_op__is_signed 1'0 + assign \pipe_16_to_18_op__data_len 4'0000 + assign \pipe_16_to_18_op__insn 32'00000000000000000000000000000000 + assign { \pipe_16_to_18_op__insn \pipe_16_to_18_op__data_len \pipe_16_to_18_op__is_signed \pipe_16_to_18_op__is_32bit \pipe_16_to_18_op__output_carry { \pipe_16_to_18_op__write_cr__ok \pipe_16_to_18_op__write_cr__data } \pipe_16_to_18_op__invert_out \pipe_16_to_18_op__input_carry \pipe_16_to_18_op__zero_a \pipe_16_to_18_op__invert_a { \pipe_16_to_18_op__oe__oe_ok \pipe_16_to_18_op__oe__oe } { \pipe_16_to_18_op__rc__rc_ok \pipe_16_to_18_op__rc__rc } \pipe_16_to_18_op__lk { \pipe_16_to_18_op__imm_data__imm_ok \pipe_16_to_18_op__imm_data__imm } \pipe_16_to_18_op__fn_unit \pipe_16_to_18_op__insn_type } { \pipe_14_to_16_op__insn$270 \pipe_14_to_16_op__data_len$269 \pipe_14_to_16_op__is_signed$268 \pipe_14_to_16_op__is_32bit$267 \pipe_14_to_16_op__output_carry$266 { \pipe_14_to_16_op__write_cr__ok$265 \pipe_14_to_16_op__write_cr__data$264 } \pipe_14_to_16_op__invert_out$263 \pipe_14_to_16_op__input_carry$262 \pipe_14_to_16_op__zero_a$261 \pipe_14_to_16_op__invert_a$260 { \pipe_14_to_16_op__oe__oe_ok$259 \pipe_14_to_16_op__oe__oe$258 } { \pipe_14_to_16_op__rc__rc_ok$257 \pipe_14_to_16_op__rc__rc$256 } \pipe_14_to_16_op__lk$255 { \pipe_14_to_16_op__imm_data__imm_ok$254 \pipe_14_to_16_op__imm_data__imm$253 } \pipe_14_to_16_op__fn_unit$252 \pipe_14_to_16_op__insn_type$251 } + sync init + end + process $group_295 + assign \pipe_16_to_18_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_16_to_18_ra \pipe_14_to_16_ra$271 + sync init + end + process $group_296 + assign \pipe_16_to_18_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_16_to_18_rb \pipe_14_to_16_rb$272 + sync init + end + process $group_297 + assign \pipe_16_to_18_xer_so 1'0 + assign \pipe_16_to_18_xer_so \pipe_14_to_16_xer_so$273 + sync init + end + process $group_298 + assign \pipe_16_to_18_divisor_neg 1'0 + assign \pipe_16_to_18_divisor_neg \pipe_14_to_16_divisor_neg$274 + sync init + end + process $group_299 + assign \pipe_16_to_18_dividend_neg 1'0 + assign \pipe_16_to_18_dividend_neg \pipe_14_to_16_dividend_neg$275 + sync init + end + process $group_300 + assign \pipe_16_to_18_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_16_to_18_divisor_radicand \pipe_14_to_16_divisor_radicand$276 + sync init + end + process $group_301 + assign \pipe_16_to_18_operation 2'00 + assign \pipe_16_to_18_operation \pipe_14_to_16_operation$277 + sync init + end + process $group_302 + assign \pipe_16_to_18_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_16_to_18_quotient_root \pipe_14_to_16_quotient_root$278 + sync init + end + process $group_303 + assign \pipe_16_to_18_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_16_to_18_root_times_radicand \pipe_14_to_16_root_times_radicand$279 + sync init + end + process $group_304 + assign \pipe_16_to_18_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_16_to_18_compare_lhs \pipe_14_to_16_compare_lhs$280 + sync init + end + process $group_305 + assign \pipe_16_to_18_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_16_to_18_compare_rhs \pipe_14_to_16_compare_rhs$281 + sync init + end + process $group_306 + assign \pipe_18_to_20_p_valid_i 1'0 + assign \pipe_18_to_20_p_valid_i \pipe_16_to_18_n_valid_o + sync init + end + process $group_307 + assign \pipe_16_to_18_n_ready_i 1'0 + assign \pipe_16_to_18_n_ready_i \pipe_18_to_20_p_ready_o + sync init + end + process $group_308 + assign \pipe_18_to_20_muxid 2'00 + assign \pipe_18_to_20_muxid \pipe_16_to_18_muxid$282 + sync init + end + process $group_309 + assign \pipe_18_to_20_op__insn_type 7'0000000 + assign \pipe_18_to_20_op__fn_unit 10'0000000000 + assign \pipe_18_to_20_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_18_to_20_op__imm_data__imm_ok 1'0 + assign \pipe_18_to_20_op__lk 1'0 + assign \pipe_18_to_20_op__rc__rc 1'0 + assign \pipe_18_to_20_op__rc__rc_ok 1'0 + assign \pipe_18_to_20_op__oe__oe 1'0 + assign \pipe_18_to_20_op__oe__oe_ok 1'0 + assign \pipe_18_to_20_op__invert_a 1'0 + assign \pipe_18_to_20_op__zero_a 1'0 + assign \pipe_18_to_20_op__input_carry 2'00 + assign \pipe_18_to_20_op__invert_out 1'0 + assign \pipe_18_to_20_op__write_cr__data 3'000 + assign \pipe_18_to_20_op__write_cr__ok 1'0 + assign \pipe_18_to_20_op__output_carry 1'0 + assign \pipe_18_to_20_op__is_32bit 1'0 + assign \pipe_18_to_20_op__is_signed 1'0 + assign \pipe_18_to_20_op__data_len 4'0000 + assign \pipe_18_to_20_op__insn 32'00000000000000000000000000000000 + assign { \pipe_18_to_20_op__insn \pipe_18_to_20_op__data_len \pipe_18_to_20_op__is_signed \pipe_18_to_20_op__is_32bit \pipe_18_to_20_op__output_carry { \pipe_18_to_20_op__write_cr__ok \pipe_18_to_20_op__write_cr__data } \pipe_18_to_20_op__invert_out \pipe_18_to_20_op__input_carry \pipe_18_to_20_op__zero_a \pipe_18_to_20_op__invert_a { \pipe_18_to_20_op__oe__oe_ok \pipe_18_to_20_op__oe__oe } { \pipe_18_to_20_op__rc__rc_ok \pipe_18_to_20_op__rc__rc } \pipe_18_to_20_op__lk { \pipe_18_to_20_op__imm_data__imm_ok \pipe_18_to_20_op__imm_data__imm } \pipe_18_to_20_op__fn_unit \pipe_18_to_20_op__insn_type } { \pipe_16_to_18_op__insn$302 \pipe_16_to_18_op__data_len$301 \pipe_16_to_18_op__is_signed$300 \pipe_16_to_18_op__is_32bit$299 \pipe_16_to_18_op__output_carry$298 { \pipe_16_to_18_op__write_cr__ok$297 \pipe_16_to_18_op__write_cr__data$296 } \pipe_16_to_18_op__invert_out$295 \pipe_16_to_18_op__input_carry$294 \pipe_16_to_18_op__zero_a$293 \pipe_16_to_18_op__invert_a$292 { \pipe_16_to_18_op__oe__oe_ok$291 \pipe_16_to_18_op__oe__oe$290 } { \pipe_16_to_18_op__rc__rc_ok$289 \pipe_16_to_18_op__rc__rc$288 } \pipe_16_to_18_op__lk$287 { \pipe_16_to_18_op__imm_data__imm_ok$286 \pipe_16_to_18_op__imm_data__imm$285 } \pipe_16_to_18_op__fn_unit$284 \pipe_16_to_18_op__insn_type$283 } + sync init + end + process $group_329 + assign \pipe_18_to_20_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_18_to_20_ra \pipe_16_to_18_ra$303 + sync init + end + process $group_330 + assign \pipe_18_to_20_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_18_to_20_rb \pipe_16_to_18_rb$304 + sync init + end + process $group_331 + assign \pipe_18_to_20_xer_so 1'0 + assign \pipe_18_to_20_xer_so \pipe_16_to_18_xer_so$305 + sync init + end + process $group_332 + assign \pipe_18_to_20_divisor_neg 1'0 + assign \pipe_18_to_20_divisor_neg \pipe_16_to_18_divisor_neg$306 + sync init + end + process $group_333 + assign \pipe_18_to_20_dividend_neg 1'0 + assign \pipe_18_to_20_dividend_neg \pipe_16_to_18_dividend_neg$307 + sync init + end + process $group_334 + assign \pipe_18_to_20_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_18_to_20_divisor_radicand \pipe_16_to_18_divisor_radicand$308 + sync init + end + process $group_335 + assign \pipe_18_to_20_operation 2'00 + assign \pipe_18_to_20_operation \pipe_16_to_18_operation$309 + sync init + end + process $group_336 + assign \pipe_18_to_20_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_18_to_20_quotient_root \pipe_16_to_18_quotient_root$310 + sync init + end + process $group_337 + assign \pipe_18_to_20_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_18_to_20_root_times_radicand \pipe_16_to_18_root_times_radicand$311 + sync init + end + process $group_338 + assign \pipe_18_to_20_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_18_to_20_compare_lhs \pipe_16_to_18_compare_lhs$312 + sync init + end + process $group_339 + assign \pipe_18_to_20_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_18_to_20_compare_rhs \pipe_16_to_18_compare_rhs$313 + sync init + end + process $group_340 + assign \pipe_20_to_22_p_valid_i 1'0 + assign \pipe_20_to_22_p_valid_i \pipe_18_to_20_n_valid_o + sync init + end + process $group_341 + assign \pipe_18_to_20_n_ready_i 1'0 + assign \pipe_18_to_20_n_ready_i \pipe_20_to_22_p_ready_o + sync init + end + process $group_342 + assign \pipe_20_to_22_muxid 2'00 + assign \pipe_20_to_22_muxid \pipe_18_to_20_muxid$314 + sync init + end + process $group_343 + assign \pipe_20_to_22_op__insn_type 7'0000000 + assign \pipe_20_to_22_op__fn_unit 10'0000000000 + assign \pipe_20_to_22_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_20_to_22_op__imm_data__imm_ok 1'0 + assign \pipe_20_to_22_op__lk 1'0 + assign \pipe_20_to_22_op__rc__rc 1'0 + assign \pipe_20_to_22_op__rc__rc_ok 1'0 + assign \pipe_20_to_22_op__oe__oe 1'0 + assign \pipe_20_to_22_op__oe__oe_ok 1'0 + assign \pipe_20_to_22_op__invert_a 1'0 + assign \pipe_20_to_22_op__zero_a 1'0 + assign \pipe_20_to_22_op__input_carry 2'00 + assign \pipe_20_to_22_op__invert_out 1'0 + assign \pipe_20_to_22_op__write_cr__data 3'000 + assign \pipe_20_to_22_op__write_cr__ok 1'0 + assign \pipe_20_to_22_op__output_carry 1'0 + assign \pipe_20_to_22_op__is_32bit 1'0 + assign \pipe_20_to_22_op__is_signed 1'0 + assign \pipe_20_to_22_op__data_len 4'0000 + assign \pipe_20_to_22_op__insn 32'00000000000000000000000000000000 + assign { \pipe_20_to_22_op__insn \pipe_20_to_22_op__data_len \pipe_20_to_22_op__is_signed \pipe_20_to_22_op__is_32bit \pipe_20_to_22_op__output_carry { \pipe_20_to_22_op__write_cr__ok \pipe_20_to_22_op__write_cr__data } \pipe_20_to_22_op__invert_out \pipe_20_to_22_op__input_carry \pipe_20_to_22_op__zero_a \pipe_20_to_22_op__invert_a { \pipe_20_to_22_op__oe__oe_ok \pipe_20_to_22_op__oe__oe } { \pipe_20_to_22_op__rc__rc_ok \pipe_20_to_22_op__rc__rc } \pipe_20_to_22_op__lk { \pipe_20_to_22_op__imm_data__imm_ok \pipe_20_to_22_op__imm_data__imm } \pipe_20_to_22_op__fn_unit \pipe_20_to_22_op__insn_type } { \pipe_18_to_20_op__insn$334 \pipe_18_to_20_op__data_len$333 \pipe_18_to_20_op__is_signed$332 \pipe_18_to_20_op__is_32bit$331 \pipe_18_to_20_op__output_carry$330 { \pipe_18_to_20_op__write_cr__ok$329 \pipe_18_to_20_op__write_cr__data$328 } \pipe_18_to_20_op__invert_out$327 \pipe_18_to_20_op__input_carry$326 \pipe_18_to_20_op__zero_a$325 \pipe_18_to_20_op__invert_a$324 { \pipe_18_to_20_op__oe__oe_ok$323 \pipe_18_to_20_op__oe__oe$322 } { \pipe_18_to_20_op__rc__rc_ok$321 \pipe_18_to_20_op__rc__rc$320 } \pipe_18_to_20_op__lk$319 { \pipe_18_to_20_op__imm_data__imm_ok$318 \pipe_18_to_20_op__imm_data__imm$317 } \pipe_18_to_20_op__fn_unit$316 \pipe_18_to_20_op__insn_type$315 } + sync init + end + process $group_363 + assign \pipe_20_to_22_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_20_to_22_ra \pipe_18_to_20_ra$335 + sync init + end + process $group_364 + assign \pipe_20_to_22_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_20_to_22_rb \pipe_18_to_20_rb$336 + sync init + end + process $group_365 + assign \pipe_20_to_22_xer_so 1'0 + assign \pipe_20_to_22_xer_so \pipe_18_to_20_xer_so$337 + sync init + end + process $group_366 + assign \pipe_20_to_22_divisor_neg 1'0 + assign \pipe_20_to_22_divisor_neg \pipe_18_to_20_divisor_neg$338 + sync init + end + process $group_367 + assign \pipe_20_to_22_dividend_neg 1'0 + assign \pipe_20_to_22_dividend_neg \pipe_18_to_20_dividend_neg$339 + sync init + end + process $group_368 + assign \pipe_20_to_22_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_20_to_22_divisor_radicand \pipe_18_to_20_divisor_radicand$340 + sync init + end + process $group_369 + assign \pipe_20_to_22_operation 2'00 + assign \pipe_20_to_22_operation \pipe_18_to_20_operation$341 + sync init + end + process $group_370 + assign \pipe_20_to_22_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_20_to_22_quotient_root \pipe_18_to_20_quotient_root$342 + sync init + end + process $group_371 + assign \pipe_20_to_22_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_20_to_22_root_times_radicand \pipe_18_to_20_root_times_radicand$343 + sync init + end + process $group_372 + assign \pipe_20_to_22_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_20_to_22_compare_lhs \pipe_18_to_20_compare_lhs$344 + sync init + end + process $group_373 + assign \pipe_20_to_22_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_20_to_22_compare_rhs \pipe_18_to_20_compare_rhs$345 + sync init + end + process $group_374 + assign \pipe_end_p_valid_i 1'0 + assign \pipe_end_p_valid_i \pipe_20_to_22_n_valid_o + sync init + end + process $group_375 + assign \pipe_20_to_22_n_ready_i 1'0 + assign \pipe_20_to_22_n_ready_i \pipe_end_p_ready_o + sync init + end + process $group_376 + assign \pipe_end_muxid 2'00 + assign \pipe_end_muxid \pipe_20_to_22_muxid$346 + sync init + end + process $group_377 + assign \pipe_end_op__insn_type 7'0000000 + assign \pipe_end_op__fn_unit 10'0000000000 + assign \pipe_end_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_op__imm_data__imm_ok 1'0 + assign \pipe_end_op__lk 1'0 + assign \pipe_end_op__rc__rc 1'0 + assign \pipe_end_op__rc__rc_ok 1'0 + assign \pipe_end_op__oe__oe 1'0 + assign \pipe_end_op__oe__oe_ok 1'0 + assign \pipe_end_op__invert_a 1'0 + assign \pipe_end_op__zero_a 1'0 + assign \pipe_end_op__input_carry 2'00 + assign \pipe_end_op__invert_out 1'0 + assign \pipe_end_op__write_cr__data 3'000 + assign \pipe_end_op__write_cr__ok 1'0 + assign \pipe_end_op__output_carry 1'0 + assign \pipe_end_op__is_32bit 1'0 + assign \pipe_end_op__is_signed 1'0 + assign \pipe_end_op__data_len 4'0000 + assign \pipe_end_op__insn 32'00000000000000000000000000000000 + assign { \pipe_end_op__insn \pipe_end_op__data_len \pipe_end_op__is_signed \pipe_end_op__is_32bit \pipe_end_op__output_carry { \pipe_end_op__write_cr__ok \pipe_end_op__write_cr__data } \pipe_end_op__invert_out \pipe_end_op__input_carry \pipe_end_op__zero_a \pipe_end_op__invert_a { \pipe_end_op__oe__oe_ok \pipe_end_op__oe__oe } { \pipe_end_op__rc__rc_ok \pipe_end_op__rc__rc } \pipe_end_op__lk { \pipe_end_op__imm_data__imm_ok \pipe_end_op__imm_data__imm } \pipe_end_op__fn_unit \pipe_end_op__insn_type } { \pipe_20_to_22_op__insn$366 \pipe_20_to_22_op__data_len$365 \pipe_20_to_22_op__is_signed$364 \pipe_20_to_22_op__is_32bit$363 \pipe_20_to_22_op__output_carry$362 { \pipe_20_to_22_op__write_cr__ok$361 \pipe_20_to_22_op__write_cr__data$360 } \pipe_20_to_22_op__invert_out$359 \pipe_20_to_22_op__input_carry$358 \pipe_20_to_22_op__zero_a$357 \pipe_20_to_22_op__invert_a$356 { \pipe_20_to_22_op__oe__oe_ok$355 \pipe_20_to_22_op__oe__oe$354 } { \pipe_20_to_22_op__rc__rc_ok$353 \pipe_20_to_22_op__rc__rc$352 } \pipe_20_to_22_op__lk$351 { \pipe_20_to_22_op__imm_data__imm_ok$350 \pipe_20_to_22_op__imm_data__imm$349 } \pipe_20_to_22_op__fn_unit$348 \pipe_20_to_22_op__insn_type$347 } + sync init + end + process $group_397 + assign \pipe_end_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_ra \pipe_20_to_22_ra$367 + sync init + end + process $group_398 + assign \pipe_end_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_rb \pipe_20_to_22_rb$368 + sync init + end + process $group_399 + assign \pipe_end_xer_so 1'0 + assign \pipe_end_xer_so \pipe_20_to_22_xer_so$369 + sync init + end + process $group_400 + assign \pipe_end_divisor_neg 1'0 + assign \pipe_end_divisor_neg \pipe_20_to_22_divisor_neg$370 + sync init + end + process $group_401 + assign \pipe_end_dividend_neg 1'0 + assign \pipe_end_dividend_neg \pipe_20_to_22_dividend_neg$371 + sync init + end + process $group_402 + assign \pipe_end_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_divisor_radicand \pipe_20_to_22_divisor_radicand$372 + sync init + end + process $group_403 + assign \pipe_end_operation 2'00 + assign \pipe_end_operation \pipe_20_to_22_operation$373 + sync init + end + process $group_404 + assign \pipe_end_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_quotient_root \pipe_20_to_22_quotient_root$374 + sync init + end + process $group_405 + assign \pipe_end_root_times_radicand 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_root_times_radicand \pipe_20_to_22_root_times_radicand$375 + sync init + end + process $group_406 + assign \pipe_end_compare_lhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_compare_lhs \pipe_20_to_22_compare_lhs$376 + sync init + end + process $group_407 + assign \pipe_end_compare_rhs 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_end_compare_rhs \pipe_20_to_22_compare_rhs$377 + sync init + end + process $group_408 + assign \pipe_start_p_valid_i 1'0 + assign \pipe_start_p_valid_i \p_valid_i + sync init + end + process $group_409 + assign \p_ready_o 1'0 + assign \p_ready_o \pipe_start_p_ready_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid + process $group_410 + assign \pipe_start_muxid$2 2'00 + assign \pipe_start_muxid$2 \muxid + sync init + end + process $group_411 + assign \pipe_start_op__insn_type$3 7'0000000 + assign \pipe_start_op__fn_unit$4 10'0000000000 + assign \pipe_start_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_start_op__imm_data__imm_ok$6 1'0 + assign \pipe_start_op__lk$7 1'0 + assign \pipe_start_op__rc__rc$8 1'0 + assign \pipe_start_op__rc__rc_ok$9 1'0 + assign \pipe_start_op__oe__oe$10 1'0 + assign \pipe_start_op__oe__oe_ok$11 1'0 + assign \pipe_start_op__invert_a$12 1'0 + assign \pipe_start_op__zero_a$13 1'0 + assign \pipe_start_op__input_carry$14 2'00 + assign \pipe_start_op__invert_out$15 1'0 + assign \pipe_start_op__write_cr__data$16 3'000 + assign \pipe_start_op__write_cr__ok$17 1'0 + assign \pipe_start_op__output_carry$18 1'0 + assign \pipe_start_op__is_32bit$19 1'0 + assign \pipe_start_op__is_signed$20 1'0 + assign \pipe_start_op__data_len$21 4'0000 + assign \pipe_start_op__insn$22 32'00000000000000000000000000000000 + assign { \pipe_start_op__insn$22 \pipe_start_op__data_len$21 \pipe_start_op__is_signed$20 \pipe_start_op__is_32bit$19 \pipe_start_op__output_carry$18 { \pipe_start_op__write_cr__ok$17 \pipe_start_op__write_cr__data$16 } \pipe_start_op__invert_out$15 \pipe_start_op__input_carry$14 \pipe_start_op__zero_a$13 \pipe_start_op__invert_a$12 { \pipe_start_op__oe__oe_ok$11 \pipe_start_op__oe__oe$10 } { \pipe_start_op__rc__rc_ok$9 \pipe_start_op__rc__rc$8 } \pipe_start_op__lk$7 { \pipe_start_op__imm_data__imm_ok$6 \pipe_start_op__imm_data__imm$5 } \pipe_start_op__fn_unit$4 \pipe_start_op__insn_type$3 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type } + sync init + end + process $group_431 + assign \pipe_start_ra$23 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_start_ra$23 \ra + sync init + end + process $group_432 + assign \pipe_start_rb$24 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_start_rb$24 \rb + sync init + end + process $group_433 + assign \pipe_start_xer_so$25 1'0 + assign \pipe_start_xer_so$25 \xer_so$1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 \xer_ca$400 + process $group_434 + assign \pipe_start_xer_ca 2'00 + assign \pipe_start_xer_ca \xer_ca$400 + sync init + end + process $group_435 + assign \n_valid_o 1'0 + assign \n_valid_o \pipe_end_n_valid_o + sync init + end + process $group_436 + assign \pipe_end_n_ready_i 1'0 + assign \pipe_end_n_ready_i \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$401 + process $group_437 + assign \muxid$401 2'00 + assign \muxid$401 \pipe_end_muxid$378 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \op__insn_type$402 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \op__fn_unit$403 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \op__imm_data__imm$404 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__imm_data__imm_ok$405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__lk$406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc$407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__rc__rc_ok$408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe$409 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__oe__oe_ok$410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_a$411 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__zero_a$412 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \op__input_carry$413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__invert_out$414 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \op__write_cr__data$415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__write_cr__ok$416 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__output_carry$417 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_32bit$418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \op__is_signed$419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \op__data_len$420 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \op__insn$421 + process $group_438 + assign \op__insn_type$402 7'0000000 + assign \op__fn_unit$403 10'0000000000 + assign \op__imm_data__imm$404 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \op__imm_data__imm_ok$405 1'0 + assign \op__lk$406 1'0 + assign \op__rc__rc$407 1'0 + assign \op__rc__rc_ok$408 1'0 + assign \op__oe__oe$409 1'0 + assign \op__oe__oe_ok$410 1'0 + assign \op__invert_a$411 1'0 + assign \op__zero_a$412 1'0 + assign \op__input_carry$413 2'00 + assign \op__invert_out$414 1'0 + assign \op__write_cr__data$415 3'000 + assign \op__write_cr__ok$416 1'0 + assign \op__output_carry$417 1'0 + assign \op__is_32bit$418 1'0 + assign \op__is_signed$419 1'0 + assign \op__data_len$420 4'0000 + assign \op__insn$421 32'00000000000000000000000000000000 + assign { \op__insn$421 \op__data_len$420 \op__is_signed$419 \op__is_32bit$418 \op__output_carry$417 { \op__write_cr__ok$416 \op__write_cr__data$415 } \op__invert_out$414 \op__input_carry$413 \op__zero_a$412 \op__invert_a$411 { \op__oe__oe_ok$410 \op__oe__oe$409 } { \op__rc__rc_ok$408 \op__rc__rc$407 } \op__lk$406 { \op__imm_data__imm_ok$405 \op__imm_data__imm$404 } \op__fn_unit$403 \op__insn_type$402 } { \pipe_end_op__insn$398 \pipe_end_op__data_len$397 \pipe_end_op__is_signed$396 \pipe_end_op__is_32bit$395 \pipe_end_op__output_carry$394 { \pipe_end_op__write_cr__ok$393 \pipe_end_op__write_cr__data$392 } \pipe_end_op__invert_out$391 \pipe_end_op__input_carry$390 \pipe_end_op__zero_a$389 \pipe_end_op__invert_a$388 { \pipe_end_op__oe__oe_ok$387 \pipe_end_op__oe__oe$386 } { \pipe_end_op__rc__rc_ok$385 \pipe_end_op__rc__rc$384 } \pipe_end_op__lk$383 { \pipe_end_op__imm_data__imm_ok$382 \pipe_end_op__imm_data__imm$381 } \pipe_end_op__fn_unit$380 \pipe_end_op__insn_type$379 } + sync init + end + process $group_458 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok 1'0 + assign { \o_ok \o } { \pipe_end_o_ok \pipe_end_o } + sync init + end + process $group_460 + assign \cr_a 4'0000 + assign \cr_a_ok 1'0 + assign { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a } + sync init + end + process $group_462 + assign \xer_ca 2'00 + assign \xer_ca_ok 1'0 + assign { \xer_ca_ok \xer_ca } { \pipe_end_xer_ca_ok \pipe_end_xer_ca } + sync init + end + process $group_464 + assign \xer_ov 2'00 + assign \xer_ov_ok 1'0 + assign { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov } + sync init + end + process $group_466 + assign \xer_so 1'0 + assign \xer_so_ok 1'0 + assign { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$399 } + sync init + end + connect \muxid 2'00 + connect \xer_ca$400 2'00 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.src_l" +module \src_l$283 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $3 + connect \B \s_src + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 3'000 + end + sync init + update \q_int 3'000 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 3 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 3 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 3 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $9 + connect \B \s_src + connect \Y $11 + end + process $group_1 + assign \q_src 3'000 + assign \q_src $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $13 + end + process $group_2 + assign \qn_src 3'000 + assign \qn_src $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_src 3'000 + assign \qlq_src $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.opc_l" +module \opc_l$284 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 1 input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_opc + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_opc + connect \Y $11 + end + process $group_1 + assign \q_opc 1'0 + assign \q_opc $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $13 + end + process $group_2 + assign \qn_opc 1'0 + assign \qn_opc $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_opc 1'0 + assign \qlq_opc $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.req_l" +module \req_l$285 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 5 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 5 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 5 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 5 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $3 + connect \B \s_req + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 5'00000 + end + sync init + update \q_int 5'00000 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 5 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 5 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 5 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $9 + connect \B \s_req + connect \Y $11 + end + process $group_1 + assign \q_req 5'00000 + assign \q_req $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \Y $13 + end + process $group_2 + assign \qn_req 5'00000 + assign \qn_req $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 5 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_req 5'00000 + assign \qlq_req $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rst_l" +module \rst_l$286 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rst + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rst + connect \Y $11 + end + process $group_1 + assign \q_rst 1'0 + assign \q_rst $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $13 + end + process $group_2 + assign \qn_rst 1'0 + assign \qn_rst $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rst 1'0 + assign \qlq_rst $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rok_l" +module \rok_l$287 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rdok + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rdok + connect \Y $11 + end + process $group_1 + assign \q_rdok 1'0 + assign \q_rdok $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $13 + end + process $group_2 + assign \qn_rdok 1'0 + assign \qn_rdok $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rdok 1'0 + assign \qlq_rdok $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alui_l" +module \alui_l$288 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 1 input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alui + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alui + connect \Y $11 + end + process $group_1 + assign \q_alui 1'0 + assign \q_alui $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $13 + end + process $group_2 + assign \qn_alui 1'0 + assign \qn_alui $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alui 1'0 + assign \qlq_alui $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_l" +module \alu_l$289 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 1 input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alu + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alu + connect \Y $11 + end + process $group_1 + assign \q_alu 1'0 + assign \q_alu $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $13 + end + process $group_2 + assign \qn_alu 1'0 + assign \qn_alu $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alu 1'0 + assign \qlq_alu $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.div0" +module \div0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 2 \oper_i__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 3 \oper_i__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 4 \oper_i__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \oper_i__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \oper_i__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \oper_i__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \oper_i__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \oper_i__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \oper_i__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \oper_i__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \oper_i__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 13 \oper_i__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \oper_i__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 15 \oper_i__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \oper_i__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \oper_i__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \oper_i__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \oper_i__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 20 \oper_i__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 21 \oper_i__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" + wire width 1 input 22 \issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" + wire width 1 output 23 \busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" + wire width 3 input 24 \rdmaskn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 output 25 \rd__rel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 input 26 \rd__go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 input 27 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 input 28 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 1 input 29 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 30 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 5 output 31 \wr__rel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 5 input 32 \wr__go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 33 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 34 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 4 output 35 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 36 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 37 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 38 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 39 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 40 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 41 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 1 input 42 \go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" + wire width 1 input 43 \shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 64 output 44 \dest1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \alu_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \alu_n_ready_i + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \alu_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \alu_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \alu_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \alu_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \alu_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \alu_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \alu_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \alu_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \alu_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \alu_p_ready_o + cell \alu$45 \alu + connect \rst \rst + connect \clk \clk + connect \o_ok \o_ok + connect \o \o + connect \cr_a_ok \cr_a_ok + connect \cr_a \cr_a + connect \xer_ca_ok \xer_ca_ok + connect \xer_ca \xer_ca + connect \xer_ov_ok \xer_ov_ok + connect \xer_ov \xer_ov + connect \xer_so_ok \xer_so_ok + connect \xer_so \xer_so + connect \n_valid_o \alu_n_valid_o + connect \n_ready_i \alu_n_ready_i + connect \op__insn_type \alu_op__insn_type + connect \op__fn_unit \alu_op__fn_unit + connect \op__imm_data__imm \alu_op__imm_data__imm + connect \op__imm_data__imm_ok \alu_op__imm_data__imm_ok + connect \op__lk \alu_op__lk + connect \op__rc__rc \alu_op__rc__rc + connect \op__rc__rc_ok \alu_op__rc__rc_ok + connect \op__oe__oe \alu_op__oe__oe + connect \op__oe__oe_ok \alu_op__oe__oe_ok + connect \op__invert_a \alu_op__invert_a + connect \op__zero_a \alu_op__zero_a + connect \op__input_carry \alu_op__input_carry + connect \op__invert_out \alu_op__invert_out + connect \op__write_cr__data \alu_op__write_cr__data + connect \op__write_cr__ok \alu_op__write_cr__ok + connect \op__output_carry \alu_op__output_carry + connect \op__is_32bit \alu_op__is_32bit + connect \op__is_signed \alu_op__is_signed + connect \op__data_len \alu_op__data_len + connect \op__insn \alu_op__insn + connect \ra \alu_ra + connect \rb \alu_rb + connect \xer_so$1 \alu_xer_so + connect \p_valid_i \alu_p_valid_i + connect \p_ready_o \alu_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \src_l_q_src + cell \src_l$283 \src_l + connect \rst \rst + connect \clk \clk + connect \s_src \src_l_s_src + connect \r_src \src_l_r_src + connect \q_src \src_l_q_src + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 1 \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_q_opc + cell \opc_l$284 \opc_l + connect \rst \rst + connect \clk \clk + connect \s_opc \opc_l_s_opc + connect \r_opc \opc_l_r_opc + connect \q_opc \opc_l_q_opc + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 5 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 \req_l_r_req + cell \req_l$285 \req_l + connect \rst \rst + connect \clk \clk + connect \q_req \req_l_q_req + connect \s_req \req_l_s_req + connect \r_req \req_l_r_req + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_r_rst + cell \rst_l$286 \rst_l + connect \rst \rst + connect \clk \clk + connect \s_rst \rst_l_s_rst + connect \r_rst \rst_l_r_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_r_rdok$next + cell \rok_l$287 \rok_l + connect \rst \rst + connect \clk \clk + connect \q_rdok \rok_l_q_rdok + connect \s_rdok \rok_l_s_rdok + connect \r_rdok \rok_l_r_rdok + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 1 \alui_l_s_alui + cell \alui_l$288 \alui_l + connect \rst \rst + connect \clk \clk + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 1 \alu_l_s_alu + cell \alu_l$289 \alu_l + connect \rst \rst + connect \clk \clk + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:177" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B \rok_l_q_rdok + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + wire width 3 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \rd__rel + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + wire width 3 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + cell $or $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $4 + connect \B \rd__go + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + cell $reduce_and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $6 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B $3 + connect \Y $9 + end + process $group_0 + assign \all_rd 1'0 + assign \all_rd $9 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + wire width 1 \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:182" + wire width 1 \all_rd_dly$next + process $group_1 + assign \all_rd_dly$next \all_rd_dly + assign \all_rd_dly$next \all_rd + sync init + update \all_rd_dly 1'0 + sync posedge \clk + update \all_rd_dly \all_rd_dly$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" + wire width 1 \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + cell $not $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:185" + cell $and $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B $11 + connect \Y $13 + end + process $group_2 + assign \all_rd_pulse 1'0 + assign \all_rd_pulse $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + wire width 1 \alu_done + process $group_3 + assign \alu_done 1'0 + assign \alu_done \alu_n_valid_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 \alu_done_dly$next + process $group_4 + assign \alu_done_dly$next \alu_done_dly + assign \alu_done_dly$next \alu_done + sync init + update \alu_done_dly 1'0 + sync posedge \clk + update \alu_done_dly \alu_done_dly$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" + wire width 1 \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + cell $not $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194" + cell $and $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B $15 + connect \Y $17 + end + process $group_5 + assign \alu_pulse 1'0 + assign \alu_pulse $17 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" + wire width 5 \alu_pulsem + process $group_6 + assign \alu_pulsem 5'00000 + assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 5 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 5 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + wire width 5 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200" + cell $and $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \wr__go + connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o } + connect \Y $19 + end + process $group_7 + assign \prev_wr_go$next \prev_wr_go + assign \prev_wr_go$next $19 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \prev_wr_go$next 5'00000 + end + sync init + update \prev_wr_go 5'00000 + sync posedge \clk + update \prev_wr_go \prev_wr_go$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 \done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + wire width 5 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93" + wire width 5 \wrmask + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \wrmask + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + wire width 5 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + cell $and $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \wr__rel + connect \B $23 + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + cell $reduce_bool $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A $25 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + cell $not $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $22 + connect \Y $21 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:208" + cell $and $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B $21 + connect \Y $29 + end + process $group_8 + assign \done_o 1'0 + assign \done_o $29 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:205" + wire width 1 \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \wr__go + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + cell $reduce_bool $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + cell $or $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $31 + connect \B $33 + connect \Y $35 + end + process $group_9 + assign \wr_any 1'0 + assign \wr_any $35 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 1 \req_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + cell $not $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_n_ready_i + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + cell $and $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B $37 + connect \Y $39 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire width 5 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + cell $and $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \req_l_q_req + connect \B \wrmask + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + cell $eq $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $41 + connect \B 1'0 + connect \Y $43 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + cell $and $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $39 + connect \B $43 + connect \Y $45 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $eq $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrmask + connect \B 1'0 + connect \Y $47 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $47 + connect \B \alu_n_ready_i + connect \Y $49 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $49 + connect \B \alu_n_valid_o + connect \Y $51 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $51 + connect \B \busy_o + connect \Y $53 + end + process $group_10 + assign \req_done 1'0 + assign \req_done $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + switch { $53 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + case 1'1 + assign \req_done 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220" + wire width 1 \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + cell $or $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \go_die_i + connect \Y $55 + end + process $group_11 + assign \reset 1'0 + assign \reset $55 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" + wire width 1 \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + cell $or $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \issue_i + connect \B \go_die_i + connect \Y $57 + end + process $group_12 + assign \rst_r 1'0 + assign \rst_r $57 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 5 \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire width 5 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + cell $or $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \wr__go + connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i } + connect \Y $59 + end + process $group_13 + assign \reset_w 5'00000 + assign \reset_w $59 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire width 3 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + cell $or $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \rd__go + connect \B { \go_die_i \go_die_i \go_die_i } + connect \Y $61 + end + process $group_14 + assign \reset_r 3'000 + assign \reset_r $61 + sync init + end + process $group_15 + assign \rok_l_s_rdok 1'0 + assign \rok_l_s_rdok \issue_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $and $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_n_valid_o + connect \B \busy_o + connect \Y $63 + end + process $group_16 + assign \rok_l_r_rdok$next \rok_l_r_rdok + assign \rok_l_r_rdok$next $63 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \rok_l_r_rdok$next 1'1 + end + sync init + update \rok_l_r_rdok 1'1 + sync posedge \clk + update \rok_l_r_rdok \rok_l_r_rdok$next + end + process $group_17 + assign \rst_l_s_rst 1'0 + assign \rst_l_s_rst \all_rd + sync init + end + process $group_18 + assign \rst_l_r_rst 1'1 + assign \rst_l_r_rst \rst_r + sync init + end + process $group_19 + assign \opc_l_s_opc$next \opc_l_s_opc + assign \opc_l_s_opc$next \issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \opc_l_s_opc$next 1'0 + end + sync init + update \opc_l_s_opc 1'0 + sync posedge \clk + update \opc_l_s_opc \opc_l_s_opc$next + end + process $group_20 + assign \opc_l_r_opc$next \opc_l_r_opc + assign \opc_l_r_opc$next \req_done + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \opc_l_r_opc$next 1'1 + end + sync init + update \opc_l_r_opc 1'1 + sync posedge \clk + update \opc_l_r_opc \opc_l_r_opc$next + end + process $group_21 + assign \src_l_s_src$next \src_l_s_src + assign \src_l_s_src$next { \issue_i \issue_i \issue_i } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \src_l_s_src$next 3'000 + end + sync init + update \src_l_s_src 3'000 + sync posedge \clk + update \src_l_s_src \src_l_s_src$next + end + process $group_22 + assign \src_l_r_src$next \src_l_r_src + assign \src_l_r_src$next \reset_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \src_l_r_src$next 3'111 + end + sync init + update \src_l_r_src 3'111 + sync posedge \clk + update \src_l_r_src \src_l_r_src$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + wire width 5 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:246" + cell $and $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \alu_pulsem + connect \B \wrmask + connect \Y $65 + end + process $group_23 + assign \req_l_s_req 5'00000 + assign \req_l_s_req $65 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + wire width 5 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + cell $or $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $67 + end + process $group_24 + assign \req_l_r_req 5'11111 + assign \req_l_r_req $67 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 7 \oper_l__insn_type + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 7 \oper_l__insn_type$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 10 \oper_l__fn_unit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 10 \oper_l__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 64 \oper_l__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 64 \oper_l__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__lk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__lk$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__rc__rc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__oe__oe + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__invert_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__invert_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__zero_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 2 \oper_l__input_carry + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 2 \oper_l__input_carry$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__invert_out + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__invert_out$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 3 \oper_l__write_cr__data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 3 \oper_l__write_cr__data$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__write_cr__ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__output_carry + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__output_carry$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__is_32bit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__is_signed + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \oper_l__is_signed$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 4 \oper_l__data_len + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 4 \oper_l__data_len$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 32 \oper_l__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 32 \oper_l__insn$next + process $group_25 + assign \oper_l__insn_type$next \oper_l__insn_type + assign \oper_l__fn_unit$next \oper_l__fn_unit + assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm + assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok + assign \oper_l__lk$next \oper_l__lk + assign \oper_l__rc__rc$next \oper_l__rc__rc + assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok + assign \oper_l__oe__oe$next \oper_l__oe__oe + assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok + assign \oper_l__invert_a$next \oper_l__invert_a + assign \oper_l__zero_a$next \oper_l__zero_a + assign \oper_l__input_carry$next \oper_l__input_carry + assign \oper_l__invert_out$next \oper_l__invert_out + assign \oper_l__write_cr__data$next \oper_l__write_cr__data + assign \oper_l__write_cr__ok$next \oper_l__write_cr__ok + assign \oper_l__output_carry$next \oper_l__output_carry + assign \oper_l__is_32bit$next \oper_l__is_32bit + assign \oper_l__is_signed$next \oper_l__is_signed + assign \oper_l__data_len$next \oper_l__data_len + assign \oper_l__insn$next \oper_l__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { \issue_i } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oper_l__imm_data__imm_ok$next 1'0 + assign \oper_l__rc__rc$next 1'0 + assign \oper_l__rc__rc_ok$next 1'0 + assign \oper_l__oe__oe$next 1'0 + assign \oper_l__oe__oe_ok$next 1'0 + assign \oper_l__write_cr__data$next 3'000 + assign \oper_l__write_cr__ok$next 1'0 + assign \oper_l__insn$next 32'00000000000000000000000000000000 + end + sync init + update \oper_l__insn_type 7'0000000 + update \oper_l__fn_unit 10'0000000000 + update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \oper_l__imm_data__imm_ok 1'0 + update \oper_l__lk 1'0 + update \oper_l__rc__rc 1'0 + update \oper_l__rc__rc_ok 1'0 + update \oper_l__oe__oe 1'0 + update \oper_l__oe__oe_ok 1'0 + update \oper_l__invert_a 1'0 + update \oper_l__zero_a 1'0 + update \oper_l__input_carry 2'00 + update \oper_l__invert_out 1'0 + update \oper_l__write_cr__data 3'000 + update \oper_l__write_cr__ok 1'0 + update \oper_l__output_carry 1'0 + update \oper_l__is_32bit 1'0 + update \oper_l__is_signed 1'0 + update \oper_l__data_len 4'0000 + update \oper_l__insn 32'00000000000000000000000000000000 + sync posedge \clk + update \oper_l__insn_type \oper_l__insn_type$next + update \oper_l__fn_unit \oper_l__fn_unit$next + update \oper_l__imm_data__imm \oper_l__imm_data__imm$next + update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next + update \oper_l__lk \oper_l__lk$next + update \oper_l__rc__rc \oper_l__rc__rc$next + update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next + update \oper_l__oe__oe \oper_l__oe__oe$next + update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next + update \oper_l__invert_a \oper_l__invert_a$next + update \oper_l__zero_a \oper_l__zero_a$next + update \oper_l__input_carry \oper_l__input_carry$next + update \oper_l__invert_out \oper_l__invert_out$next + update \oper_l__write_cr__data \oper_l__write_cr__data$next + update \oper_l__write_cr__ok \oper_l__write_cr__ok$next + update \oper_l__output_carry \oper_l__output_carry$next + update \oper_l__is_32bit \oper_l__is_32bit$next + update \oper_l__is_signed \oper_l__is_signed$next + update \oper_l__data_len \oper_l__data_len$next + update \oper_l__insn \oper_l__insn$next + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \oper_r__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 \oper_r__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \oper_r__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \oper_r__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \oper_r__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \oper_r__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \oper_r__insn + process $group_45 + assign \oper_r__insn_type 7'0000000 + assign \oper_r__fn_unit 10'0000000000 + assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oper_r__imm_data__imm_ok 1'0 + assign \oper_r__lk 1'0 + assign \oper_r__rc__rc 1'0 + assign \oper_r__rc__rc_ok 1'0 + assign \oper_r__oe__oe 1'0 + assign \oper_r__oe__oe_ok 1'0 + assign \oper_r__invert_a 1'0 + assign \oper_r__zero_a 1'0 + assign \oper_r__input_carry 2'00 + assign \oper_r__invert_out 1'0 + assign \oper_r__write_cr__data 3'000 + assign \oper_r__write_cr__ok 1'0 + assign \oper_r__output_carry 1'0 + assign \oper_r__is_32bit 1'0 + assign \oper_r__is_signed 1'0 + assign \oper_r__data_len 4'0000 + assign \oper_r__insn 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { \issue_i } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } \oper_l__invert_out \oper_l__input_carry \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 64 \data_r0_l__o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 64 \data_r0_l__o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \data_r0_l__o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \data_r0_l__o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $69 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $69 + end + process $group_65 + assign \data_r0_l__o$next \data_r0_l__o + assign \data_r0_l__o_ok$next \data_r0_l__o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { $69 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \data_r0_l__o_ok$next 1'0 + end + sync init + update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r0_l__o_ok 1'0 + sync posedge \clk + update \data_r0_l__o \data_r0_l__o$next + update \data_r0_l__o_ok \data_r0_l__o_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $71 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $71 + end + process $group_67 + assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r0__o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { $71 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign { \data_r0__o_ok \data_r0__o } { \o_ok \o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + assign { \data_r0__o_ok \data_r0__o } { \data_r0_l__o_ok \data_r0_l__o } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 4 \data_r1_l__cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 4 \data_r1_l__cr_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \data_r1_l__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \data_r1_l__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $73 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $73 + end + process $group_69 + assign \data_r1_l__cr_a$next \data_r1_l__cr_a + assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { $73 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \cr_a } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \data_r1_l__cr_a_ok$next 1'0 + end + sync init + update \data_r1_l__cr_a 4'0000 + update \data_r1_l__cr_a_ok 1'0 + sync posedge \clk + update \data_r1_l__cr_a \data_r1_l__cr_a$next + update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" + wire width 1 \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $75 + end + process $group_71 + assign \data_r1__cr_a 4'0000 + assign \data_r1__cr_a_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { $75 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign { \data_r1__cr_a_ok \data_r1__cr_a } { \cr_a_ok \cr_a } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + assign { \data_r1__cr_a_ok \data_r1__cr_a } { \data_r1_l__cr_a_ok \data_r1_l__cr_a } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 2 \data_r2_l__xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 2 \data_r2_l__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \data_r2_l__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \data_r2_l__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $77 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $77 + end + process $group_73 + assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca + assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { $77 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \xer_ca } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \data_r2_l__xer_ca_ok$next 1'0 + end + sync init + update \data_r2_l__xer_ca 2'00 + update \data_r2_l__xer_ca_ok 1'0 + sync posedge \clk + update \data_r2_l__xer_ca \data_r2_l__xer_ca$next + update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" + wire width 1 \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $79 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $79 + end + process $group_75 + assign \data_r2__xer_ca 2'00 + assign \data_r2__xer_ca_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { $79 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \xer_ca_ok \xer_ca } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + assign { \data_r2__xer_ca_ok \data_r2__xer_ca } { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 2 \data_r3_l__xer_ov + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 2 \data_r3_l__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \data_r3_l__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \data_r3_l__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $81 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $81 + end + process $group_77 + assign \data_r3_l__xer_ov$next \data_r3_l__xer_ov + assign \data_r3_l__xer_ov_ok$next \data_r3_l__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { $81 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign { \data_r3_l__xer_ov_ok$next \data_r3_l__xer_ov$next } { \xer_ov_ok \xer_ov } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \data_r3_l__xer_ov_ok$next 1'0 + end + sync init + update \data_r3_l__xer_ov 2'00 + update \data_r3_l__xer_ov_ok 1'0 + sync posedge \clk + update \data_r3_l__xer_ov \data_r3_l__xer_ov$next + update \data_r3_l__xer_ov_ok \data_r3_l__xer_ov_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" + wire width 2 \data_r3__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" + wire width 1 \data_r3__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $83 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $83 + end + process $group_79 + assign \data_r3__xer_ov 2'00 + assign \data_r3__xer_ov_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { $83 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign { \data_r3__xer_ov_ok \data_r3__xer_ov } { \xer_ov_ok \xer_ov } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + assign { \data_r3__xer_ov_ok \data_r3__xer_ov } { \data_r3_l__xer_ov_ok \data_r3_l__xer_ov } + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \data_r4_l__xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \data_r4_l__xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \data_r4_l__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:36" + wire width 1 \data_r4_l__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $85 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $85 + end + process $group_81 + assign \data_r4_l__xer_so$next \data_r4_l__xer_so + assign \data_r4_l__xer_so_ok$next \data_r4_l__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { $85 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign { \data_r4_l__xer_so_ok$next \data_r4_l__xer_so$next } { \xer_so_ok \xer_so } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \data_r4_l__xer_so_ok$next 1'0 + end + sync init + update \data_r4_l__xer_so 1'0 + update \data_r4_l__xer_so_ok 1'0 + sync posedge \clk + update \data_r4_l__xer_so \data_r4_l__xer_so$next + update \data_r4_l__xer_so_ok \data_r4_l__xer_so_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" + wire width 1 \data_r4__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:261" + wire width 1 \data_r4__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $87 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $87 + end + process $group_83 + assign \data_r4__xer_so 1'0 + assign \data_r4__xer_so_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { $87 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign { \data_r4__xer_so_ok \data_r4__xer_so } { \xer_so_ok \xer_so } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + assign { \data_r4__xer_so_ok \data_r4__xer_so } { \data_r4_l__xer_so_ok \data_r4_l__xer_so } + end + sync init + end + process $group_85 + assign \wrmask 5'00000 + assign \wrmask { \data_r4__xer_so_ok \data_r3__xer_ov_ok \data_r2__xer_ca_ok \data_r1__cr_a_ok \data_r0__o_ok } + sync init + end + process $group_86 + assign \alu_op__insn_type 7'0000000 + assign \alu_op__fn_unit 10'0000000000 + assign \alu_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_op__imm_data__imm_ok 1'0 + assign \alu_op__lk 1'0 + assign \alu_op__rc__rc 1'0 + assign \alu_op__rc__rc_ok 1'0 + assign \alu_op__oe__oe 1'0 + assign \alu_op__oe__oe_ok 1'0 + assign \alu_op__invert_a 1'0 + assign \alu_op__zero_a 1'0 + assign \alu_op__input_carry 2'00 + assign \alu_op__invert_out 1'0 + assign \alu_op__write_cr__data 3'000 + assign \alu_op__write_cr__ok 1'0 + assign \alu_op__output_carry 1'0 + assign \alu_op__is_32bit 1'0 + assign \alu_op__is_signed 1'0 + assign \alu_op__data_len 4'0000 + assign \alu_op__insn 32'00000000000000000000000000000000 + assign { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry { \alu_op__write_cr__ok \alu_op__write_cr__data } \alu_op__invert_out \alu_op__input_carry \alu_op__zero_a \alu_op__invert_a { \alu_op__oe__oe_ok \alu_op__oe__oe } { \alu_op__rc__rc_ok \alu_op__rc__rc } \alu_op__lk { \alu_op__imm_data__imm_ok \alu_op__imm_data__imm } \alu_op__fn_unit \alu_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" + wire width 1 \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" + cell $mux $90 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \oper_r__zero_a + connect \Y $89 + end + process $group_106 + assign \src_sel 1'0 + assign \src_sel $89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + wire width 64 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + cell $mux $92 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \oper_r__zero_a + connect \Y $91 + end + process $group_107 + assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm $91 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" + wire width 1 \src_sel$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" + wire width 1 $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" + cell $mux $95 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \oper_r__imm_data__imm_ok + connect \Y $94 + end + process $group_108 + assign \src_sel$93 1'0 + assign \src_sel$93 $94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:156" + wire width 64 \src_or_imm$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + wire width 64 $97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + cell $mux $98 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \oper_r__imm_data__imm + connect \S \oper_r__imm_data__imm_ok + connect \Y $97 + end + process $group_109 + assign \src_or_imm$96 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm$96 $97 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + wire width 64 \src_r0$next + process $group_110 + assign \src_r0$next \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { \src_sel } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign \src_r0$next \src_or_imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + end + sync init + update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \src_r0 \src_r0$next + end + process $group_111 + assign \alu_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { \src_sel } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign \alu_ra \src_or_imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + assign \alu_ra \src_r0 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + wire width 64 \src_r1$next + process $group_112 + assign \src_r1$next \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { \src_sel$93 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign \src_r1$next \src_or_imm$96 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + end + sync init + update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \src_r1 \src_r1$next + end + process $group_113 + assign \alu_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { \src_sel$93 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign \alu_rb \src_or_imm$96 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + assign \alu_rb \src_r1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + wire width 1 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:38" + wire width 1 \src_r2$next + process $group_114 + assign \src_r2$next \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { \src_l_q_src [2] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign \src_r2$next \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + end + sync init + update \src_r2 1'0 + sync posedge \clk + update \src_r2 \src_r2$next + end + process $group_115 + assign \alu_xer_so 1'0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + switch { \src_l_q_src [2] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + case 1'1 + assign \alu_xer_so \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:42" + case + assign \alu_xer_so \src_r2 + end + sync init + end + process $group_116 + assign \alu_p_valid_i 1'0 + assign \alu_p_valid_i \alui_l_q_alui + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" + wire width 1 $99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:320" + cell $and $100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_p_ready_o + connect \B \alui_l_q_alui + connect \Y $99 + end + process $group_117 + assign \alui_l_r_alui$next \alui_l_r_alui + assign \alui_l_r_alui$next $99 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \alui_l_r_alui$next 1'1 + end + sync init + update \alui_l_r_alui 1'1 + sync posedge \clk + update \alui_l_r_alui \alui_l_r_alui$next + end + process $group_118 + assign \alui_l_s_alui 1'0 + assign \alui_l_s_alui \all_rd_pulse + sync init + end + process $group_119 + assign \alu_n_ready_i 1'0 + assign \alu_n_ready_i \alu_l_q_alu + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + wire width 1 $101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_n_valid_o + connect \B \alu_l_q_alu + connect \Y $101 + end + process $group_120 + assign \alu_l_r_alu$next \alu_l_r_alu + assign \alu_l_r_alu$next $101 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \alu_l_r_alu$next 1'1 + end + sync init + update \alu_l_r_alu 1'1 + sync posedge \clk + update \alu_l_r_alu \alu_l_r_alu$next + end + process $group_121 + assign \alu_l_s_alu 1'0 + assign \alu_l_s_alu \all_rd_pulse + sync init + end + process $group_122 + assign \busy_o 1'0 + assign \busy_o \opc_l_q_opc + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" + wire width 3 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" + cell $and $104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \busy_o \busy_o \busy_o } + connect \Y $103 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" + cell $not $106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oper_r__zero_a + connect \Y $105 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" + wire width 1 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:163" + cell $not $108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oper_r__imm_data__imm_ok + connect \Y $107 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" + wire width 3 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" + cell $and $110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $103 + connect \B { 1'1 $107 $105 } + connect \Y $109 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" + wire width 3 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" + cell $not $112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \rdmaskn + connect \Y $111 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" + wire width 3 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:340" + cell $and $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $109 + connect \B $111 + connect \Y $113 + end + process $group_123 + assign \rd__rel 3'000 + assign \rd__rel $113 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" + wire width 1 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" + cell $and $116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B \shadown_i + connect \Y $115 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" + wire width 1 $117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" + cell $and $118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B \shadown_i + connect \Y $117 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" + wire width 1 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" + cell $and $120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B \shadown_i + connect \Y $119 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" + wire width 1 $121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" + cell $and $122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B \shadown_i + connect \Y $121 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" + wire width 1 $123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:343" + cell $and $124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B \shadown_i + connect \Y $123 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 5 $125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \req_l_q_req + connect \B { $115 $117 $119 $121 $123 } + connect \Y $125 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 5 $127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $125 + connect \B \wrmask + connect \Y $127 + end + process $group_124 + assign \wr__rel 5'00000 + assign \wr__rel $127 + sync init + end + process $group_125 + assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + switch { \wr__go [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + case 1'1 + assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 4 \dest2_o + process $group_126 + assign \dest2_o 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + switch { \wr__go [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + case 1'1 + assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 2 \dest3_o + process $group_127 + assign \dest3_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + switch { \wr__go [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + case 1'1 + assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 2 \dest4_o + process $group_128 + assign \dest4_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + switch { \wr__go [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + case 1'1 + assign \dest4_o { \data_r3__xer_ov_ok \data_r3__xer_ov } [1:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 1 \dest5_o + process $group_129 + assign \dest5_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + switch { \wr__go [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:348" + case 1'1 + assign \dest5_o { \data_r4__xer_so_ok \data_r4__xer_so } [0] + end + sync init + end +end +attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.p" -module \p$46 +module \p$291 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -65476,7 +184836,7 @@ module \p$46 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.n" -module \n$47 +module \n$292 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -65504,7 +184864,7 @@ module \n$47 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.p" -module \p$49 +module \p$294 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -65532,7 +184892,7 @@ module \p$49 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.n" -module \n$50 +module \n$295 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -65560,7 +184920,7 @@ module \n$50 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.input" -module \input$51 +module \input$296 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -71872,7 +191232,7 @@ module \clz end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.main" -module \main$52 +module \main$297 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -73670,7 +193030,7 @@ module \main$52 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe.output" -module \output$53 +module \output$298 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -74236,7 +193596,7 @@ module \output$53 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu.pipe" -module \pipe$48 +module \pipe$293 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -74577,11 +193937,11 @@ module \pipe$48 wire width 1 output 55 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \xer_ca_ok$next - cell \p$49 \p + cell \p$294 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$50 \n + cell \n$295 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -74851,7 +194211,7 @@ module \pipe$48 wire width 64 \input_ra$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 \input_rb$44 - cell \input$51 \input + cell \input$296 \input connect \muxid \input_muxid connect \op__insn_type \input_op__insn_type connect \op__fn_unit \input_op__fn_unit @@ -75165,7 +194525,7 @@ module \pipe$48 wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \main_o_ok - cell \main$52 \main + cell \main$297 \main connect \muxid \main_muxid connect \op__insn_type \main_op__insn_type connect \op__fn_unit \main_op__fn_unit @@ -75491,7 +194851,7 @@ module \pipe$48 wire width 2 \output_xer_ca$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \output_xer_ca_ok - cell \output$53 \output + cell \output$298 \output connect \muxid \output_muxid connect \op__insn_type \output_op__insn_type connect \op__fn_unit \output_op__fn_unit @@ -76120,7 +195480,7 @@ module \pipe$48 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu" -module \alu$45 +module \alu$290 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -76276,11 +195636,11 @@ module \alu$45 wire width 1 input 32 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 output 33 \p_ready_o - cell \p$46 \p + cell \p$291 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$47 \n + cell \n$292 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -76566,7 +195926,7 @@ module \alu$45 wire width 2 \pipe_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \pipe_xer_ca_ok - cell \pipe$48 \pipe + cell \pipe$293 \pipe connect \rst \rst connect \clk \clk connect \p_valid_i \pipe_p_valid_i @@ -76865,7 +196225,7 @@ module \alu$45 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l" -module \src_l$54 +module \src_l$299 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -77010,7 +196370,7 @@ module \src_l$54 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l" -module \opc_l$55 +module \opc_l$300 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -77155,7 +196515,7 @@ module \opc_l$55 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l" -module \req_l$56 +module \req_l$301 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -77300,7 +196660,7 @@ module \req_l$56 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l" -module \rst_l$57 +module \rst_l$302 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -77445,7 +196805,7 @@ module \rst_l$57 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l" -module \rok_l$58 +module \rok_l$303 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -77590,7 +196950,7 @@ module \rok_l$58 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l" -module \alui_l$59 +module \alui_l$304 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -77735,7 +197095,7 @@ module \alui_l$59 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l" -module \alu_l$60 +module \alu_l$305 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -78187,7 +197547,7 @@ module \logical0 wire width 1 \alu_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 \alu_p_ready_o - cell \alu$45 \alu + cell \alu$290 \alu connect \rst \rst connect \clk \clk connect \o_ok \o_ok @@ -78233,7 +197593,7 @@ module \logical0 wire width 2 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 2 \src_l_q_src - cell \src_l$54 \src_l + cell \src_l$299 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src @@ -78250,7 +197610,7 @@ module \logical0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \opc_l_q_opc - cell \opc_l$55 \opc_l + cell \opc_l$300 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc @@ -78263,7 +197623,7 @@ module \logical0 wire width 3 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 \req_l_r_req - cell \req_l$56 \req_l + cell \req_l$301 \req_l connect \rst \rst connect \clk \clk connect \q_req \req_l_q_req @@ -78274,7 +197634,7 @@ module \logical0 wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \rst_l_r_rst - cell \rst_l$57 \rst_l + cell \rst_l$302 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst @@ -78288,7 +197648,7 @@ module \logical0 wire width 1 \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \rok_l_r_rdok$next - cell \rok_l$58 \rok_l + cell \rok_l$303 \rok_l connect \rst \rst connect \clk \clk connect \q_rdok \rok_l_q_rdok @@ -78303,7 +197663,7 @@ module \logical0 wire width 1 \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" wire width 1 \alui_l_s_alui - cell \alui_l$59 \alui_l + cell \alui_l$304 \alui_l connect \rst \rst connect \clk \clk connect \q_alui \alui_l_q_alui @@ -78318,7 +197678,7 @@ module \logical0 wire width 1 \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" wire width 1 \alu_l_s_alu - cell \alu_l$60 \alu_l + cell \alu_l$305 \alu_l connect \rst \rst connect \clk \clk connect \q_alu \alu_l_q_alu @@ -79910,7 +199270,7 @@ module \logical0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.p" -module \p$62 +module \p$307 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -79938,7 +199298,7 @@ module \p$62 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.n" -module \n$63 +module \n$308 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -79966,7 +199326,7 @@ module \n$63 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.p" -module \p$65 +module \p$310 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -79994,7 +199354,7 @@ module \p$65 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.n" -module \n$66 +module \n$311 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -80022,7 +199382,7 @@ module \n$66 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.input" -module \input$67 +module \input$312 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -81190,7 +200550,7 @@ module \rotator end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.main" -module \main$68 +module \main$313 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -81667,7 +201027,7 @@ module \main$68 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe.output" -module \output$69 +module \output$314 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -82190,7 +201550,7 @@ module \output$69 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu.pipe" -module \pipe$64 +module \pipe$309 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -82517,11 +201877,11 @@ module \pipe$64 wire width 1 output 51 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \xer_ca_ok$next - cell \p$65 \p + cell \p$310 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$66 \n + cell \n$311 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -82787,7 +202147,7 @@ module \pipe$64 wire width 64 \input_rc$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 2 \input_xer_ca$41 - cell \input$67 \input + cell \input$312 \input connect \muxid \input_muxid connect \op__insn_type \input_op__insn_type connect \op__fn_unit \input_op__fn_unit @@ -83091,7 +202451,7 @@ module \pipe$64 wire width 1 \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 2 \main_xer_ca - cell \main$68 \main + cell \main$313 \main connect \muxid \main_muxid connect \op__insn_type \main_op__insn_type connect \op__fn_unit \main_op__fn_unit @@ -83401,7 +202761,7 @@ module \pipe$64 wire width 2 \output_xer_ca$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \output_xer_ca_ok - cell \output$69 \output + cell \output$314 \output connect \muxid \output_muxid connect \op__insn_type \output_op__insn_type connect \op__fn_unit \output_op__fn_unit @@ -84016,7 +203376,7 @@ module \pipe$64 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu" -module \alu$61 +module \alu$306 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -84170,11 +203530,11 @@ module \alu$61 wire width 1 input 31 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 output 32 \p_ready_o - cell \p$62 \p + cell \p$307 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$63 \n + cell \n$308 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -84452,7 +203812,7 @@ module \alu$61 wire width 2 \pipe_xer_ca$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \pipe_xer_ca_ok - cell \pipe$64 \pipe + cell \pipe$309 \pipe connect \rst \rst connect \clk \clk connect \p_valid_i \pipe_p_valid_i @@ -84745,7 +204105,7 @@ module \alu$61 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l" -module \src_l$70 +module \src_l$315 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -84890,7 +204250,7 @@ module \src_l$70 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l" -module \opc_l$71 +module \opc_l$316 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -85035,7 +204395,7 @@ module \opc_l$71 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l" -module \req_l$72 +module \req_l$317 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -85180,7 +204540,7 @@ module \req_l$72 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l" -module \rst_l$73 +module \rst_l$318 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -85325,7 +204685,7 @@ module \rst_l$73 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l" -module \rok_l$74 +module \rok_l$319 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -85470,7 +204830,7 @@ module \rok_l$74 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l" -module \alui_l$75 +module \alui_l$320 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -85615,7 +204975,7 @@ module \alui_l$75 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l" -module \alu_l$76 +module \alu_l$321 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -86063,7 +205423,7 @@ module \shiftrot0 wire width 1 \alu_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 \alu_p_ready_o - cell \alu$61 \alu + cell \alu$306 \alu connect \rst \rst connect \clk \clk connect \o_ok \o_ok @@ -86108,7 +205468,7 @@ module \shiftrot0 wire width 4 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 4 \src_l_q_src - cell \src_l$70 \src_l + cell \src_l$315 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src @@ -86125,7 +205485,7 @@ module \shiftrot0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \opc_l_q_opc - cell \opc_l$71 \opc_l + cell \opc_l$316 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc @@ -86138,7 +205498,7 @@ module \shiftrot0 wire width 3 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 3 \req_l_r_req - cell \req_l$72 \req_l + cell \req_l$317 \req_l connect \rst \rst connect \clk \clk connect \q_req \req_l_q_req @@ -86149,7 +205509,7 @@ module \shiftrot0 wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \rst_l_r_rst - cell \rst_l$73 \rst_l + cell \rst_l$318 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst @@ -86163,7 +205523,7 @@ module \shiftrot0 wire width 1 \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \rok_l_r_rdok$next - cell \rok_l$74 \rok_l + cell \rok_l$319 \rok_l connect \rst \rst connect \clk \clk connect \q_rdok \rok_l_q_rdok @@ -86178,7 +205538,7 @@ module \shiftrot0 wire width 1 \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" wire width 1 \alui_l_s_alui - cell \alui_l$75 \alui_l + cell \alui_l$320 \alui_l connect \rst \rst connect \clk \clk connect \q_alui \alui_l_q_alui @@ -86193,7 +205553,7 @@ module \shiftrot0 wire width 1 \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" wire width 1 \alu_l_s_alu - cell \alu_l$76 \alu_l + cell \alu_l$321 \alu_l connect \rst \rst connect \clk \clk connect \q_alu \alu_l_q_alu @@ -87772,7 +207132,7 @@ module \shiftrot0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l" -module \opc_l$77 +module \opc_l$322 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -87917,7 +207277,7 @@ module \opc_l$77 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l" -module \src_l$78 +module \src_l$323 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -88062,7 +207422,7 @@ module \src_l$78 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l" -module \alu_l$79 +module \alu_l$324 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -88932,7 +208292,7 @@ module \upd_l end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l" -module \rst_l$80 +module \rst_l$325 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -89246,7 +208606,7 @@ module \ldst0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \opc_l_q_opc - cell \opc_l$77 \opc_l + cell \opc_l$322 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc @@ -89263,7 +208623,7 @@ module \ldst0 wire width 3 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 \src_l_q_src - cell \src_l$78 \src_l + cell \src_l$323 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src @@ -89276,7 +208636,7 @@ module \ldst0 wire width 1 \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \alu_l_q_alu - cell \alu_l$79 \alu_l + cell \alu_l$324 \alu_l connect \rst \rst connect \clk \clk connect \s_alu \alu_l_s_alu @@ -89365,7 +208725,7 @@ module \ldst0 wire width 1 \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_q_rst - cell \rst_l$80 \rst_l + cell \rst_l$325 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst @@ -91570,8 +210930,109 @@ module \fus attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 7 input 51 \oper_i__insn_type$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 7 input 51 \oper_i__insn_type$17 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 10 input 52 \oper_i__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 32 input 53 \oper_i__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 1 input 54 \oper_i__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 4 input 55 \oper_i__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 13 input 56 \oper_i__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" + wire width 1 input 57 \issue_i$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" + wire width 1 output 58 \busy_o$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" + wire width 6 input 59 \rdmaskn$23 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 60 \oper_i__insn_type$24 attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -91583,22 +211044,54 @@ module \fus attribute \enum_value_0010000000 "TRAP" attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 input 52 \oper_i__fn_unit$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 32 input 53 \oper_i__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 1 input 54 \oper_i__is_32bit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 input 55 \oper_i__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 13 input 56 \oper_i__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 input 61 \oper_i__fn_unit$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 62 \oper_i__imm_data__imm$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 63 \oper_i__imm_data__imm_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 64 \oper_i__lk$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 65 \oper_i__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 66 \oper_i__rc__rc_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 67 \oper_i__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 68 \oper_i__oe__oe_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 69 \oper_i__invert_a$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 70 \oper_i__zero_a$34 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 71 \oper_i__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 72 \oper_i__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 73 \oper_i__write_cr__data$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 74 \oper_i__write_cr__ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 75 \oper_i__output_carry$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 76 \oper_i__is_32bit$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 77 \oper_i__is_signed$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 78 \oper_i__data_len$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 79 \oper_i__insn$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 input 57 \issue_i$21 + wire width 1 input 80 \issue_i$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 58 \busy_o$22 + wire width 1 output 81 \busy_o$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 6 input 59 \rdmaskn$23 + wire width 3 input 82 \rdmaskn$46 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -91672,7 +211165,7 @@ module \fus attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 7 input 60 \oper_i__insn_type$24 + wire width 7 input 83 \oper_i__insn_type$47 attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -91685,53 +211178,53 @@ module \fus attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 input 61 \oper_i__fn_unit$25 + wire width 10 input 84 \oper_i__fn_unit$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 64 input 62 \oper_i__imm_data__imm$26 + wire width 64 input 85 \oper_i__imm_data__imm$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 63 \oper_i__imm_data__imm_ok$27 + wire width 1 input 86 \oper_i__imm_data__imm_ok$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 64 \oper_i__lk$28 + wire width 1 input 87 \oper_i__lk$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 65 \oper_i__rc__rc$29 + wire width 1 input 88 \oper_i__rc__rc$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 66 \oper_i__rc__rc_ok$30 + wire width 1 input 89 \oper_i__rc__rc_ok$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 67 \oper_i__oe__oe$31 + wire width 1 input 90 \oper_i__oe__oe$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 68 \oper_i__oe__oe_ok$32 + wire width 1 input 91 \oper_i__oe__oe_ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 69 \oper_i__invert_a$33 + wire width 1 input 92 \oper_i__invert_a$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 70 \oper_i__zero_a$34 + wire width 1 input 93 \oper_i__zero_a$57 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 2 input 71 \oper_i__input_carry$35 + wire width 2 input 94 \oper_i__input_carry$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 72 \oper_i__invert_out$36 + wire width 1 input 95 \oper_i__invert_out$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 3 input 73 \oper_i__write_cr__data$37 + wire width 3 input 96 \oper_i__write_cr__data$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 74 \oper_i__write_cr__ok$38 + wire width 1 input 97 \oper_i__write_cr__ok$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 75 \oper_i__output_carry$39 + wire width 1 input 98 \oper_i__output_carry$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 76 \oper_i__is_32bit$40 + wire width 1 input 99 \oper_i__is_32bit$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 77 \oper_i__is_signed$41 + wire width 1 input 100 \oper_i__is_signed$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 4 input 78 \oper_i__data_len$42 + wire width 4 input 101 \oper_i__data_len$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 32 input 79 \oper_i__insn$43 + wire width 32 input 102 \oper_i__insn$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 input 80 \issue_i$44 + wire width 1 input 103 \issue_i$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 81 \busy_o$45 + wire width 1 output 104 \busy_o$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 2 input 82 \rdmaskn$46 + wire width 2 input 105 \rdmaskn$69 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -91805,7 +211298,7 @@ module \fus attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 7 input 83 \oper_i__insn_type$47 + wire width 7 input 106 \oper_i__insn_type$70 attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -91818,47 +211311,47 @@ module \fus attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 input 84 \oper_i__fn_unit$48 + wire width 10 input 107 \oper_i__fn_unit$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 64 input 85 \oper_i__imm_data__imm$49 + wire width 64 input 108 \oper_i__imm_data__imm$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 86 \oper_i__imm_data__imm_ok$50 + wire width 1 input 109 \oper_i__imm_data__imm_ok$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 87 \oper_i__rc__rc$51 + wire width 1 input 110 \oper_i__rc__rc$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 88 \oper_i__rc__rc_ok$52 + wire width 1 input 111 \oper_i__rc__rc_ok$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 89 \oper_i__oe__oe$53 + wire width 1 input 112 \oper_i__oe__oe$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 90 \oper_i__oe__oe_ok$54 + wire width 1 input 113 \oper_i__oe__oe_ok$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 3 input 91 \oper_i__write_cr__data$55 + wire width 3 input 114 \oper_i__write_cr__data$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 92 \oper_i__write_cr__ok$56 + wire width 1 input 115 \oper_i__write_cr__ok$79 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 2 input 93 \oper_i__input_carry$57 + wire width 2 input 116 \oper_i__input_carry$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 94 \oper_i__output_carry$58 + wire width 1 input 117 \oper_i__output_carry$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 95 \oper_i__input_cr$59 + wire width 1 input 118 \oper_i__input_cr$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 96 \oper_i__output_cr$60 + wire width 1 input 119 \oper_i__output_cr$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 97 \oper_i__is_32bit$61 + wire width 1 input 120 \oper_i__is_32bit$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 98 \oper_i__is_signed$62 + wire width 1 input 121 \oper_i__is_signed$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 32 input 99 \oper_i__insn$63 + wire width 32 input 122 \oper_i__insn$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 input 100 \issue_i$64 + wire width 1 input 123 \issue_i$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 101 \busy_o$65 + wire width 1 output 124 \busy_o$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 4 input 102 \rdmaskn$66 + wire width 4 input 125 \rdmaskn$89 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -91932,303 +211425,343 @@ module \fus attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 7 input 103 \oper_i__insn_type$67 + wire width 7 input 126 \oper_i__insn_type$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 64 input 104 \oper_i__imm_data__imm$68 + wire width 64 input 127 \oper_i__imm_data__imm$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 105 \oper_i__imm_data__imm_ok$69 + wire width 1 input 128 \oper_i__imm_data__imm_ok$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 106 \oper_i__zero_a$70 + wire width 1 input 129 \oper_i__zero_a$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 107 \oper_i__is_32bit$71 + wire width 1 input 130 \oper_i__is_32bit$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 108 \oper_i__is_signed$72 + wire width 1 input 131 \oper_i__is_signed$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 4 input 109 \oper_i__data_len$73 + wire width 4 input 132 \oper_i__data_len$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 110 \oper_i__byte_reverse$74 + wire width 1 input 133 \oper_i__byte_reverse$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 111 \oper_i__sign_extend$75 + wire width 1 input 134 \oper_i__sign_extend$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 112 \oper_i__update + wire width 1 input 135 \oper_i__update attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 input 113 \issue_i$76 + wire width 1 input 136 \issue_i$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 114 \busy_o$77 + wire width 1 output 137 \busy_o$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 3 input 115 \rdmaskn$78 + wire width 3 input 138 \rdmaskn$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 116 \rd__rel + wire width 4 output 139 \rd__rel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 117 \rd__go + wire width 4 input 140 \rd__go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 118 \src1_i + wire width 64 input 141 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 119 \rd__rel$79 + wire width 6 output 142 \rd__rel$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 input 120 \rd__go$80 + wire width 6 input 143 \rd__go$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 121 \src1_i$81 + wire width 64 input 144 \src1_i$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 122 \rd__rel$82 + wire width 6 output 145 \rd__rel$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 input 123 \rd__go$83 + wire width 6 input 146 \rd__go$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 124 \src1_i$84 + wire width 64 input 147 \src1_i$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 125 \rd__rel$85 + wire width 3 output 148 \rd__rel$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 input 126 \rd__go$86 + wire width 3 input 149 \rd__go$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 127 \src1_i$87 + wire width 64 input 150 \src1_i$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 128 \rd__rel$88 + wire width 2 output 151 \rd__rel$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 129 \rd__go$89 + wire width 2 input 152 \rd__go$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 130 \src1_i$90 + wire width 64 input 153 \src1_i$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 131 \rd__rel$91 + wire width 4 output 154 \rd__rel$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 132 \rd__go$92 + wire width 4 input 155 \rd__go$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 input 156 \src1_i$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 output 157 \rd__rel$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 input 158 \rd__go$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 input 159 \src1_i$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 input 160 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 133 \src1_i$93 + wire width 64 input 161 \src2_i$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 134 \src2_i + wire width 64 input 162 \src2_i$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 135 \src2_i$94 + wire width 64 input 163 \src2_i$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 136 \src2_i$95 + wire width 64 input 164 \src2_i$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 137 \src2_i$96 + wire width 64 input 165 \src2_i$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 138 \src2_i$97 + wire width 64 input 166 \src2_i$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 139 \src2_i$98 + wire width 64 input 167 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 140 \src3_i + wire width 64 input 168 \src3_i$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 141 \src3_i$99 + wire width 1 input 169 \src3_i$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 1 input 142 \src3_i$100 + wire width 1 input 170 \src3_i$128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 2 input 143 \src4_i + wire width 2 input 171 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 2 input 144 \src4_i$101 + wire width 2 input 172 \src4_i$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 32 input 145 \src3_i$102 + wire width 32 input 173 \src3_i$130 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 input 146 \src4_i$103 + wire width 4 input 174 \src4_i$131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 147 \rd__rel$104 + wire width 4 output 175 \rd__rel$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 148 \rd__go$105 + wire width 4 input 176 \rd__go$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 input 149 \src3_i$106 + wire width 4 input 177 \src3_i$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 input 150 \src5_i + wire width 4 input 178 \src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 input 151 \src6_i + wire width 4 input 179 \src6_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 152 \src1_i$107 + wire width 64 input 180 \src1_i$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 153 \src3_i$108 + wire width 64 input 181 \src3_i$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 154 \src2_i$109 + wire width 64 input 182 \src2_i$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 155 \src4_i$110 + wire width 64 input 183 \src4_i$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 156 \src4_i$111 + wire width 64 input 184 \src4_i$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 157 \src5_i$112 + wire width 64 input 185 \src5_i$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 158 \src6_i$113 + wire width 64 input 186 \src6_i$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 159 \o_ok + wire width 1 output 187 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 160 \wr__rel + wire width 5 output 188 \wr__rel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 input 161 \wr__go + wire width 5 input 189 \wr__go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 162 \o_ok$114 + wire width 1 output 190 \o_ok$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 163 \wr__rel$115 + wire width 3 output 191 \wr__rel$143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 164 \wr__go$116 + wire width 3 input 192 \wr__go$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 165 \o_ok$117 + wire width 1 output 193 \o_ok$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 166 \wr__rel$118 + wire width 5 output 194 \wr__rel$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 input 167 \wr__go$119 + wire width 5 input 195 \wr__go$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 168 \o_ok$120 + wire width 1 output 196 \o_ok$148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 169 \wr__rel$121 + wire width 5 output 197 \wr__rel$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 170 \wr__go$122 + wire width 5 input 198 \wr__go$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 171 \o_ok$123 + wire width 1 output 199 \o_ok$151 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 172 \wr__rel$124 + wire width 3 output 200 \wr__rel$152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 173 \wr__go$125 + wire width 3 input 201 \wr__go$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 202 \o_ok$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 output 203 \wr__rel$155 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 174 \wr__rel$126 + wire width 3 input 204 \wr__go$156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 input 175 \wr__go$127 + wire width 2 output 205 \wr__rel$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 2 input 206 \wr__go$158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 207 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 208 \o$159 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 209 \o$160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 210 \o$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 211 \o$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 176 \o + wire width 64 output 212 \o$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 177 \o$128 + wire width 64 output 213 \o$164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 178 \o$129 + wire width 64 output 214 \ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 179 \o$130 + wire width 1 output 215 \full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 180 \o$131 + wire width 32 output 216 \full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 181 \o$132 + wire width 1 output 217 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 182 \ea + wire width 1 output 218 \cr_a_ok$165 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 183 \full_cr_ok + wire width 1 output 219 \cr_a_ok$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 32 output 184 \full_cr + wire width 1 output 220 \cr_a_ok$167 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 185 \cr_a_ok + wire width 1 output 221 \cr_a_ok$168 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 186 \cr_a_ok$133 + wire width 4 output 222 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 187 \cr_a_ok$134 + wire width 4 output 223 \cr_a$169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 188 \cr_a_ok$135 + wire width 4 output 224 \cr_a$170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 output 189 \cr_a + wire width 4 output 225 \cr_a$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 output 190 \cr_a$136 + wire width 4 output 226 \cr_a$172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 output 191 \cr_a$137 + wire width 1 output 227 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 output 192 \cr_a$138 + wire width 1 output 228 \xer_ca_ok$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 193 \xer_ca_ok + wire width 1 output 229 \xer_ca_ok$174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 194 \xer_ca_ok$139 + wire width 1 output 230 \xer_ca_ok$175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 195 \xer_ca_ok$140 + wire width 2 output 231 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 output 196 \xer_ca + wire width 2 output 232 \xer_ca$176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 output 197 \xer_ca$141 + wire width 2 output 233 \xer_ca$177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 output 198 \xer_ca$142 + wire width 2 output 234 \xer_ca$178 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 199 \xer_ov_ok + wire width 1 output 235 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 output 200 \xer_ov + wire width 1 output 236 \xer_ov_ok$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 201 \xer_so_ok + wire width 2 output 237 \xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 202 \xer_so + wire width 2 output 238 \xer_ov$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 203 \spr1_ok + wire width 1 output 239 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 240 \xer_so_ok$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 241 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 242 \xer_so$182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 243 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 204 \wr__rel$143 + wire width 3 output 244 \wr__rel$183 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 205 \wr__go$144 + wire width 3 input 245 \wr__go$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 206 \spr1_ok$145 + wire width 1 output 246 \spr1_ok$185 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 207 \spr1 + wire width 64 output 247 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 208 \spr1$146 + wire width 64 output 248 \spr1$186 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 209 \spr2_ok + wire width 1 output 249 \spr2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 210 \spr2_ok$147 + wire width 1 output 250 \spr2_ok$187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 211 \spr2 + wire width 64 output 251 \spr2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 212 \spr2$148 + wire width 64 output 252 \spr2$188 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 213 \nia_ok + wire width 1 output 253 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 214 \nia_ok$149 + wire width 1 output 254 \nia_ok$189 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 215 \nia + wire width 64 output 255 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 216 \nia$150 + wire width 64 output 256 \nia$190 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 217 \msr_ok + wire width 1 output 257 \msr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 218 \msr + wire width 64 output 258 \msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 219 \go_die_i + wire width 1 input 259 \go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 220 \shadown_i + wire width 1 input 260 \shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 221 \dest1_o + wire width 64 output 261 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 222 \go_die_i$151 + wire width 1 input 262 \go_die_i$191 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 223 \shadown_i$152 + wire width 1 input 263 \shadown_i$192 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 224 \dest1_o$153 + wire width 64 output 264 \dest1_o$193 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 225 \go_die_i$154 + wire width 1 input 265 \go_die_i$194 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 226 \shadown_i$155 + wire width 1 input 266 \shadown_i$195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 227 \dest1_o$156 + wire width 64 output 267 \dest1_o$196 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 228 \go_die_i$157 + wire width 1 input 268 \go_die_i$197 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 229 \shadown_i$158 + wire width 1 input 269 \shadown_i$198 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 230 \dest1_o$159 + wire width 64 output 270 \dest1_o$199 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 231 \go_die_i$160 + wire width 1 input 271 \go_die_i$200 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 232 \shadown_i$161 + wire width 1 input 272 \shadown_i$201 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 233 \dest1_o$162 + wire width 64 output 273 \dest1_o$202 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 234 \go_die_i$163 + wire width 1 input 274 \go_die_i$203 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 235 \shadown_i$164 + wire width 1 input 275 \shadown_i$204 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 236 \dest1_o$165 + wire width 64 output 276 \dest1_o$205 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 237 \go_die_i$166 + wire width 1 input 277 \go_die_i$206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" + wire width 1 input 278 \shadown_i$207 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 64 output 279 \dest1_o$208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 1 input 280 \go_die_i$209 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112" - wire width 1 output 238 \load_mem_o + wire width 1 output 281 \load_mem_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" - wire width 1 output 239 \stwd_mem_o + wire width 1 output 282 \stwd_mem_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 240 \shadown_i$167 + wire width 1 input 283 \shadown_i$210 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 output 241 \ldst_port0_is_ld_i + wire width 1 output 284 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 output 242 \ldst_port0_is_st_i + wire width 1 output 285 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 output 243 \ldst_port0_data_len + wire width 4 output 286 \ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 96 output 244 \ldst_port0_addr_i + wire width 96 output 287 \ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 245 \ldst_port0_addr_i_ok + wire width 1 output 288 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 input 246 \ldst_port0_addr_exc_o + wire width 1 input 289 \ldst_port0_addr_exc_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 input 247 \ldst_port0_addr_ok_o + wire width 1 input 290 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 input 248 \ldst_port0_ld_data_o + wire width 64 input 291 \ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 input 249 \ldst_port0_ld_data_o_ok + wire width 1 input 292 \ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 250 \ldst_port0_st_data_i + wire width 64 output 293 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 251 \ldst_port0_st_data_i_ok + wire width 1 output 294 \ldst_port0_st_data_i_ok cell \alu0 \alu0 connect \rst \rst connect \clk \clk @@ -92263,7 +211796,7 @@ module \fus connect \rd__go \rd__go connect \src1_i \src1_i connect \src2_i \src2_i - connect \src3_i \src3_i$100 + connect \src3_i \src3_i$127 connect \src4_i \src4_i connect \o_ok \o_ok connect \wr__rel \wr__rel @@ -92292,25 +211825,25 @@ module \fus connect \issue_i \issue_i$4 connect \busy_o \busy_o$5 connect \rdmaskn \rdmaskn$6 - connect \rd__rel \rd__rel$79 - connect \rd__go \rd__go$80 - connect \src1_i \src1_i$81 - connect \src2_i \src2_i$94 - connect \src3_i \src3_i$102 - connect \src4_i \src4_i$103 + connect \rd__rel \rd__rel$102 + connect \rd__go \rd__go$103 + connect \src1_i \src1_i$104 + connect \src2_i \src2_i$120 + connect \src3_i \src3_i$130 + connect \src4_i \src4_i$131 connect \src5_i \src5_i connect \src6_i \src6_i - connect \o_ok \o_ok$114 - connect \wr__rel \wr__rel$115 - connect \wr__go \wr__go$116 - connect \o \o$128 + connect \o_ok \o_ok$142 + connect \wr__rel \wr__rel$143 + connect \wr__go \wr__go$144 + connect \o \o$159 connect \full_cr_ok \full_cr_ok connect \full_cr \full_cr - connect \cr_a_ok \cr_a_ok$133 - connect \cr_a \cr_a$136 - connect \go_die_i \go_die_i$151 - connect \shadown_i \shadown_i$152 - connect \dest1_o \dest1_o$153 + connect \cr_a_ok \cr_a_ok$165 + connect \cr_a \cr_a$169 + connect \go_die_i \go_die_i$191 + connect \shadown_i \shadown_i$192 + connect \dest1_o \dest1_o$193 end cell \branch0 \branch0 connect \rst \rst @@ -92325,23 +211858,23 @@ module \fus connect \issue_i \issue_i$14 connect \busy_o \busy_o$15 connect \rdmaskn \rdmaskn$16 - connect \rd__rel \rd__rel$104 - connect \rd__go \rd__go$105 - connect \src3_i \src3_i$106 - connect \src1_i \src1_i$107 - connect \src2_i \src2_i$109 - connect \src4_i \src4_i$111 + connect \rd__rel \rd__rel$132 + connect \rd__go \rd__go$133 + connect \src3_i \src3_i$134 + connect \src1_i \src1_i$135 + connect \src2_i \src2_i$137 + connect \src4_i \src4_i$139 connect \spr1_ok \spr1_ok - connect \wr__rel \wr__rel$143 - connect \wr__go \wr__go$144 + connect \wr__rel \wr__rel$183 + connect \wr__go \wr__go$184 connect \spr1 \spr1 connect \spr2_ok \spr2_ok connect \spr2 \spr2 connect \nia_ok \nia_ok connect \nia \nia - connect \go_die_i \go_die_i$154 - connect \shadown_i \shadown_i$155 - connect \dest1_o \dest1_o$156 + connect \go_die_i \go_die_i$194 + connect \shadown_i \shadown_i$195 + connect \dest1_o \dest1_o$196 end cell \trap0 \trap0 connect \rst \rst @@ -92355,31 +211888,31 @@ module \fus connect \issue_i \issue_i$21 connect \busy_o \busy_o$22 connect \rdmaskn \rdmaskn$23 - connect \rd__rel \rd__rel$82 - connect \rd__go \rd__go$83 - connect \src1_i \src1_i$84 - connect \src2_i \src2_i$95 - connect \src3_i \src3_i$108 - connect \src4_i \src4_i$110 - connect \src5_i \src5_i$112 - connect \src6_i \src6_i$113 - connect \o_ok \o_ok$117 - connect \wr__rel \wr__rel$118 - connect \wr__go \wr__go$119 - connect \o \o$129 - connect \spr1_ok \spr1_ok$145 - connect \spr1 \spr1$146 - connect \spr2_ok \spr2_ok$147 - connect \spr2 \spr2$148 - connect \nia_ok \nia_ok$149 - connect \nia \nia$150 + connect \rd__rel \rd__rel$105 + connect \rd__go \rd__go$106 + connect \src1_i \src1_i$107 + connect \src2_i \src2_i$121 + connect \src3_i \src3_i$136 + connect \src4_i \src4_i$138 + connect \src5_i \src5_i$140 + connect \src6_i \src6_i$141 + connect \o_ok \o_ok$145 + connect \wr__rel \wr__rel$146 + connect \wr__go \wr__go$147 + connect \o \o$160 + connect \spr1_ok \spr1_ok$185 + connect \spr1 \spr1$186 + connect \spr2_ok \spr2_ok$187 + connect \spr2 \spr2$188 + connect \nia_ok \nia_ok$189 + connect \nia \nia$190 connect \msr_ok \msr_ok connect \msr \msr - connect \go_die_i \go_die_i$157 - connect \shadown_i \shadown_i$158 - connect \dest1_o \dest1_o$159 + connect \go_die_i \go_die_i$197 + connect \shadown_i \shadown_i$198 + connect \dest1_o \dest1_o$199 end - cell \logical0 \logical0 + cell \div0 \div0 connect \rst \rst connect \clk \clk connect \oper_i__insn_type \oper_i__insn_type$24 @@ -92405,62 +211938,109 @@ module \fus connect \issue_i \issue_i$44 connect \busy_o \busy_o$45 connect \rdmaskn \rdmaskn$46 - connect \rd__rel \rd__rel$85 - connect \rd__go \rd__go$86 - connect \src1_i \src1_i$87 - connect \src2_i \src2_i$96 - connect \o_ok \o_ok$120 - connect \wr__rel \wr__rel$121 - connect \wr__go \wr__go$122 - connect \o \o$130 - connect \cr_a_ok \cr_a_ok$134 - connect \cr_a \cr_a$137 - connect \xer_ca_ok \xer_ca_ok$139 - connect \xer_ca \xer_ca$141 - connect \go_die_i \go_die_i$160 - connect \shadown_i \shadown_i$161 - connect \dest1_o \dest1_o$162 + connect \rd__rel \rd__rel$108 + connect \rd__go \rd__go$109 + connect \src1_i \src1_i$110 + connect \src2_i \src2_i$122 + connect \src3_i \src3_i$128 + connect \o_ok \o_ok$148 + connect \wr__rel \wr__rel$149 + connect \wr__go \wr__go$150 + connect \o \o$161 + connect \cr_a_ok \cr_a_ok$166 + connect \cr_a \cr_a$170 + connect \xer_ca_ok \xer_ca_ok$173 + connect \xer_ca \xer_ca$176 + connect \xer_ov_ok \xer_ov_ok$179 + connect \xer_ov \xer_ov$180 + connect \xer_so_ok \xer_so_ok$181 + connect \xer_so \xer_so$182 + connect \go_die_i \go_die_i$200 + connect \shadown_i \shadown_i$201 + connect \dest1_o \dest1_o$202 end - cell \shiftrot0 \shiftrot0 + cell \logical0 \logical0 connect \rst \rst connect \clk \clk connect \oper_i__insn_type \oper_i__insn_type$47 connect \oper_i__fn_unit \oper_i__fn_unit$48 connect \oper_i__imm_data__imm \oper_i__imm_data__imm$49 connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$50 - connect \oper_i__rc__rc \oper_i__rc__rc$51 - connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$52 - connect \oper_i__oe__oe \oper_i__oe__oe$53 - connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$54 - connect \oper_i__write_cr__data \oper_i__write_cr__data$55 - connect \oper_i__write_cr__ok \oper_i__write_cr__ok$56 - connect \oper_i__input_carry \oper_i__input_carry$57 - connect \oper_i__output_carry \oper_i__output_carry$58 - connect \oper_i__input_cr \oper_i__input_cr$59 - connect \oper_i__output_cr \oper_i__output_cr$60 - connect \oper_i__is_32bit \oper_i__is_32bit$61 - connect \oper_i__is_signed \oper_i__is_signed$62 - connect \oper_i__insn \oper_i__insn$63 - connect \issue_i \issue_i$64 - connect \busy_o \busy_o$65 - connect \rdmaskn \rdmaskn$66 - connect \rd__rel \rd__rel$88 - connect \rd__go \rd__go$89 - connect \src1_i \src1_i$90 - connect \src2_i \src2_i$97 + connect \oper_i__lk \oper_i__lk$51 + connect \oper_i__rc__rc \oper_i__rc__rc$52 + connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$53 + connect \oper_i__oe__oe \oper_i__oe__oe$54 + connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$55 + connect \oper_i__invert_a \oper_i__invert_a$56 + connect \oper_i__zero_a \oper_i__zero_a$57 + connect \oper_i__input_carry \oper_i__input_carry$58 + connect \oper_i__invert_out \oper_i__invert_out$59 + connect \oper_i__write_cr__data \oper_i__write_cr__data$60 + connect \oper_i__write_cr__ok \oper_i__write_cr__ok$61 + connect \oper_i__output_carry \oper_i__output_carry$62 + connect \oper_i__is_32bit \oper_i__is_32bit$63 + connect \oper_i__is_signed \oper_i__is_signed$64 + connect \oper_i__data_len \oper_i__data_len$65 + connect \oper_i__insn \oper_i__insn$66 + connect \issue_i \issue_i$67 + connect \busy_o \busy_o$68 + connect \rdmaskn \rdmaskn$69 + connect \rd__rel \rd__rel$111 + connect \rd__go \rd__go$112 + connect \src1_i \src1_i$113 + connect \src2_i \src2_i$123 + connect \o_ok \o_ok$151 + connect \wr__rel \wr__rel$152 + connect \wr__go \wr__go$153 + connect \o \o$162 + connect \cr_a_ok \cr_a_ok$167 + connect \cr_a \cr_a$171 + connect \xer_ca_ok \xer_ca_ok$174 + connect \xer_ca \xer_ca$177 + connect \go_die_i \go_die_i$203 + connect \shadown_i \shadown_i$204 + connect \dest1_o \dest1_o$205 + end + cell \shiftrot0 \shiftrot0 + connect \rst \rst + connect \clk \clk + connect \oper_i__insn_type \oper_i__insn_type$70 + connect \oper_i__fn_unit \oper_i__fn_unit$71 + connect \oper_i__imm_data__imm \oper_i__imm_data__imm$72 + connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$73 + connect \oper_i__rc__rc \oper_i__rc__rc$74 + connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$75 + connect \oper_i__oe__oe \oper_i__oe__oe$76 + connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$77 + connect \oper_i__write_cr__data \oper_i__write_cr__data$78 + connect \oper_i__write_cr__ok \oper_i__write_cr__ok$79 + connect \oper_i__input_carry \oper_i__input_carry$80 + connect \oper_i__output_carry \oper_i__output_carry$81 + connect \oper_i__input_cr \oper_i__input_cr$82 + connect \oper_i__output_cr \oper_i__output_cr$83 + connect \oper_i__is_32bit \oper_i__is_32bit$84 + connect \oper_i__is_signed \oper_i__is_signed$85 + connect \oper_i__insn \oper_i__insn$86 + connect \issue_i \issue_i$87 + connect \busy_o \busy_o$88 + connect \rdmaskn \rdmaskn$89 + connect \rd__rel \rd__rel$114 + connect \rd__go \rd__go$115 + connect \src1_i \src1_i$116 + connect \src2_i \src2_i$124 connect \src3_i \src3_i - connect \src4_i \src4_i$101 - connect \o_ok \o_ok$123 - connect \wr__rel \wr__rel$124 - connect \wr__go \wr__go$125 - connect \o \o$131 - connect \cr_a_ok \cr_a_ok$135 - connect \cr_a \cr_a$138 - connect \xer_ca_ok \xer_ca_ok$140 - connect \xer_ca \xer_ca$142 - connect \go_die_i \go_die_i$163 - connect \shadown_i \shadown_i$164 - connect \dest1_o \dest1_o$165 + connect \src4_i \src4_i$129 + connect \o_ok \o_ok$154 + connect \wr__rel \wr__rel$155 + connect \wr__go \wr__go$156 + connect \o \o$163 + connect \cr_a_ok \cr_a_ok$168 + connect \cr_a \cr_a$172 + connect \xer_ca_ok \xer_ca_ok$175 + connect \xer_ca \xer_ca$178 + connect \go_die_i \go_die_i$206 + connect \shadown_i \shadown_i$207 + connect \dest1_o \dest1_o$208 end cell \ldst0 \ldst0 connect \ad__go \ad__go @@ -92469,32 +212049,32 @@ module \fus connect \st__rel \st__rel connect \rst \rst connect \clk \clk - connect \oper_i__insn_type \oper_i__insn_type$67 - connect \oper_i__imm_data__imm \oper_i__imm_data__imm$68 - connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$69 - connect \oper_i__zero_a \oper_i__zero_a$70 - connect \oper_i__is_32bit \oper_i__is_32bit$71 - connect \oper_i__is_signed \oper_i__is_signed$72 - connect \oper_i__data_len \oper_i__data_len$73 - connect \oper_i__byte_reverse \oper_i__byte_reverse$74 - connect \oper_i__sign_extend \oper_i__sign_extend$75 + connect \oper_i__insn_type \oper_i__insn_type$90 + connect \oper_i__imm_data__imm \oper_i__imm_data__imm$91 + connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$92 + connect \oper_i__zero_a \oper_i__zero_a$93 + connect \oper_i__is_32bit \oper_i__is_32bit$94 + connect \oper_i__is_signed \oper_i__is_signed$95 + connect \oper_i__data_len \oper_i__data_len$96 + connect \oper_i__byte_reverse \oper_i__byte_reverse$97 + connect \oper_i__sign_extend \oper_i__sign_extend$98 connect \oper_i__update \oper_i__update - connect \issue_i \issue_i$76 - connect \busy_o \busy_o$77 - connect \rdmaskn \rdmaskn$78 - connect \rd__rel \rd__rel$91 - connect \rd__go \rd__go$92 - connect \src1_i \src1_i$93 - connect \src2_i \src2_i$98 - connect \src3_i \src3_i$99 - connect \wr__rel \wr__rel$126 - connect \wr__go \wr__go$127 - connect \o \o$132 + connect \issue_i \issue_i$99 + connect \busy_o \busy_o$100 + connect \rdmaskn \rdmaskn$101 + connect \rd__rel \rd__rel$117 + connect \rd__go \rd__go$118 + connect \src1_i \src1_i$119 + connect \src2_i \src2_i$125 + connect \src3_i \src3_i$126 + connect \wr__rel \wr__rel$157 + connect \wr__go \wr__go$158 + connect \o \o$164 connect \ea \ea - connect \go_die_i \go_die_i$166 + connect \go_die_i \go_die_i$209 connect \load_mem_o \load_mem_o connect \stwd_mem_o \stwd_mem_o - connect \shadown_i \shadown_i$167 + connect \shadown_i \shadown_i$210 connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i connect \ldst_port0_is_st_i \ldst_port0_is_st_i connect \ldst_port0_data_len \ldst_port0_data_len @@ -94588,7 +214168,7 @@ module \idx_l end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l" -module \reset_l$82 +module \reset_l$327 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -94735,7 +214315,7 @@ module \pick end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.l0" -module \l0$81 +module \l0$326 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -94811,7 +214391,7 @@ module \l0$81 wire width 1 \reset_l_r_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \reset_l_q_reset - cell \reset_l$82 \reset_l + cell \reset_l$327 \reset_l connect \rst \rst connect \clk \clk connect \s_reset \reset_l_s_reset @@ -96132,7 +215712,7 @@ module \l0 connect \m_valid_i \m_valid_i connect \x_valid_i \x_valid_i end - cell \l0$81 \l0 + cell \l0$326 \l0 connect \rst \rst connect \clk \clk connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i @@ -109657,7 +229237,7 @@ module \int end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0" -module \reg_0$83 +module \reg_0$328 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -110143,7 +229723,7 @@ module \reg_0$83 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1" -module \reg_1$84 +module \reg_1$329 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -110629,7 +230209,7 @@ module \reg_1$84 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2" -module \reg_2$85 +module \reg_2$330 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -111115,7 +230695,7 @@ module \reg_2$85 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3" -module \reg_3$86 +module \reg_3$331 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -111601,7 +231181,7 @@ module \reg_3$86 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4" -module \reg_4$87 +module \reg_4$332 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -112087,7 +231667,7 @@ module \reg_4$87 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5" -module \reg_5$88 +module \reg_5$333 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -112573,7 +232153,7 @@ module \reg_5$88 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6" -module \reg_6$89 +module \reg_6$334 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -113059,7 +232639,7 @@ module \reg_6$89 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7" -module \reg_7$90 +module \reg_7$335 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -113602,7 +233182,7 @@ module \cr wire width 4 \reg_0_w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_0_w0__wen - cell \reg_0$83 \reg_0 + cell \reg_0$328 \reg_0 connect \rst \rst connect \clk \clk connect \src10__ren \reg_0_src10__ren @@ -113648,7 +233228,7 @@ module \cr wire width 4 \reg_1_w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_1_w1__wen - cell \reg_1$84 \reg_1 + cell \reg_1$329 \reg_1 connect \rst \rst connect \clk \clk connect \src11__ren \reg_1_src11__ren @@ -113694,7 +233274,7 @@ module \cr wire width 4 \reg_2_w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_2_w2__wen - cell \reg_2$85 \reg_2 + cell \reg_2$330 \reg_2 connect \rst \rst connect \clk \clk connect \src12__ren \reg_2_src12__ren @@ -113740,7 +233320,7 @@ module \cr wire width 4 \reg_3_w3__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_3_w3__wen - cell \reg_3$86 \reg_3 + cell \reg_3$331 \reg_3 connect \rst \rst connect \clk \clk connect \src13__ren \reg_3_src13__ren @@ -113786,7 +233366,7 @@ module \cr wire width 4 \reg_4_w4__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_4_w4__wen - cell \reg_4$87 \reg_4 + cell \reg_4$332 \reg_4 connect \rst \rst connect \clk \clk connect \src14__ren \reg_4_src14__ren @@ -113832,7 +233412,7 @@ module \cr wire width 4 \reg_5_w5__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_5_w5__wen - cell \reg_5$88 \reg_5 + cell \reg_5$333 \reg_5 connect \rst \rst connect \clk \clk connect \src15__ren \reg_5_src15__ren @@ -113878,7 +233458,7 @@ module \cr wire width 4 \reg_6_w6__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_6_w6__wen - cell \reg_6$89 \reg_6 + cell \reg_6$334 \reg_6 connect \rst \rst connect \clk \clk connect \src16__ren \reg_6_src16__ren @@ -113924,7 +233504,7 @@ module \cr wire width 4 \reg_7_w7__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_7_w7__wen - cell \reg_7$90 \reg_7 + cell \reg_7$335 \reg_7 connect \rst \rst connect \clk \clk connect \src17__ren \reg_7_src17__ren @@ -114420,7 +234000,7 @@ module \cr end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0" -module \reg_0$91 +module \reg_0$336 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -114964,7 +234544,7 @@ module \reg_0$91 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1" -module \reg_1$92 +module \reg_1$337 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -115508,7 +235088,7 @@ module \reg_1$92 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2" -module \reg_2$93 +module \reg_2$338 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -116109,7 +235689,7 @@ module \xer wire width 2 \reg_0_w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_0_w0__wen - cell \reg_0$91 \reg_0 + cell \reg_0$336 \reg_0 connect \rst \rst connect \clk \clk connect \src10__ren \reg_0_src10__ren @@ -116161,7 +235741,7 @@ module \xer wire width 2 \reg_1_w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_1_w1__wen - cell \reg_1$92 \reg_1 + cell \reg_1$337 \reg_1 connect \rst \rst connect \clk \clk connect \src11__ren \reg_1_src11__ren @@ -116213,7 +235793,7 @@ module \xer wire width 2 \reg_2_w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_2_w2__wen - cell \reg_2$93 \reg_2 + cell \reg_2$338 \reg_2 connect \rst \rst connect \clk \clk connect \src12__ren \reg_2_src12__ren @@ -116458,7 +236038,7 @@ module \xer end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_0" -module \reg_0$94 +module \reg_0$339 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -117192,7 +236772,7 @@ module \reg_0$94 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_1" -module \reg_1$95 +module \reg_1$340 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -117926,7 +237506,7 @@ module \reg_1$95 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_2" -module \reg_2$96 +module \reg_2$341 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -118660,7 +238240,7 @@ module \reg_2$96 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_3" -module \reg_3$97 +module \reg_3$342 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -119394,7 +238974,7 @@ module \reg_3$97 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_4" -module \reg_4$98 +module \reg_4$343 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -120128,7 +239708,7 @@ module \reg_4$98 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_5" -module \reg_5$99 +module \reg_5$344 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -120862,7 +240442,7 @@ module \reg_5$99 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_6" -module \reg_6$100 +module \reg_6$345 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -121596,7 +241176,7 @@ module \reg_6$100 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_7" -module \reg_7$101 +module \reg_7$346 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -122415,7 +241995,7 @@ module \fast wire width 1 \reg_0_d_wr10__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_0_d_wr10__data_i - cell \reg_0$94 \reg_0 + cell \reg_0$339 \reg_0 connect \rst \rst connect \clk \clk connect \src10__ren \reg_0_src10__ren @@ -122479,7 +242059,7 @@ module \fast wire width 1 \reg_1_d_wr11__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_1_d_wr11__data_i - cell \reg_1$95 \reg_1 + cell \reg_1$340 \reg_1 connect \rst \rst connect \clk \clk connect \src11__ren \reg_1_src11__ren @@ -122543,7 +242123,7 @@ module \fast wire width 1 \reg_2_d_wr12__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_2_d_wr12__data_i - cell \reg_2$96 \reg_2 + cell \reg_2$341 \reg_2 connect \rst \rst connect \clk \clk connect \src12__ren \reg_2_src12__ren @@ -122607,7 +242187,7 @@ module \fast wire width 1 \reg_3_d_wr13__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_3_d_wr13__data_i - cell \reg_3$97 \reg_3 + cell \reg_3$342 \reg_3 connect \rst \rst connect \clk \clk connect \src13__ren \reg_3_src13__ren @@ -122671,7 +242251,7 @@ module \fast wire width 1 \reg_4_d_wr14__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_4_d_wr14__data_i - cell \reg_4$98 \reg_4 + cell \reg_4$343 \reg_4 connect \rst \rst connect \clk \clk connect \src14__ren \reg_4_src14__ren @@ -122735,7 +242315,7 @@ module \fast wire width 1 \reg_5_d_wr15__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_5_d_wr15__data_i - cell \reg_5$99 \reg_5 + cell \reg_5$344 \reg_5 connect \rst \rst connect \clk \clk connect \src15__ren \reg_5_src15__ren @@ -122799,7 +242379,7 @@ module \fast wire width 1 \reg_6_d_wr16__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_6_d_wr16__data_i - cell \reg_6$100 \reg_6 + cell \reg_6$345 \reg_6 connect \rst \rst connect \clk \clk connect \src16__ren \reg_6_src16__ren @@ -122863,7 +242443,7 @@ module \fast wire width 1 \reg_7_d_wr17__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_7_d_wr17__data_i - cell \reg_7$101 \reg_7 + cell \reg_7$346 \reg_7 connect \rst \rst connect \clk \clk connect \src17__ren \reg_7_src17__ren @@ -124973,23 +244553,23 @@ module \rdpick_INT_ra attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 6 input 1 \i + wire width 7 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 6 output 2 \o + wire width 7 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 6 \ni + wire width 7 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 6 $1 + wire width 7 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \i connect \Y $1 end process $group_0 - assign \ni 6'000000 + assign \ni 7'0000000 assign \ni $1 sync init end @@ -125135,24 +244715,51 @@ module \rdpick_INT_ra assign \t5 $19 sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end process $group_7 - assign \o 6'000000 - assign \o { \t5 \t4 \t3 \t2 \t1 \t0 } + assign \t6 1'0 + assign \t6 $23 + sync init + end + process $group_8 + assign \o 7'0000000 + assign \o { \t6 \t5 \t4 \t3 \t2 \t1 \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $23 + wire width 1 $27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $24 + cell $reduce_bool $28 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A \o - connect \Y $23 + connect \Y $27 end - process $group_8 + process $group_9 assign \en_o 1'0 - assign \en_o $23 + assign \en_o $27 sync init end end @@ -125162,23 +244769,23 @@ module \rdpick_INT_rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 6 input 1 \i + wire width 7 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 6 output 2 \o + wire width 7 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 6 \ni + wire width 7 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 6 $1 + wire width 7 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \i connect \Y $1 end process $group_0 - assign \ni 6'000000 + assign \ni 7'0000000 assign \ni $1 sync init end @@ -125324,24 +244931,51 @@ module \rdpick_INT_rb assign \t5 $19 sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end process $group_7 - assign \o 6'000000 - assign \o { \t5 \t4 \t3 \t2 \t1 \t0 } + assign \t6 1'0 + assign \t6 $23 + sync init + end + process $group_8 + assign \o 7'0000000 + assign \o { \t6 \t5 \t4 \t3 \t2 \t1 \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $23 + wire width 1 $27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $24 + cell $reduce_bool $28 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A \o - connect \Y $23 + connect \Y $27 end - process $group_8 + process $group_9 assign \en_o 1'0 - assign \en_o $23 + assign \en_o $27 sync init end end @@ -125427,60 +245061,87 @@ module \rdpick_INT_rc end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_so" -module \rdpick_XER_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 0 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 1 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $1 - end - process $group_0 - assign \ni 1'0 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i - sync init - end - process $group_2 - assign \o 1'0 - assign \o { \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 - end - process $group_3 - assign \en_o 1'0 - assign \en_o $3 - sync init - end -end -attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_so" +module \rdpick_XER_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 0 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 2 input 1 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 2 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 2 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 2'00 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + process $group_3 + assign \o 2'00 + assign \o { \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $7 + end + process $group_4 + assign \en_o 1'0 + assign \en_o $7 + sync init + end +end +attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ca" module \rdpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" @@ -126107,23 +245768,23 @@ module \wrpick_INT_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 6 input 1 \i + wire width 7 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 6 output 2 \o + wire width 7 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 6 \ni + wire width 7 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 6 $1 + wire width 7 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \i connect \Y $1 end process $group_0 - assign \ni 6'000000 + assign \ni 7'0000000 assign \ni $1 sync init end @@ -126269,24 +245930,51 @@ module \wrpick_INT_o assign \t5 $19 sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end process $group_7 - assign \o 6'000000 - assign \o { \t5 \t4 \t3 \t2 \t1 \t0 } + assign \t6 1'0 + assign \t6 $23 + sync init + end + process $group_8 + assign \o 7'0000000 + assign \o { \t6 \t5 \t4 \t3 \t2 \t1 \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $23 + wire width 1 $27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $24 + cell $reduce_bool $28 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A \o - connect \Y $23 + connect \Y $27 end - process $group_8 + process $group_9 assign \en_o 1'0 - assign \en_o $23 + assign \en_o $27 sync init end end @@ -126401,6 +246089,168 @@ end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_cr_a" module \wrpick_CR_cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 0 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 5 input 1 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 5 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 5 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 5 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 5'00000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end + process $group_4 + assign \t3 1'0 + assign \t3 $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] } + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $16 + connect \Y $15 + end + process $group_5 + assign \t4 1'0 + assign \t4 $15 + sync init + end + process $group_6 + assign \o 5'00000 + assign \o { \t4 \t3 \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $19 + end + process $group_7 + assign \en_o 1'0 + assign \en_o $19 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ca" +module \wrpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" @@ -126534,28 +246384,28 @@ module \wrpick_CR_cr_a end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ca" -module \wrpick_XER_xer_ca +attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ov" +module \wrpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 3 input 1 \i + wire width 2 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 3 output 2 \o + wire width 2 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 3 \ni + wire width 2 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 3 $1 + wire width 2 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \i connect \Y $1 end process $group_0 - assign \ni 3'000 + assign \ni 2'00 assign \ni $1 sync init end @@ -126593,77 +246443,50 @@ module \wrpick_XER_xer_ca assign \t1 $3 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - process $group_4 - assign \o 3'000 - assign \o { \t2 \t1 \t0 } + assign \o 2'00 + assign \o { \t1 \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $11 + wire width 1 $7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $12 + cell $reduce_bool $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $11 + connect \Y $7 end - process $group_5 + process $group_4 assign \en_o 1'0 - assign \en_o $11 + assign \en_o $7 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ov" -module \wrpick_XER_xer_ov +attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_so" +module \wrpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 1 \i + wire width 2 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 2 \o + wire width 2 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni + wire width 2 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 1 $1 + wire width 2 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \i connect \Y $1 end process $group_0 - assign \ni 1'0 + assign \ni 2'00 assign \ni $1 sync init end @@ -126671,81 +246494,54 @@ module \wrpick_XER_xer_ov wire width 1 \t0 process $group_1 assign \t0 1'0 - assign \t0 \i - sync init - end - process $group_2 - assign \o 1'0 - assign \o { \t0 } + assign \t0 \i [0] sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 - end - process $group_3 - assign \en_o 1'0 - assign \en_o $3 - sync init + connect \A { \i [0] \ni [1] } + connect \Y $4 end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_so" -module \wrpick_XER_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 0 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 1 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \i - connect \Y $1 - end - process $group_0 - assign \ni 1'0 - assign \ni $1 - sync init + connect \A $4 + connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i + process $group_2 + assign \t1 1'0 + assign \t1 $3 sync init end - process $group_2 - assign \o 1'0 - assign \o { \t0 } + process $group_3 + assign \o 2'00 + assign \o { \t1 \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $3 + wire width 1 $7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 + cell $reduce_bool $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $3 + connect \Y $7 end - process $group_3 + process $group_4 assign \en_o 1'0 - assign \en_o $3 + assign \en_o $7 sync init end end @@ -127242,92 +247038,199 @@ module \core attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33" - wire width 7 output 18 \insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 19 \imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 20 \imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 21 \oper_i__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" - wire width 1 output 22 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 23 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 24 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 25 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 26 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 27 \oper_i__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" - wire width 1 output 28 \invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63" - wire width 1 output 29 \zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 30 \oper_i__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64" - wire width 1 output 31 \invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 32 \cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 33 \cr_out_ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 2 output 34 \oper_i__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65" - wire width 2 output 35 \input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 36 \oper_i__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66" - wire width 1 output 37 \output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 38 \oper_i__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67" - wire width 1 output 39 \input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 40 \oper_i__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68" - wire width 1 output 41 \output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 42 \oper_i__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69" - wire width 1 output 43 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 44 \oper_i__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70" - wire width 1 output 45 \is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 4 output 46 \oper_i__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" - wire width 4 output 47 \data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71" - wire width 32 output 48 \insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 49 \oper_i__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73" - wire width 1 output 50 \byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 51 \oper_i__sign_extend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74" - wire width 1 output 52 \sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33" + wire width 7 output 18 \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 19 \imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 20 \imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 21 \oper_i__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" + wire width 1 output 22 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 23 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 24 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 25 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 26 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 27 \oper_i__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" + wire width 1 output 28 \invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63" + wire width 1 output 29 \zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 30 \oper_i__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64" + wire width 1 output 31 \invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 32 \cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 33 \cr_out_ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 2 output 34 \oper_i__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65" + wire width 2 output 35 \input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 36 \oper_i__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66" + wire width 1 output 37 \output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 38 \oper_i__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67" + wire width 1 output 39 \input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 40 \oper_i__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68" + wire width 1 output 41 \output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 42 \oper_i__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69" + wire width 1 output 43 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 44 \oper_i__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70" + wire width 1 output 45 \is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 4 output 46 \oper_i__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" + wire width 4 output 47 \data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71" + wire width 32 output 48 \insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 49 \oper_i__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73" + wire width 1 output 50 \byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 51 \oper_i__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74" + wire width 1 output 52 \sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" + wire width 1 output 53 \issue_i$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" + wire width 1 output 54 \busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 55 \reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 56 \reg2_ok + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 7 output 57 \oper_i__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 10 output 58 \oper_i__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 32 output 59 \oper_i__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 1 output 60 \oper_i__read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire width 1 output 61 \read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 1 output 62 \oper_i__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire width 1 output 63 \write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 53 \issue_i$1 + wire width 1 output 64 \issue_i$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 54 \busy_o + wire width 1 output 65 \busy_o$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 55 \reg1_ok + wire width 1 output 66 \cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 56 \reg2_ok + wire width 1 output 67 \cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 68 \cr_in2_ok$5 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -127400,8 +247303,8 @@ module \core attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 7 output 57 \oper_i__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 7 output 69 \oper_i__insn_type$6 attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -127413,28 +247316,22 @@ module \core attribute \enum_value_0010000000 "TRAP" attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 output 58 \oper_i__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 32 output 59 \oper_i__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 1 output 60 \oper_i__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 output 61 \read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 1 output 62 \oper_i__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire width 1 output 63 \write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 10 output 70 \oper_i__fn_unit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 1 output 71 \oper_i__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 1 output 72 \oper_i__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 32 output 73 \oper_i__insn$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 64 \issue_i$3 + wire width 1 output 74 \issue_i$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 65 \busy_o$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 66 \cr_in1_ok + wire width 1 output 75 \busy_o$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 67 \cr_in2_ok + wire width 1 output 76 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 68 \cr_in2_ok$5 + wire width 1 output 77 \fast2_ok attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -127507,8 +247404,8 @@ module \core attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 7 output 69 \oper_i__insn_type$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 7 output 78 \oper_i__insn_type$13 attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -127520,22 +247417,24 @@ module \core attribute \enum_value_0010000000 "TRAP" attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 output 70 \oper_i__fn_unit$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 output 71 \oper_i__lk$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 output 72 \oper_i__is_32bit$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 32 output 73 \oper_i__insn$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 10 output 79 \oper_i__fn_unit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 32 output 80 \oper_i__insn$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 1 output 81 \oper_i__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 4 output 82 \oper_i__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:76" + wire width 4 input 83 \traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 13 output 84 \oper_i__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:77" + wire width 13 output 85 \trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 74 \issue_i$11 + wire width 1 output 86 \issue_i$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 75 \busy_o$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 76 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 77 \fast2_ok + wire width 1 output 87 \busy_o$18 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -127608,8 +247507,8 @@ module \core attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 7 output 78 \oper_i__insn_type$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 88 \oper_i__insn_type$19 attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -127621,24 +247520,32 @@ module \core attribute \enum_value_0010000000 "TRAP" attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 output 79 \oper_i__fn_unit$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 32 output 80 \oper_i__insn$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 1 output 81 \oper_i__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 output 82 \oper_i__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:76" - wire width 4 input 83 \traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 13 output 84 \oper_i__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:77" - wire width 13 output 85 \trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 89 \oper_i__fn_unit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 90 \oper_i__lk$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 91 \oper_i__invert_a$22 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 92 \oper_i__input_carry$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 93 \oper_i__invert_out$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 94 \oper_i__output_carry$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 95 \oper_i__is_32bit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 96 \oper_i__is_signed$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 97 \oper_i__data_len$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 86 \issue_i$17 + wire width 1 output 98 \issue_i$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 87 \busy_o$18 + wire width 1 output 99 \busy_o$30 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -127712,7 +247619,7 @@ module \core attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 7 output 88 \oper_i__insn_type$19 + wire width 7 output 100 \oper_i__insn_type$31 attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -127725,31 +247632,31 @@ module \core attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 output 89 \oper_i__fn_unit$20 + wire width 10 output 101 \oper_i__fn_unit$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 90 \oper_i__lk$21 + wire width 1 output 102 \oper_i__lk$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 91 \oper_i__invert_a$22 + wire width 1 output 103 \oper_i__invert_a$34 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 2 output 92 \oper_i__input_carry$23 + wire width 2 output 104 \oper_i__input_carry$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 93 \oper_i__invert_out$24 + wire width 1 output 105 \oper_i__invert_out$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 94 \oper_i__output_carry$25 + wire width 1 output 106 \oper_i__output_carry$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 95 \oper_i__is_32bit$26 + wire width 1 output 107 \oper_i__is_32bit$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 96 \oper_i__is_signed$27 + wire width 1 output 108 \oper_i__is_signed$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 4 output 97 \oper_i__data_len$28 + wire width 4 output 109 \oper_i__data_len$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 98 \issue_i$29 + wire width 1 output 110 \issue_i$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 99 \busy_o$30 + wire width 1 output 111 \busy_o$42 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -127823,29 +247730,29 @@ module \core attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 7 output 100 \oper_i__insn_type$31 + wire width 7 output 112 \oper_i__insn_type$43 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 2 output 101 \oper_i__input_carry$32 + wire width 2 output 113 \oper_i__input_carry$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 102 \oper_i__output_carry$33 + wire width 1 output 114 \oper_i__output_carry$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 103 \oper_i__input_cr$34 + wire width 1 output 115 \oper_i__input_cr$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 104 \oper_i__output_cr$35 + wire width 1 output 116 \oper_i__output_cr$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 105 \oper_i__is_32bit$36 + wire width 1 output 117 \oper_i__is_32bit$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 106 \oper_i__is_signed$37 + wire width 1 output 118 \oper_i__is_signed$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 107 \issue_i$38 + wire width 1 output 119 \issue_i$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 108 \busy_o$39 + wire width 1 output 120 \busy_o$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 109 \reg3_ok + wire width 1 output 121 \reg3_ok attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -127919,161 +247826,175 @@ module \core attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 7 output 110 \oper_i__insn_type$40 + wire width 7 output 122 \oper_i__insn_type$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 111 \oper_i__zero_a + wire width 1 output 123 \oper_i__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 112 \oper_i__is_32bit$41 + wire width 1 output 124 \oper_i__is_32bit$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 113 \oper_i__is_signed$42 + wire width 1 output 125 \oper_i__is_signed$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 4 output 114 \oper_i__data_len$43 + wire width 4 output 126 \oper_i__data_len$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 115 \oper_i__byte_reverse$44 + wire width 1 output 127 \oper_i__byte_reverse$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 116 \oper_i__sign_extend$45 + wire width 1 output 128 \oper_i__sign_extend$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 117 \oper_i__update + wire width 1 output 129 \oper_i__update attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:75" - wire width 1 output 118 \update + wire width 1 output 130 \update attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 119 \issue_i$46 + wire width 1 output 131 \issue_i$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 120 \busy_o$47 + wire width 1 output 132 \busy_o$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 121 \reg1 + wire width 5 output 133 \reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 122 \rd__rel + wire width 4 output 134 \rd__rel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 123 \rd__go + wire width 4 output 135 \rd__go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 124 \src1_i + wire width 64 output 136 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 125 \rd__rel$48 + wire width 6 output 137 \rd__rel$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 126 \rd__go$49 + wire width 6 output 138 \rd__go$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 127 \src1_i$50 + wire width 64 output 139 \src1_i$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 128 \rd__rel$51 + wire width 6 output 140 \rd__rel$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 129 \rd__go$52 + wire width 6 output 141 \rd__go$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 130 \src1_i$53 + wire width 64 output 142 \src1_i$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 131 \rd__rel$54 + wire width 3 output 143 \rd__rel$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 132 \rd__go$55 + wire width 3 output 144 \rd__go$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 133 \src1_i$56 + wire width 64 output 145 \src1_i$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 134 \rd__rel$57 + wire width 2 output 146 \rd__rel$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 135 \rd__go$58 + wire width 2 output 147 \rd__go$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 136 \src1_i$59 + wire width 64 output 148 \src1_i$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 137 \rd__rel$60 + wire width 4 output 149 \rd__rel$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 138 \rd__go$61 + wire width 4 output 150 \rd__go$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 139 \src1_i$62 + wire width 64 output 151 \src1_i$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 output 152 \rd__rel$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 output 153 \rd__go$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 output 154 \src1_i$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 140 \reg2 + wire width 5 output 155 \reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 141 \src2_i + wire width 64 output 156 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 142 \src2_i$63 + wire width 64 output 157 \src2_i$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 143 \src2_i$64 + wire width 64 output 158 \src2_i$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 144 \src2_i$65 + wire width 64 output 159 \src2_i$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 145 \src2_i$66 + wire width 64 output 160 \src2_i$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 146 \src2_i$67 + wire width 64 output 161 \src2_i$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 output 162 \src2_i$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 147 \reg3 + wire width 5 output 163 \reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 148 \src3_i + wire width 64 output 164 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 149 \cr_in1 + wire width 3 output 165 \cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 150 \rd__rel$68 + wire width 4 output 166 \rd__rel$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 151 \rd__go$69 + wire width 4 output 167 \rd__go$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 152 \cr_in2 + wire width 3 output 168 \cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 153 \cr_in2$70 + wire width 3 output 169 \cr_in2$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 154 \fast1 + wire width 3 output 170 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 155 \src1_i$71 + wire width 64 output 171 \src1_i$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 156 \fast2 + wire width 3 output 172 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 157 \src2_i$72 + wire width 64 output 173 \src2_i$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 158 \rego + wire width 5 output 174 \rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 159 \wr__rel + wire width 5 output 175 \wr__rel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 160 \wr__go + wire width 5 output 176 \wr__go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" wire width 5 \wr__go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 161 \wr__rel$73 + wire width 3 output 177 \wr__rel$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 output 178 \wr__go$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 162 \wr__go$74 + wire width 3 \wr__go$90$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \wr__go$74$next + wire width 5 output 179 \wr__rel$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 163 \wr__rel$75 + wire width 5 output 180 \wr__go$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 164 \wr__go$76 + wire width 5 \wr__go$92$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 \wr__go$76$next + wire width 5 output 181 \wr__rel$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 165 \wr__rel$77 + wire width 5 output 182 \wr__go$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 166 \wr__go$78 + wire width 5 \wr__go$94$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \wr__go$78$next + wire width 3 output 183 \wr__rel$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 167 \wr__rel$79 + wire width 3 output 184 \wr__go$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 168 \wr__go$80 + wire width 3 \wr__go$96$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \wr__go$80$next + wire width 3 output 185 \wr__rel$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 output 186 \wr__go$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 \wr__go$98$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 input 169 \o_ok + wire width 1 input 187 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 170 \wr__rel$81 + wire width 2 output 188 \wr__rel$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 171 \wr__go$82 + wire width 2 output 189 \wr__go$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 \wr__go$82$next + wire width 2 \wr__go$100$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 172 \o + wire width 64 output 190 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 173 \ea + wire width 5 output 191 \ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 input 174 \ea_ok + wire width 1 input 192 \ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 175 \ea$83 + wire width 64 output 193 \ea$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 176 \fasto1 + wire width 3 output 194 \fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 177 \wr__rel$84 + wire width 3 output 195 \wr__rel$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 178 \wr__go$85 + wire width 3 output 196 \wr__go$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \wr__go$85$next + wire width 3 \wr__go$103$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 179 \fasto2 + wire width 3 output 197 \fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" - wire width 32 output 180 \opcode_in + wire width 32 output 198 \opcode_in attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -128081,7 +248002,7 @@ module \core attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 3 output 181 \in1_sel + wire width 3 output 199 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -128098,26 +248019,26 @@ module \core attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 4 output 182 \in2_sel + wire width 4 output 200 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 2 output 183 \in3_sel + wire width 2 output 201 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 184 \out_sel + wire width 2 output 202 \out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 2 output 185 \rc_sel + wire width 2 output 203 \rc_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -128127,7 +248048,7 @@ module \core attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 3 output 186 \cr_in + wire width 3 output 204 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -128135,9 +248056,9 @@ module \core attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 187 \cr_out$86 + wire width 3 output 205 \cr_out$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37" - wire width 64 output 188 \nia + wire width 64 output 206 \nia attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -128150,7 +248071,7 @@ module \core attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 189 \function_unit + wire width 10 output 207 \function_unit attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -128224,23 +248145,23 @@ module \core attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 7 output 190 \internal_op + wire width 7 output 208 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 191 \rego_ok + wire width 1 output 209 \rego_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 192 \ea_ok$87 + wire width 1 output 210 \ea_ok$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 10 output 193 \spr1 + wire width 10 output 211 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 194 \spr1_ok + wire width 1 output 212 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 10 output 195 \spro + wire width 10 output 213 \spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 196 \spro_ok + wire width 1 output 214 \spro_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 197 \fasto1_ok + wire width 1 output 215 \fasto1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 198 \fasto2_ok + wire width 1 output 216 \fasto2_ok attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -128248,25 +248169,25 @@ module \core attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 4 output 199 \ldst_len + wire width 4 output 217 \ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 200 \inv_a + wire width 1 output 218 \inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 201 \inv_out + wire width 1 output 219 \inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 202 \cry_out + wire width 1 output 220 \cry_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 203 \is_32b + wire width 1 output 221 \is_32b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 204 \sgn + wire width 1 output 222 \sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 205 \lk$88 + wire width 1 output 223 \lk$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 206 \br + wire width 1 output 224 \br attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 207 \sgn_ext + wire width 1 output 225 \sgn_ext attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 208 \upd + wire width 1 output 226 \upd attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -128298,157 +248219,163 @@ module \core attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 5 output 209 \form + wire width 5 output 227 \form attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 210 \rsrv + wire width 1 output 228 \rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 211 \sgl_pipe + wire width 1 output 229 \sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123" - wire width 8 output 212 \asmcode + wire width 8 output 230 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 1 input 231 \go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" + wire width 1 input 232 \shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 64 output 233 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 213 \go_die_i + wire width 1 input 234 \go_die_i$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 214 \shadown_i + wire width 1 input 235 \shadown_i$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 215 \dest1_o + wire width 64 output 236 \dest1_o$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 216 \go_die_i$89 + wire width 1 input 237 \go_die_i$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 217 \shadown_i$90 + wire width 1 input 238 \shadown_i$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 218 \dest1_o$91 + wire width 64 output 239 \dest1_o$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 219 \go_die_i$92 + wire width 1 input 240 \go_die_i$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 220 \shadown_i$93 + wire width 1 input 241 \shadown_i$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 221 \dest1_o$94 + wire width 64 output 242 \dest1_o$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 222 \go_die_i$95 + wire width 1 input 243 \go_die_i$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 223 \shadown_i$96 + wire width 1 input 244 \shadown_i$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 224 \dest1_o$97 + wire width 64 output 245 \dest1_o$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 225 \go_die_i$98 + wire width 1 input 246 \go_die_i$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 226 \shadown_i$99 + wire width 1 input 247 \shadown_i$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 227 \dest1_o$100 + wire width 64 output 248 \dest1_o$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 228 \go_die_i$101 + wire width 1 input 249 \go_die_i$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 229 \shadown_i$102 + wire width 1 input 250 \shadown_i$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 230 \dest1_o$103 + wire width 64 output 251 \dest1_o$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 231 \go_die_i$104 + wire width 1 input 252 \go_die_i$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112" - wire width 1 output 232 \load_mem_o + wire width 1 output 253 \load_mem_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" - wire width 1 output 233 \stwd_mem_o + wire width 1 output 254 \stwd_mem_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 234 \shadown_i$105 + wire width 1 input 255 \shadown_i$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 output 235 \ldst_port0_is_ld_i + wire width 1 output 256 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 output 236 \ldst_port0_is_st_i + wire width 1 output 257 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 output 237 \ldst_port0_data_len + wire width 4 output 258 \ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 96 output 238 \ldst_port0_addr_i + wire width 96 output 259 \ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 239 \ldst_port0_addr_i_ok + wire width 1 output 260 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 output 240 \ldst_port0_addr_exc_o + wire width 1 output 261 \ldst_port0_addr_exc_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 output 241 \ldst_port0_addr_ok_o + wire width 1 output 262 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 242 \ldst_port0_ld_data_o + wire width 64 output 263 \ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 243 \ldst_port0_ld_data_o_ok + wire width 1 output 264 \ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 244 \ldst_port0_st_data_i + wire width 64 output 265 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 245 \ldst_port0_st_data_i_ok + wire width 1 output 266 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 output 246 \ldst_port0_is_ld_i$106 + wire width 1 output 267 \ldst_port0_is_ld_i$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 1 output 247 \ldst_port0_busy_o + wire width 1 output 268 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 output 248 \ldst_port0_is_st_i$107 + wire width 1 output 269 \ldst_port0_is_st_i$128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 output 249 \ldst_port0_data_len$108 + wire width 4 output 270 \ldst_port0_data_len$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 48 output 250 \ldst_port0_addr_i$109 + wire width 48 output 271 \ldst_port0_addr_i$130 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 251 \ldst_port0_addr_i_ok$110 + wire width 1 output 272 \ldst_port0_addr_i_ok$131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27" - wire width 8 output 252 \x_mask_i + wire width 8 output 273 \x_mask_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26" - wire width 48 output 253 \x_addr_i + wire width 48 output 274 \x_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 output 254 \ldst_port0_addr_ok_o$111 + wire width 1 output 275 \ldst_port0_addr_ok_o$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" - wire width 64 output 255 \m_ld_data_o + wire width 64 output 276 \m_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 256 \ldst_port0_ld_data_o$112 + wire width 64 output 277 \ldst_port0_ld_data_o$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 257 \ldst_port0_ld_data_o_ok$113 + wire width 1 output 278 \ldst_port0_ld_data_o_ok$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42" - wire width 1 output 258 \x_busy_o + wire width 1 output 279 \x_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 259 \ldst_port0_st_data_i_ok$114 + wire width 1 output 280 \ldst_port0_st_data_i_ok$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 260 \ldst_port0_st_data_i$115 + wire width 64 output 281 \ldst_port0_st_data_i$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30" - wire width 64 output 261 \x_st_data_i + wire width 64 output 282 \x_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 input 262 \ldst_port0_addr_exc_o$116 + wire width 1 input 283 \ldst_port0_addr_exc_o$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28" - wire width 1 output 263 \x_ld_i + wire width 1 output 284 \x_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29" - wire width 1 output 264 \x_st_i + wire width 1 output 285 \x_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37" - wire width 1 output 265 \m_valid_i + wire width 1 output 286 \m_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33" - wire width 1 output 266 \x_valid_i + wire width 1 output 287 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" - wire width 1 output 267 \ldst_port0_go_die_i + wire width 1 output 288 \ldst_port0_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" - wire width 1 input 268 \ldst_port0_go_die_i$117 + wire width 1 input 289 \ldst_port0_go_die_i$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 1 output 269 \ldst_port0_busy_o$118 + wire width 1 output 290 \ldst_port0_busy_o$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 270 \dbus__cyc + wire width 1 output 291 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 input 271 \x_stall_i + wire width 1 input 292 \x_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 272 \dbus__ack + wire width 1 input 293 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 273 \dbus__err + wire width 1 input 294 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 274 \dbus__stb + wire width 1 output 295 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 input 275 \dbus__dat_r + wire width 64 input 296 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 45 output 276 \dbus__adr + wire width 45 output 297 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 8 output 277 \dbus__sel + wire width 8 output 298 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 278 \dbus__we + wire width 1 output 299 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 output 279 \dbus__dat_w + wire width 64 output 300 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36" - wire width 1 input 280 \m_stall_i + wire width 1 input 301 \m_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire width 1 output 281 \m_load_err_o + wire width 1 output 302 \m_load_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" - wire width 1 output 282 \m_store_err_o + wire width 1 output 303 \m_store_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" - wire width 45 output 283 \m_badaddr_o + wire width 45 output 304 \m_badaddr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" - wire width 1 output 284 \m_busy_o + wire width 1 output 305 \m_busy_o cell \pdecode2 \pdecode2 connect \bigendian \bigendian connect \raw_opcode_in \raw_opcode_in @@ -128493,7 +248420,7 @@ module \core connect \reg3 \reg3 connect \cr_in1 \cr_in1 connect \cr_in2 \cr_in2 - connect \cr_in2$2 \cr_in2$70 + connect \cr_in2$2 \cr_in2$86 connect \fast1 \fast1 connect \fast2 \fast2 connect \rego \rego @@ -128507,12 +248434,12 @@ module \core connect \out_sel \out_sel connect \rc_sel \rc_sel connect \cr_in \cr_in - connect \cr_out$3 \cr_out$86 + connect \cr_out$3 \cr_out$104 connect \nia \nia connect \function_unit \function_unit connect \internal_op \internal_op connect \rego_ok \rego_ok - connect \ea_ok \ea_ok$87 + connect \ea_ok \ea_ok$105 connect \spr1 \spr1 connect \spr1_ok \spr1_ok connect \spro \spro @@ -128525,7 +248452,7 @@ module \core connect \cry_out \cry_out connect \is_32b \is_32b connect \sgn \sgn - connect \lk$4 \lk$88 + connect \lk$4 \lk$106 connect \br \br connect \sgn_ext \sgn_ext connect \upd \upd @@ -128570,37 +248497,59 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" wire width 4 \fus_rdmaskn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 6 \fus_rdmaskn$119 + wire width 6 \fus_rdmaskn$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 64 \fus_oper_i__imm_data__imm$120 + wire width 64 \fus_oper_i__imm_data__imm$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 \fus_oper_i__imm_data__imm_ok$121 + wire width 1 \fus_oper_i__imm_data__imm_ok$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" + wire width 4 \fus_rdmaskn$143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 4 \fus_rdmaskn$122 + wire width 6 \fus_rdmaskn$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \fus_oper_i__imm_data__imm$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \fus_oper_i__imm_data__imm_ok$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \fus_oper_i__rc__rc$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \fus_oper_i__rc__rc_ok$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \fus_oper_i__oe__oe$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \fus_oper_i__oe__oe_ok$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \fus_oper_i__zero_a$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \fus_oper_i__write_cr__data$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \fus_oper_i__write_cr__ok$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \fus_oper_i__insn$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 6 \fus_rdmaskn$123 + wire width 3 \fus_rdmaskn$155 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 64 \fus_oper_i__imm_data__imm$124 + wire width 64 \fus_oper_i__imm_data__imm$156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__imm_data__imm_ok$125 + wire width 1 \fus_oper_i__imm_data__imm_ok$157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__rc__rc$126 + wire width 1 \fus_oper_i__rc__rc$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__rc__rc_ok$127 + wire width 1 \fus_oper_i__rc__rc_ok$159 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__oe__oe$128 + wire width 1 \fus_oper_i__oe__oe$160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__oe__oe_ok$129 + wire width 1 \fus_oper_i__oe__oe_ok$161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__zero_a$130 + wire width 1 \fus_oper_i__zero_a$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 3 \fus_oper_i__write_cr__data$131 + wire width 3 \fus_oper_i__write_cr__data$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__write_cr__ok$132 + wire width 1 \fus_oper_i__write_cr__ok$164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 32 \fus_oper_i__insn$133 + wire width 32 \fus_oper_i__insn$165 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 2 \fus_rdmaskn$134 + wire width 2 \fus_rdmaskn$166 attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -128613,81 +248562,87 @@ module \core attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \fus_oper_i__fn_unit$135 + wire width 10 \fus_oper_i__fn_unit$167 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 64 \fus_oper_i__imm_data__imm$136 + wire width 64 \fus_oper_i__imm_data__imm$168 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \fus_oper_i__imm_data__imm_ok$137 + wire width 1 \fus_oper_i__imm_data__imm_ok$169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \fus_oper_i__rc__rc$138 + wire width 1 \fus_oper_i__rc__rc$170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \fus_oper_i__rc__rc_ok$139 + wire width 1 \fus_oper_i__rc__rc_ok$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \fus_oper_i__oe__oe$140 + wire width 1 \fus_oper_i__oe__oe$172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \fus_oper_i__oe__oe_ok$141 + wire width 1 \fus_oper_i__oe__oe_ok$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 3 \fus_oper_i__write_cr__data$142 + wire width 3 \fus_oper_i__write_cr__data$174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \fus_oper_i__write_cr__ok$143 + wire width 1 \fus_oper_i__write_cr__ok$175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 32 \fus_oper_i__insn$144 + wire width 32 \fus_oper_i__insn$176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 4 \fus_rdmaskn$145 + wire width 4 \fus_rdmaskn$177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 64 \fus_oper_i__imm_data__imm$146 + wire width 64 \fus_oper_i__imm_data__imm$178 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 \fus_oper_i__imm_data__imm_ok$147 + wire width 1 \fus_oper_i__imm_data__imm_ok$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 3 \fus_rdmaskn$148 + wire width 3 \fus_rdmaskn$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" wire width 64 \fus_src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 1 \fus_src3_i$149 + wire width 1 \fus_src3_i$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 1 \fus_src3_i$182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" wire width 2 \fus_src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 2 \fus_src4_i$150 + wire width 2 \fus_src4_i$183 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 32 \fus_src3_i$151 + wire width 32 \fus_src3_i$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 \fus_src4_i$152 + wire width 4 \fus_src4_i$185 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 \fus_src3_i$153 + wire width 4 \fus_src3_i$186 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" wire width 4 \fus_src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" wire width 4 \fus_src6_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 \fus_src3_i$154 + wire width 64 \fus_src3_i$187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 \fus_src4_i$155 + wire width 64 \fus_src4_i$188 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 \fus_src4_i$156 + wire width 64 \fus_src4_i$189 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 \fus_src5_i$157 + wire width 64 \fus_src5_i$190 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 \fus_src6_i$158 + wire width 64 \fus_src6_i$191 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_o_ok$159 + wire width 1 \fus_o_ok$192 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fus_o_ok$193 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_o_ok$160 + wire width 1 \fus_o_ok$194 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_o_ok$161 + wire width 1 \fus_o_ok$195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_o_ok$162 + wire width 1 \fus_o_ok$196 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 \fus_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_o$163 + wire width 64 \fus_o$197 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_o$164 + wire width 64 \fus_o$198 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_o$165 + wire width 64 \fus_o$199 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_o$166 + wire width 64 \fus_o$200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \fus_o$201 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -128695,63 +248650,79 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_cr_a_ok$167 + wire width 1 \fus_cr_a_ok$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fus_cr_a_ok$203 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_cr_a_ok$168 + wire width 1 \fus_cr_a_ok$204 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_cr_a_ok$169 + wire width 1 \fus_cr_a_ok$205 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 4 \fus_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 \fus_cr_a$170 + wire width 4 \fus_cr_a$206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 4 \fus_cr_a$207 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 \fus_cr_a$171 + wire width 4 \fus_cr_a$208 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 \fus_cr_a$172 + wire width 4 \fus_cr_a$209 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_xer_ca_ok$173 + wire width 1 \fus_xer_ca_ok$210 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_xer_ca_ok$174 + wire width 1 \fus_xer_ca_ok$211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fus_xer_ca_ok$212 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 2 \fus_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 \fus_xer_ca$175 + wire width 2 \fus_xer_ca$213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \fus_xer_ca$214 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 \fus_xer_ca$176 + wire width 2 \fus_xer_ca$215 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fus_xer_ov_ok$216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 2 \fus_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \fus_xer_ov$217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fus_xer_so_ok$218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fus_xer_so$219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_spr1_ok$177 + wire width 1 \fus_spr1_ok$220 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 \fus_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_spr1$178 + wire width 64 \fus_spr1$221 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_spr2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_spr2_ok$179 + wire width 1 \fus_spr2_ok$222 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 \fus_spr2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_spr2$180 + wire width 64 \fus_spr2$223 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_nia_ok$181 + wire width 1 \fus_nia_ok$224 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 \fus_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_nia$182 + wire width 64 \fus_nia$225 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_msr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -128797,17 +248768,17 @@ module \core connect \oper_i__write_cr_whole \oper_i__write_cr_whole connect \issue_i$4 \issue_i$3 connect \busy_o$5 \busy_o$4 - connect \rdmaskn$6 \fus_rdmaskn$119 + connect \rdmaskn$6 \fus_rdmaskn$140 connect \oper_i__insn_type$7 \oper_i__insn_type$6 connect \oper_i__fn_unit$8 \oper_i__fn_unit$7 - connect \oper_i__imm_data__imm$9 \fus_oper_i__imm_data__imm$120 - connect \oper_i__imm_data__imm_ok$10 \fus_oper_i__imm_data__imm_ok$121 + connect \oper_i__imm_data__imm$9 \fus_oper_i__imm_data__imm$141 + connect \oper_i__imm_data__imm_ok$10 \fus_oper_i__imm_data__imm_ok$142 connect \oper_i__lk$11 \oper_i__lk$8 connect \oper_i__is_32bit$12 \oper_i__is_32bit$9 connect \oper_i__insn$13 \oper_i__insn$10 connect \issue_i$14 \issue_i$11 connect \busy_o$15 \busy_o$12 - connect \rdmaskn$16 \fus_rdmaskn$122 + connect \rdmaskn$16 \fus_rdmaskn$143 connect \oper_i__insn_type$17 \oper_i__insn_type$13 connect \oper_i__fn_unit$18 \oper_i__fn_unit$14 connect \oper_i__insn$19 \oper_i__insn$15 @@ -128816,188 +248787,231 @@ module \core connect \oper_i__trapaddr \oper_i__trapaddr connect \issue_i$21 \issue_i$17 connect \busy_o$22 \busy_o$18 - connect \rdmaskn$23 \fus_rdmaskn$123 + connect \rdmaskn$23 \fus_rdmaskn$144 connect \oper_i__insn_type$24 \oper_i__insn_type$19 connect \oper_i__fn_unit$25 \oper_i__fn_unit$20 - connect \oper_i__imm_data__imm$26 \fus_oper_i__imm_data__imm$124 - connect \oper_i__imm_data__imm_ok$27 \fus_oper_i__imm_data__imm_ok$125 + connect \oper_i__imm_data__imm$26 \fus_oper_i__imm_data__imm$145 + connect \oper_i__imm_data__imm_ok$27 \fus_oper_i__imm_data__imm_ok$146 connect \oper_i__lk$28 \oper_i__lk$21 - connect \oper_i__rc__rc$29 \fus_oper_i__rc__rc$126 - connect \oper_i__rc__rc_ok$30 \fus_oper_i__rc__rc_ok$127 - connect \oper_i__oe__oe$31 \fus_oper_i__oe__oe$128 - connect \oper_i__oe__oe_ok$32 \fus_oper_i__oe__oe_ok$129 + connect \oper_i__rc__rc$29 \fus_oper_i__rc__rc$147 + connect \oper_i__rc__rc_ok$30 \fus_oper_i__rc__rc_ok$148 + connect \oper_i__oe__oe$31 \fus_oper_i__oe__oe$149 + connect \oper_i__oe__oe_ok$32 \fus_oper_i__oe__oe_ok$150 connect \oper_i__invert_a$33 \oper_i__invert_a$22 - connect \oper_i__zero_a$34 \fus_oper_i__zero_a$130 + connect \oper_i__zero_a$34 \fus_oper_i__zero_a$151 connect \oper_i__input_carry$35 \oper_i__input_carry$23 connect \oper_i__invert_out$36 \oper_i__invert_out$24 - connect \oper_i__write_cr__data$37 \fus_oper_i__write_cr__data$131 - connect \oper_i__write_cr__ok$38 \fus_oper_i__write_cr__ok$132 + connect \oper_i__write_cr__data$37 \fus_oper_i__write_cr__data$152 + connect \oper_i__write_cr__ok$38 \fus_oper_i__write_cr__ok$153 connect \oper_i__output_carry$39 \oper_i__output_carry$25 connect \oper_i__is_32bit$40 \oper_i__is_32bit$26 connect \oper_i__is_signed$41 \oper_i__is_signed$27 connect \oper_i__data_len$42 \oper_i__data_len$28 - connect \oper_i__insn$43 \fus_oper_i__insn$133 + connect \oper_i__insn$43 \fus_oper_i__insn$154 connect \issue_i$44 \issue_i$29 connect \busy_o$45 \busy_o$30 - connect \rdmaskn$46 \fus_rdmaskn$134 + connect \rdmaskn$46 \fus_rdmaskn$155 connect \oper_i__insn_type$47 \oper_i__insn_type$31 - connect \oper_i__fn_unit$48 \fus_oper_i__fn_unit$135 - connect \oper_i__imm_data__imm$49 \fus_oper_i__imm_data__imm$136 - connect \oper_i__imm_data__imm_ok$50 \fus_oper_i__imm_data__imm_ok$137 - connect \oper_i__rc__rc$51 \fus_oper_i__rc__rc$138 - connect \oper_i__rc__rc_ok$52 \fus_oper_i__rc__rc_ok$139 - connect \oper_i__oe__oe$53 \fus_oper_i__oe__oe$140 - connect \oper_i__oe__oe_ok$54 \fus_oper_i__oe__oe_ok$141 - connect \oper_i__write_cr__data$55 \fus_oper_i__write_cr__data$142 - connect \oper_i__write_cr__ok$56 \fus_oper_i__write_cr__ok$143 - connect \oper_i__input_carry$57 \oper_i__input_carry$32 - connect \oper_i__output_carry$58 \oper_i__output_carry$33 - connect \oper_i__input_cr$59 \oper_i__input_cr$34 - connect \oper_i__output_cr$60 \oper_i__output_cr$35 - connect \oper_i__is_32bit$61 \oper_i__is_32bit$36 - connect \oper_i__is_signed$62 \oper_i__is_signed$37 - connect \oper_i__insn$63 \fus_oper_i__insn$144 - connect \issue_i$64 \issue_i$38 - connect \busy_o$65 \busy_o$39 - connect \rdmaskn$66 \fus_rdmaskn$145 - connect \oper_i__insn_type$67 \oper_i__insn_type$40 - connect \oper_i__imm_data__imm$68 \fus_oper_i__imm_data__imm$146 - connect \oper_i__imm_data__imm_ok$69 \fus_oper_i__imm_data__imm_ok$147 - connect \oper_i__zero_a$70 \oper_i__zero_a - connect \oper_i__is_32bit$71 \oper_i__is_32bit$41 - connect \oper_i__is_signed$72 \oper_i__is_signed$42 - connect \oper_i__data_len$73 \oper_i__data_len$43 - connect \oper_i__byte_reverse$74 \oper_i__byte_reverse$44 - connect \oper_i__sign_extend$75 \oper_i__sign_extend$45 + connect \oper_i__fn_unit$48 \oper_i__fn_unit$32 + connect \oper_i__imm_data__imm$49 \fus_oper_i__imm_data__imm$156 + connect \oper_i__imm_data__imm_ok$50 \fus_oper_i__imm_data__imm_ok$157 + connect \oper_i__lk$51 \oper_i__lk$33 + connect \oper_i__rc__rc$52 \fus_oper_i__rc__rc$158 + connect \oper_i__rc__rc_ok$53 \fus_oper_i__rc__rc_ok$159 + connect \oper_i__oe__oe$54 \fus_oper_i__oe__oe$160 + connect \oper_i__oe__oe_ok$55 \fus_oper_i__oe__oe_ok$161 + connect \oper_i__invert_a$56 \oper_i__invert_a$34 + connect \oper_i__zero_a$57 \fus_oper_i__zero_a$162 + connect \oper_i__input_carry$58 \oper_i__input_carry$35 + connect \oper_i__invert_out$59 \oper_i__invert_out$36 + connect \oper_i__write_cr__data$60 \fus_oper_i__write_cr__data$163 + connect \oper_i__write_cr__ok$61 \fus_oper_i__write_cr__ok$164 + connect \oper_i__output_carry$62 \oper_i__output_carry$37 + connect \oper_i__is_32bit$63 \oper_i__is_32bit$38 + connect \oper_i__is_signed$64 \oper_i__is_signed$39 + connect \oper_i__data_len$65 \oper_i__data_len$40 + connect \oper_i__insn$66 \fus_oper_i__insn$165 + connect \issue_i$67 \issue_i$41 + connect \busy_o$68 \busy_o$42 + connect \rdmaskn$69 \fus_rdmaskn$166 + connect \oper_i__insn_type$70 \oper_i__insn_type$43 + connect \oper_i__fn_unit$71 \fus_oper_i__fn_unit$167 + connect \oper_i__imm_data__imm$72 \fus_oper_i__imm_data__imm$168 + connect \oper_i__imm_data__imm_ok$73 \fus_oper_i__imm_data__imm_ok$169 + connect \oper_i__rc__rc$74 \fus_oper_i__rc__rc$170 + connect \oper_i__rc__rc_ok$75 \fus_oper_i__rc__rc_ok$171 + connect \oper_i__oe__oe$76 \fus_oper_i__oe__oe$172 + connect \oper_i__oe__oe_ok$77 \fus_oper_i__oe__oe_ok$173 + connect \oper_i__write_cr__data$78 \fus_oper_i__write_cr__data$174 + connect \oper_i__write_cr__ok$79 \fus_oper_i__write_cr__ok$175 + connect \oper_i__input_carry$80 \oper_i__input_carry$44 + connect \oper_i__output_carry$81 \oper_i__output_carry$45 + connect \oper_i__input_cr$82 \oper_i__input_cr$46 + connect \oper_i__output_cr$83 \oper_i__output_cr$47 + connect \oper_i__is_32bit$84 \oper_i__is_32bit$48 + connect \oper_i__is_signed$85 \oper_i__is_signed$49 + connect \oper_i__insn$86 \fus_oper_i__insn$176 + connect \issue_i$87 \issue_i$50 + connect \busy_o$88 \busy_o$51 + connect \rdmaskn$89 \fus_rdmaskn$177 + connect \oper_i__insn_type$90 \oper_i__insn_type$52 + connect \oper_i__imm_data__imm$91 \fus_oper_i__imm_data__imm$178 + connect \oper_i__imm_data__imm_ok$92 \fus_oper_i__imm_data__imm_ok$179 + connect \oper_i__zero_a$93 \oper_i__zero_a + connect \oper_i__is_32bit$94 \oper_i__is_32bit$53 + connect \oper_i__is_signed$95 \oper_i__is_signed$54 + connect \oper_i__data_len$96 \oper_i__data_len$55 + connect \oper_i__byte_reverse$97 \oper_i__byte_reverse$56 + connect \oper_i__sign_extend$98 \oper_i__sign_extend$57 connect \oper_i__update \oper_i__update - connect \issue_i$76 \issue_i$46 - connect \busy_o$77 \busy_o$47 - connect \rdmaskn$78 \fus_rdmaskn$148 + connect \issue_i$99 \issue_i$58 + connect \busy_o$100 \busy_o$59 + connect \rdmaskn$101 \fus_rdmaskn$180 connect \rd__rel \rd__rel connect \rd__go \rd__go connect \src1_i \src1_i - connect \rd__rel$79 \rd__rel$48 - connect \rd__go$80 \rd__go$49 - connect \src1_i$81 \src1_i$50 - connect \rd__rel$82 \rd__rel$51 - connect \rd__go$83 \rd__go$52 - connect \src1_i$84 \src1_i$53 - connect \rd__rel$85 \rd__rel$54 - connect \rd__go$86 \rd__go$55 - connect \src1_i$87 \src1_i$56 - connect \rd__rel$88 \rd__rel$57 - connect \rd__go$89 \rd__go$58 - connect \src1_i$90 \src1_i$59 - connect \rd__rel$91 \rd__rel$60 - connect \rd__go$92 \rd__go$61 - connect \src1_i$93 \src1_i$62 + connect \rd__rel$102 \rd__rel$60 + connect \rd__go$103 \rd__go$61 + connect \src1_i$104 \src1_i$62 + connect \rd__rel$105 \rd__rel$63 + connect \rd__go$106 \rd__go$64 + connect \src1_i$107 \src1_i$65 + connect \rd__rel$108 \rd__rel$66 + connect \rd__go$109 \rd__go$67 + connect \src1_i$110 \src1_i$68 + connect \rd__rel$111 \rd__rel$69 + connect \rd__go$112 \rd__go$70 + connect \src1_i$113 \src1_i$71 + connect \rd__rel$114 \rd__rel$72 + connect \rd__go$115 \rd__go$73 + connect \src1_i$116 \src1_i$74 + connect \rd__rel$117 \rd__rel$75 + connect \rd__go$118 \rd__go$76 + connect \src1_i$119 \src1_i$77 connect \src2_i \src2_i - connect \src2_i$94 \src2_i$63 - connect \src2_i$95 \src2_i$64 - connect \src2_i$96 \src2_i$65 - connect \src2_i$97 \src2_i$66 - connect \src2_i$98 \src2_i$67 + connect \src2_i$120 \src2_i$78 + connect \src2_i$121 \src2_i$79 + connect \src2_i$122 \src2_i$80 + connect \src2_i$123 \src2_i$81 + connect \src2_i$124 \src2_i$82 + connect \src2_i$125 \src2_i$83 connect \src3_i \fus_src3_i - connect \src3_i$99 \src3_i - connect \src3_i$100 \fus_src3_i$149 + connect \src3_i$126 \src3_i + connect \src3_i$127 \fus_src3_i$181 + connect \src3_i$128 \fus_src3_i$182 connect \src4_i \fus_src4_i - connect \src4_i$101 \fus_src4_i$150 - connect \src3_i$102 \fus_src3_i$151 - connect \src4_i$103 \fus_src4_i$152 - connect \rd__rel$104 \rd__rel$68 - connect \rd__go$105 \rd__go$69 - connect \src3_i$106 \fus_src3_i$153 + connect \src4_i$129 \fus_src4_i$183 + connect \src3_i$130 \fus_src3_i$184 + connect \src4_i$131 \fus_src4_i$185 + connect \rd__rel$132 \rd__rel$84 + connect \rd__go$133 \rd__go$85 + connect \src3_i$134 \fus_src3_i$186 connect \src5_i \fus_src5_i connect \src6_i \fus_src6_i - connect \src1_i$107 \src1_i$71 - connect \src3_i$108 \fus_src3_i$154 - connect \src2_i$109 \src2_i$72 - connect \src4_i$110 \fus_src4_i$155 - connect \src4_i$111 \fus_src4_i$156 - connect \src5_i$112 \fus_src5_i$157 - connect \src6_i$113 \fus_src6_i$158 + connect \src1_i$135 \src1_i$87 + connect \src3_i$136 \fus_src3_i$187 + connect \src2_i$137 \src2_i$88 + connect \src4_i$138 \fus_src4_i$188 + connect \src4_i$139 \fus_src4_i$189 + connect \src5_i$140 \fus_src5_i$190 + connect \src6_i$141 \fus_src6_i$191 connect \o_ok \fus_o_ok connect \wr__rel \wr__rel connect \wr__go \wr__go - connect \o_ok$114 \fus_o_ok$159 - connect \wr__rel$115 \wr__rel$73 - connect \wr__go$116 \wr__go$74 - connect \o_ok$117 \fus_o_ok$160 - connect \wr__rel$118 \wr__rel$75 - connect \wr__go$119 \wr__go$76 - connect \o_ok$120 \fus_o_ok$161 - connect \wr__rel$121 \wr__rel$77 - connect \wr__go$122 \wr__go$78 - connect \o_ok$123 \fus_o_ok$162 - connect \wr__rel$124 \wr__rel$79 - connect \wr__go$125 \wr__go$80 - connect \wr__rel$126 \wr__rel$81 - connect \wr__go$127 \wr__go$82 + connect \o_ok$142 \fus_o_ok$192 + connect \wr__rel$143 \wr__rel$89 + connect \wr__go$144 \wr__go$90 + connect \o_ok$145 \fus_o_ok$193 + connect \wr__rel$146 \wr__rel$91 + connect \wr__go$147 \wr__go$92 + connect \o_ok$148 \fus_o_ok$194 + connect \wr__rel$149 \wr__rel$93 + connect \wr__go$150 \wr__go$94 + connect \o_ok$151 \fus_o_ok$195 + connect \wr__rel$152 \wr__rel$95 + connect \wr__go$153 \wr__go$96 + connect \o_ok$154 \fus_o_ok$196 + connect \wr__rel$155 \wr__rel$97 + connect \wr__go$156 \wr__go$98 + connect \wr__rel$157 \wr__rel$99 + connect \wr__go$158 \wr__go$100 connect \o \fus_o - connect \o$128 \fus_o$163 - connect \o$129 \fus_o$164 - connect \o$130 \fus_o$165 - connect \o$131 \fus_o$166 - connect \o$132 \o - connect \ea \ea$83 + connect \o$159 \fus_o$197 + connect \o$160 \fus_o$198 + connect \o$161 \fus_o$199 + connect \o$162 \fus_o$200 + connect \o$163 \fus_o$201 + connect \o$164 \o + connect \ea \ea$101 connect \full_cr_ok \fus_full_cr_ok connect \full_cr \fus_full_cr connect \cr_a_ok \fus_cr_a_ok - connect \cr_a_ok$133 \fus_cr_a_ok$167 - connect \cr_a_ok$134 \fus_cr_a_ok$168 - connect \cr_a_ok$135 \fus_cr_a_ok$169 + connect \cr_a_ok$165 \fus_cr_a_ok$202 + connect \cr_a_ok$166 \fus_cr_a_ok$203 + connect \cr_a_ok$167 \fus_cr_a_ok$204 + connect \cr_a_ok$168 \fus_cr_a_ok$205 connect \cr_a \fus_cr_a - connect \cr_a$136 \fus_cr_a$170 - connect \cr_a$137 \fus_cr_a$171 - connect \cr_a$138 \fus_cr_a$172 + connect \cr_a$169 \fus_cr_a$206 + connect \cr_a$170 \fus_cr_a$207 + connect \cr_a$171 \fus_cr_a$208 + connect \cr_a$172 \fus_cr_a$209 connect \xer_ca_ok \fus_xer_ca_ok - connect \xer_ca_ok$139 \fus_xer_ca_ok$173 - connect \xer_ca_ok$140 \fus_xer_ca_ok$174 + connect \xer_ca_ok$173 \fus_xer_ca_ok$210 + connect \xer_ca_ok$174 \fus_xer_ca_ok$211 + connect \xer_ca_ok$175 \fus_xer_ca_ok$212 connect \xer_ca \fus_xer_ca - connect \xer_ca$141 \fus_xer_ca$175 - connect \xer_ca$142 \fus_xer_ca$176 + connect \xer_ca$176 \fus_xer_ca$213 + connect \xer_ca$177 \fus_xer_ca$214 + connect \xer_ca$178 \fus_xer_ca$215 connect \xer_ov_ok \fus_xer_ov_ok + connect \xer_ov_ok$179 \fus_xer_ov_ok$216 connect \xer_ov \fus_xer_ov + connect \xer_ov$180 \fus_xer_ov$217 connect \xer_so_ok \fus_xer_so_ok + connect \xer_so_ok$181 \fus_xer_so_ok$218 connect \xer_so \fus_xer_so + connect \xer_so$182 \fus_xer_so$219 connect \spr1_ok \fus_spr1_ok - connect \wr__rel$143 \wr__rel$84 - connect \wr__go$144 \wr__go$85 - connect \spr1_ok$145 \fus_spr1_ok$177 + connect \wr__rel$183 \wr__rel$102 + connect \wr__go$184 \wr__go$103 + connect \spr1_ok$185 \fus_spr1_ok$220 connect \spr1 \fus_spr1 - connect \spr1$146 \fus_spr1$178 + connect \spr1$186 \fus_spr1$221 connect \spr2_ok \fus_spr2_ok - connect \spr2_ok$147 \fus_spr2_ok$179 + connect \spr2_ok$187 \fus_spr2_ok$222 connect \spr2 \fus_spr2 - connect \spr2$148 \fus_spr2$180 + connect \spr2$188 \fus_spr2$223 connect \nia_ok \fus_nia_ok - connect \nia_ok$149 \fus_nia_ok$181 + connect \nia_ok$189 \fus_nia_ok$224 connect \nia \fus_nia - connect \nia$150 \fus_nia$182 + connect \nia$190 \fus_nia$225 connect \msr_ok \fus_msr_ok connect \msr \fus_msr connect \go_die_i \go_die_i connect \shadown_i \shadown_i connect \dest1_o \dest1_o - connect \go_die_i$151 \go_die_i$89 - connect \shadown_i$152 \shadown_i$90 - connect \dest1_o$153 \dest1_o$91 - connect \go_die_i$154 \go_die_i$92 - connect \shadown_i$155 \shadown_i$93 - connect \dest1_o$156 \dest1_o$94 - connect \go_die_i$157 \go_die_i$95 - connect \shadown_i$158 \shadown_i$96 - connect \dest1_o$159 \dest1_o$97 - connect \go_die_i$160 \go_die_i$98 - connect \shadown_i$161 \shadown_i$99 - connect \dest1_o$162 \dest1_o$100 - connect \go_die_i$163 \go_die_i$101 - connect \shadown_i$164 \shadown_i$102 - connect \dest1_o$165 \dest1_o$103 - connect \go_die_i$166 \go_die_i$104 + connect \go_die_i$191 \go_die_i$107 + connect \shadown_i$192 \shadown_i$108 + connect \dest1_o$193 \dest1_o$109 + connect \go_die_i$194 \go_die_i$110 + connect \shadown_i$195 \shadown_i$111 + connect \dest1_o$196 \dest1_o$112 + connect \go_die_i$197 \go_die_i$113 + connect \shadown_i$198 \shadown_i$114 + connect \dest1_o$199 \dest1_o$115 + connect \go_die_i$200 \go_die_i$116 + connect \shadown_i$201 \shadown_i$117 + connect \dest1_o$202 \dest1_o$118 + connect \go_die_i$203 \go_die_i$119 + connect \shadown_i$204 \shadown_i$120 + connect \dest1_o$205 \dest1_o$121 + connect \go_die_i$206 \go_die_i$122 + connect \shadown_i$207 \shadown_i$123 + connect \dest1_o$208 \dest1_o$124 + connect \go_die_i$209 \go_die_i$125 connect \load_mem_o \load_mem_o connect \stwd_mem_o \stwd_mem_o - connect \shadown_i$167 \shadown_i$105 + connect \shadown_i$210 \shadown_i$126 connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i connect \ldst_port0_is_st_i \ldst_port0_is_st_i connect \ldst_port0_data_len \ldst_port0_data_len @@ -129024,30 +249038,30 @@ module \core connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok connect \ldst_port0_st_data_i \ldst_port0_st_data_i connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok - connect \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i$106 + connect \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i$127 connect \ldst_port0_busy_o \ldst_port0_busy_o - connect \ldst_port0_is_st_i$2 \ldst_port0_is_st_i$107 - connect \ldst_port0_data_len$3 \ldst_port0_data_len$108 - connect \ldst_port0_addr_i$4 \ldst_port0_addr_i$109 - connect \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok$110 + connect \ldst_port0_is_st_i$2 \ldst_port0_is_st_i$128 + connect \ldst_port0_data_len$3 \ldst_port0_data_len$129 + connect \ldst_port0_addr_i$4 \ldst_port0_addr_i$130 + connect \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok$131 connect \x_mask_i \x_mask_i connect \x_addr_i \x_addr_i - connect \ldst_port0_addr_ok_o$6 \ldst_port0_addr_ok_o$111 + connect \ldst_port0_addr_ok_o$6 \ldst_port0_addr_ok_o$132 connect \m_ld_data_o \m_ld_data_o - connect \ldst_port0_ld_data_o$7 \ldst_port0_ld_data_o$112 - connect \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o_ok$113 + connect \ldst_port0_ld_data_o$7 \ldst_port0_ld_data_o$133 + connect \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o_ok$134 connect \x_busy_o \x_busy_o - connect \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i_ok$114 - connect \ldst_port0_st_data_i$10 \ldst_port0_st_data_i$115 + connect \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i_ok$135 + connect \ldst_port0_st_data_i$10 \ldst_port0_st_data_i$136 connect \x_st_data_i \x_st_data_i - connect \ldst_port0_addr_exc_o$11 \ldst_port0_addr_exc_o$116 + connect \ldst_port0_addr_exc_o$11 \ldst_port0_addr_exc_o$137 connect \x_ld_i \x_ld_i connect \x_st_i \x_st_i connect \m_valid_i \m_valid_i connect \x_valid_i \x_valid_i connect \ldst_port0_go_die_i \ldst_port0_go_die_i - connect \ldst_port0_go_die_i$12 \ldst_port0_go_die_i$117 - connect \ldst_port0_busy_o$13 \ldst_port0_busy_o$118 + connect \ldst_port0_go_die_i$12 \ldst_port0_go_die_i$138 + connect \ldst_port0_busy_o$13 \ldst_port0_busy_o$139 connect \dbus__cyc \dbus__cyc connect \x_stall_i \x_stall_i connect \dbus__ack \dbus__ack @@ -129085,13 +249099,13 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \int_data_i$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \int_wen$183 + wire width 32 \int_wen$226 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \int_wen$183$next + wire width 32 \int_wen$226$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_data_i$184 + wire width 64 \int_data_i$227 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_data_i$184$next + wire width 64 \int_data_i$227$next cell \int \int connect \rst \rst connect \clk \clk @@ -129103,8 +249117,8 @@ module \core connect \src3__data_o \int_src3__data_o connect \wen \int_wen connect \data_i \int_data_i - connect \wen$1 \int_wen$183 - connect \data_i$2 \int_data_i$184 + connect \wen$1 \int_wen$226 + connect \data_i$2 \int_data_i$227 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 8 \cr_full_rd__ren @@ -129171,21 +249185,21 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 \xer_data_i$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$185 + wire width 3 \xer_wen$228 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$185$next + wire width 3 \xer_wen$228$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$186 + wire width 2 \xer_data_i$229 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$186$next + wire width 2 \xer_data_i$229$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$187 + wire width 3 \xer_wen$230 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$187$next + wire width 3 \xer_wen$230$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$188 + wire width 2 \xer_data_i$231 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$188$next + wire width 2 \xer_data_i$231$next cell \xer \xer connect \rst \rst connect \clk \clk @@ -129195,10 +249209,10 @@ module \core connect \src2__data_o \xer_src2__data_o connect \wen \xer_wen connect \data_i \xer_data_i - connect \wen$1 \xer_wen$185 - connect \data_i$2 \xer_data_i$186 - connect \wen$3 \xer_wen$187 - connect \data_i$4 \xer_data_i$188 + connect \wen$1 \xer_wen$228 + connect \data_i$2 \xer_data_i$229 + connect \wen$3 \xer_wen$230 + connect \data_i$4 \xer_data_i$231 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 8 \fast_src3__ren @@ -129225,25 +249239,25 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \fast_data_i$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \fast_wen$189 + wire width 8 \fast_wen$232 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \fast_wen$189$next + wire width 8 \fast_wen$232$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_data_i$190 + wire width 64 \fast_data_i$233 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_data_i$190$next + wire width 64 \fast_data_i$233$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_data_i$191 + wire width 64 \fast_data_i$234 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_data_i$191$next + wire width 64 \fast_data_i$234$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \fast_wen$192 + wire width 8 \fast_wen$235 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \fast_wen$192$next + wire width 8 \fast_wen$235$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_data_i$193 + wire width 64 \fast_data_i$236 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_data_i$193$next + wire width 64 \fast_data_i$236$next cell \fast \fast connect \d_rd1__ren \d_rd1__ren connect \d_rd1__data_o \d_rd1__data_o @@ -129262,11 +249276,11 @@ module \core connect \src2__data_o \fast_src2__data_o connect \wen$1 \fast_wen connect \data_i$2 \fast_data_i - connect \wen$3 \fast_wen$189 - connect \data_i$4 \fast_data_i$190 - connect \data_i$5 \fast_data_i$191 - connect \wen$6 \fast_wen$192 - connect \data_i$7 \fast_data_i$193 + connect \wen$3 \fast_wen$232 + connect \data_i$4 \fast_data_i$233 + connect \data_i$5 \fast_data_i$234 + connect \wen$6 \fast_wen$235 + connect \data_i$7 \fast_data_i$236 end cell \spr \spr connect \rst \rst @@ -129275,9 +249289,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \rdpick_INT_ra_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 6 \rdpick_INT_ra_i + wire width 7 \rdpick_INT_ra_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 6 \rdpick_INT_ra_o + wire width 7 \rdpick_INT_ra_o cell \rdpick_INT_ra \rdpick_INT_ra connect \en_o \rdpick_INT_ra_en_o connect \i \rdpick_INT_ra_i @@ -129286,9 +249300,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \rdpick_INT_rb_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 6 \rdpick_INT_rb_i + wire width 7 \rdpick_INT_rb_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 6 \rdpick_INT_rb_o + wire width 7 \rdpick_INT_rb_o cell \rdpick_INT_rb \rdpick_INT_rb connect \en_o \rdpick_INT_rb_en_o connect \i \rdpick_INT_rb_i @@ -129308,9 +249322,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \rdpick_XER_xer_so_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \rdpick_XER_xer_so_i + wire width 2 \rdpick_XER_xer_so_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \rdpick_XER_xer_so_o + wire width 2 \rdpick_XER_xer_so_o cell \rdpick_XER_xer_so \rdpick_XER_xer_so connect \en_o \rdpick_XER_xer_so_en_o connect \i \rdpick_XER_xer_so_i @@ -129418,9 +249432,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \wrpick_INT_o_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 6 \wrpick_INT_o_i + wire width 7 \wrpick_INT_o_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 6 \wrpick_INT_o_o + wire width 7 \wrpick_INT_o_o cell \wrpick_INT_o \wrpick_INT_o connect \en_o \wrpick_INT_o_en_o connect \i \wrpick_INT_o_i @@ -129451,9 +249465,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \wrpick_CR_cr_a_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 4 \wrpick_CR_cr_a_i + wire width 5 \wrpick_CR_cr_a_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 4 \wrpick_CR_cr_a_o + wire width 5 \wrpick_CR_cr_a_o cell \wrpick_CR_cr_a \wrpick_CR_cr_a connect \en_o \wrpick_CR_cr_a_en_o connect \i \wrpick_CR_cr_a_i @@ -129462,9 +249476,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \wrpick_XER_xer_ca_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 3 \wrpick_XER_xer_ca_i + wire width 4 \wrpick_XER_xer_ca_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 3 \wrpick_XER_xer_ca_o + wire width 4 \wrpick_XER_xer_ca_o cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca connect \en_o \wrpick_XER_xer_ca_en_o connect \i \wrpick_XER_xer_ca_i @@ -129473,9 +249487,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \wrpick_XER_xer_ov_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \wrpick_XER_xer_ov_i + wire width 2 \wrpick_XER_xer_ov_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \wrpick_XER_xer_ov_o + wire width 2 \wrpick_XER_xer_ov_o cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov connect \en_o \wrpick_XER_xer_ov_en_o connect \i \wrpick_XER_xer_ov_i @@ -129484,9 +249498,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \wrpick_XER_xer_so_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \wrpick_XER_xer_so_i + wire width 2 \wrpick_XER_xer_so_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \wrpick_XER_xer_so_o + wire width 2 \wrpick_XER_xer_so_o cell \wrpick_XER_xer_so \wrpick_XER_xer_so connect \en_o \wrpick_XER_xer_so_en_o connect \i \wrpick_XER_xer_so_i @@ -129539,11 +249553,11 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" wire width 1 \en_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $194 + wire width 1 $237 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $195 + wire width 10 $238 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $196 + cell $and $239 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -129551,32 +249565,32 @@ module \core parameter \Y_WIDTH 10 connect \A \fn_unit connect \B 2'10 - connect \Y $195 + connect \Y $238 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $197 + cell $reduce_bool $240 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 - connect \A $195 - connect \Y $194 + connect \A $238 + connect \Y $237 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $198 + wire width 1 $241 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $199 + cell $and $242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $194 - connect \Y $198 + connect \B $237 + connect \Y $241 end process $group_0 assign \en_alu0 1'0 - assign \en_alu0 $198 + assign \en_alu0 $241 sync init end process $group_1 @@ -129800,6 +249814,8 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" wire width 1 \en_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 \en_div0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" wire width 1 \en_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" wire width 1 \en_shiftrot0 @@ -129832,31 +249848,37 @@ module \core assign \corebusy_o \busy_o$18 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 assign \corebusy_o \busy_o$30 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \corebusy_o \busy_o$42 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \corebusy_o \busy_o$39 + assign \corebusy_o \busy_o$51 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_ldst0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \corebusy_o \busy_o$47 + assign \corebusy_o \busy_o$59 end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 4 $200 + wire width 4 $243 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71" - wire width 1 $201 + wire width 1 $244 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71" - cell $and $202 + cell $and $245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -129864,12 +249886,12 @@ module \core parameter \Y_WIDTH 1 connect \A \oe connect \B \oe_ok - connect \Y $201 + connect \Y $244 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" - wire width 1 $203 + wire width 1 $246 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" - cell $eq $204 + cell $eq $247 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -129877,15 +249899,15 @@ module \core parameter \Y_WIDTH 1 connect \A \input_carry connect \B 2'10 - connect \Y $203 + connect \Y $246 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $205 + cell $not $248 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A { $203 $201 \reg2_ok \reg1_ok } - connect \Y $200 + connect \A { $246 $244 \reg2_ok \reg1_ok } + connect \Y $243 end process $group_27 assign \fus_rdmaskn 4'0000 @@ -129893,29 +249915,30 @@ module \core switch { \en_alu0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \fus_rdmaskn $200 + assign \fus_rdmaskn $243 end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104" - wire width 7 \fu_enable + wire width 8 \fu_enable process $group_28 - assign \fu_enable 7'0000000 + assign \fu_enable 8'00000000 assign \fu_enable [0] \en_alu0 assign \fu_enable [1] \en_cr0 assign \fu_enable [2] \en_branch0 assign \fu_enable [3] \en_trap0 - assign \fu_enable [4] \en_logical0 - assign \fu_enable [5] \en_shiftrot0 - assign \fu_enable [6] \en_ldst0 + assign \fu_enable [4] \en_div0 + assign \fu_enable [5] \en_logical0 + assign \fu_enable [6] \en_shiftrot0 + assign \fu_enable [7] \en_ldst0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $206 + wire width 1 $249 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $207 + wire width 10 $250 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $208 + cell $and $251 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -129923,32 +249946,32 @@ module \core parameter \Y_WIDTH 10 connect \A \fn_unit connect \B 7'1000000 - connect \Y $207 + connect \Y $250 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $209 + cell $reduce_bool $252 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 - connect \A $207 - connect \Y $206 + connect \A $250 + connect \Y $249 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $210 + wire width 1 $253 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $211 + cell $and $254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $206 - connect \Y $210 + connect \B $249 + connect \Y $253 end process $group_29 assign \en_cr0 1'0 - assign \en_cr0 $210 + assign \en_cr0 $253 sync init end process $group_30 @@ -130012,31 +250035,31 @@ module \core sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 6 $212 + wire width 6 $255 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $213 + cell $not $256 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { \cr_in2_ok$5 \cr_in2_ok \cr_in1_ok \read_cr_whole \reg2_ok \reg1_ok } - connect \Y $212 + connect \Y $255 end process $group_36 - assign \fus_rdmaskn$119 6'000000 + assign \fus_rdmaskn$140 6'000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_cr0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \fus_rdmaskn$119 $212 + assign \fus_rdmaskn$140 $255 end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $214 + wire width 1 $257 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $215 + wire width 10 $258 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $216 + cell $and $259 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -130044,32 +250067,32 @@ module \core parameter \Y_WIDTH 10 connect \A \fn_unit connect \B 6'100000 - connect \Y $215 + connect \Y $258 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $217 + cell $reduce_bool $260 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 - connect \A $215 - connect \Y $214 + connect \A $258 + connect \Y $257 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $218 + wire width 1 $261 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $219 + cell $and $262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $214 - connect \Y $218 + connect \B $257 + connect \Y $261 end process $group_37 assign \en_branch0 1'0 - assign \en_branch0 $218 + assign \en_branch0 $261 sync init end process $group_38 @@ -130093,13 +250116,13 @@ module \core sync init end process $group_40 - assign \fus_oper_i__imm_data__imm$120 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i__imm_data__imm_ok$121 1'0 + assign \fus_oper_i__imm_data__imm$141 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i__imm_data__imm_ok$142 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_branch0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign { \fus_oper_i__imm_data__imm_ok$121 \fus_oper_i__imm_data__imm$120 } { \imm_ok \imm } + assign { \fus_oper_i__imm_data__imm_ok$142 \fus_oper_i__imm_data__imm$141 } { \imm_ok \imm } end sync init end @@ -130144,31 +250167,31 @@ module \core sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 4 $220 + wire width 4 $263 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $221 + cell $not $264 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 1'1 \cr_in1_ok \fast2_ok \fast1_ok } - connect \Y $220 + connect \Y $263 end process $group_46 - assign \fus_rdmaskn$122 4'0000 + assign \fus_rdmaskn$143 4'0000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_branch0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \fus_rdmaskn$122 $220 + assign \fus_rdmaskn$143 $263 end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $222 + wire width 1 $265 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $223 + wire width 10 $266 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $224 + cell $and $267 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -130176,32 +250199,32 @@ module \core parameter \Y_WIDTH 10 connect \A \fn_unit connect \B 8'10000000 - connect \Y $223 + connect \Y $266 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $225 + cell $reduce_bool $268 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 - connect \A $223 - connect \Y $222 + connect \A $266 + connect \Y $265 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $226 + wire width 1 $269 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $227 + cell $and $270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $222 - connect \Y $226 + connect \B $265 + connect \Y $269 end process $group_47 assign \en_trap0 1'0 - assign \en_trap0 $226 + assign \en_trap0 $269 sync init end process $group_48 @@ -130275,70 +250298,70 @@ module \core sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 6 $228 + wire width 6 $271 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $229 + cell $not $272 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 1'1 1'1 \fast2_ok \fast1_ok \reg2_ok \reg1_ok } - connect \Y $228 + connect \Y $271 end process $group_55 - assign \fus_rdmaskn$123 6'000000 + assign \fus_rdmaskn$144 6'000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_trap0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \fus_rdmaskn$123 $228 + assign \fus_rdmaskn$144 $271 end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $230 + wire width 1 $273 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $231 + wire width 10 $274 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $232 + cell $and $275 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 + parameter \B_WIDTH 10 parameter \Y_WIDTH 10 connect \A \fn_unit - connect \B 5'10000 - connect \Y $231 + connect \B 10'1000000000 + connect \Y $274 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $233 + cell $reduce_bool $276 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 - connect \A $231 - connect \Y $230 + connect \A $274 + connect \Y $273 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $234 + wire width 1 $277 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $235 + cell $and $278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $230 - connect \Y $234 + connect \B $273 + connect \Y $277 end process $group_56 - assign \en_logical0 1'0 - assign \en_logical0 $234 + assign \en_div0 1'0 + assign \en_div0 $277 sync init end process $group_57 assign \oper_i__insn_type$19 7'0000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 assign \oper_i__insn_type$19 \insn_type @@ -130348,7 +250371,7 @@ module \core process $group_58 assign \oper_i__fn_unit$20 10'0000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 assign \oper_i__fn_unit$20 \fn_unit @@ -130356,20 +250379,20 @@ module \core sync init end process $group_59 - assign \fus_oper_i__imm_data__imm$124 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i__imm_data__imm_ok$125 1'0 + assign \fus_oper_i__imm_data__imm$145 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i__imm_data__imm_ok$146 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign { \fus_oper_i__imm_data__imm_ok$125 \fus_oper_i__imm_data__imm$124 } { \imm_ok \imm } + assign { \fus_oper_i__imm_data__imm_ok$146 \fus_oper_i__imm_data__imm$145 } { \imm_ok \imm } end sync init end process $group_61 assign \oper_i__lk$21 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 assign \oper_i__lk$21 \lk @@ -130377,31 +250400,31 @@ module \core sync init end process $group_62 - assign \fus_oper_i__rc__rc$126 1'0 - assign \fus_oper_i__rc__rc_ok$127 1'0 + assign \fus_oper_i__rc__rc$147 1'0 + assign \fus_oper_i__rc__rc_ok$148 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign { \fus_oper_i__rc__rc_ok$127 \fus_oper_i__rc__rc$126 } { \rc_ok \rc } + assign { \fus_oper_i__rc__rc_ok$148 \fus_oper_i__rc__rc$147 } { \rc_ok \rc } end sync init end process $group_64 - assign \fus_oper_i__oe__oe$128 1'0 - assign \fus_oper_i__oe__oe_ok$129 1'0 + assign \fus_oper_i__oe__oe$149 1'0 + assign \fus_oper_i__oe__oe_ok$150 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign { \fus_oper_i__oe__oe_ok$129 \fus_oper_i__oe__oe$128 } { \oe_ok \oe } + assign { \fus_oper_i__oe__oe_ok$150 \fus_oper_i__oe__oe$149 } { \oe_ok \oe } end sync init end process $group_66 assign \oper_i__invert_a$22 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 assign \oper_i__invert_a$22 \invert_a @@ -130409,19 +250432,19 @@ module \core sync init end process $group_67 - assign \fus_oper_i__zero_a$130 1'0 + assign \fus_oper_i__zero_a$151 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \fus_oper_i__zero_a$130 \zero_a + assign \fus_oper_i__zero_a$151 \zero_a end sync init end process $group_68 assign \oper_i__input_carry$23 2'00 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 assign \oper_i__input_carry$23 \input_carry @@ -130431,7 +250454,7 @@ module \core process $group_69 assign \oper_i__invert_out$24 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 assign \oper_i__invert_out$24 \invert_out @@ -130439,20 +250462,20 @@ module \core sync init end process $group_70 - assign \fus_oper_i__write_cr__data$131 3'000 - assign \fus_oper_i__write_cr__ok$132 1'0 + assign \fus_oper_i__write_cr__data$152 3'000 + assign \fus_oper_i__write_cr__ok$153 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign { \fus_oper_i__write_cr__ok$132 \fus_oper_i__write_cr__data$131 } { \cr_out_ok \cr_out } + assign { \fus_oper_i__write_cr__ok$153 \fus_oper_i__write_cr__data$152 } { \cr_out_ok \cr_out } end sync init end process $group_72 assign \oper_i__output_carry$25 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 assign \oper_i__output_carry$25 \output_carry @@ -130462,7 +250485,7 @@ module \core process $group_73 assign \oper_i__is_32bit$26 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 assign \oper_i__is_32bit$26 \is_32bit @@ -130472,7 +250495,7 @@ module \core process $group_74 assign \oper_i__is_signed$27 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 assign \oper_i__is_signed$27 \is_signed @@ -130482,7 +250505,7 @@ module \core process $group_75 assign \oper_i__data_len$28 4'0000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 assign \oper_i__data_len$28 \data_len @@ -130490,19 +250513,19 @@ module \core sync init end process $group_76 - assign \fus_oper_i__insn$133 32'00000000000000000000000000000000 + assign \fus_oper_i__insn$154 32'00000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \fus_oper_i__insn$133 \insn + assign \fus_oper_i__insn$154 \insn end sync init end process $group_77 assign \issue_i$29 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_logical0 } + switch { \en_div0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 assign \issue_i$29 \issue_i @@ -130510,31 +250533,279 @@ module \core sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 2 $236 + wire width 3 $279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71" + wire width 1 $280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71" + cell $and $281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oe + connect \B \oe_ok + connect \Y $280 + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $237 + cell $not $282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { $280 \reg2_ok \reg1_ok } + connect \Y $279 + end + process $group_78 + assign \fus_rdmaskn$155 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_div0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \fus_rdmaskn$155 $279 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + wire width 1 $283 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + wire width 10 $284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + cell $and $285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 10 + connect \A \fn_unit + connect \B 5'10000 + connect \Y $284 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + cell $reduce_bool $286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A $284 + connect \Y $283 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + wire width 1 $287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + cell $and $288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \valid + connect \B $283 + connect \Y $287 + end + process $group_79 + assign \en_logical0 1'0 + assign \en_logical0 $287 + sync init + end + process $group_80 + assign \oper_i__insn_type$31 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \oper_i__insn_type$31 \insn_type + end + sync init + end + process $group_81 + assign \oper_i__fn_unit$32 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \oper_i__fn_unit$32 \fn_unit + end + sync init + end + process $group_82 + assign \fus_oper_i__imm_data__imm$156 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i__imm_data__imm_ok$157 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign { \fus_oper_i__imm_data__imm_ok$157 \fus_oper_i__imm_data__imm$156 } { \imm_ok \imm } + end + sync init + end + process $group_84 + assign \oper_i__lk$33 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \oper_i__lk$33 \lk + end + sync init + end + process $group_85 + assign \fus_oper_i__rc__rc$158 1'0 + assign \fus_oper_i__rc__rc_ok$159 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign { \fus_oper_i__rc__rc_ok$159 \fus_oper_i__rc__rc$158 } { \rc_ok \rc } + end + sync init + end + process $group_87 + assign \fus_oper_i__oe__oe$160 1'0 + assign \fus_oper_i__oe__oe_ok$161 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign { \fus_oper_i__oe__oe_ok$161 \fus_oper_i__oe__oe$160 } { \oe_ok \oe } + end + sync init + end + process $group_89 + assign \oper_i__invert_a$34 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \oper_i__invert_a$34 \invert_a + end + sync init + end + process $group_90 + assign \fus_oper_i__zero_a$162 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \fus_oper_i__zero_a$162 \zero_a + end + sync init + end + process $group_91 + assign \oper_i__input_carry$35 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \oper_i__input_carry$35 \input_carry + end + sync init + end + process $group_92 + assign \oper_i__invert_out$36 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \oper_i__invert_out$36 \invert_out + end + sync init + end + process $group_93 + assign \fus_oper_i__write_cr__data$163 3'000 + assign \fus_oper_i__write_cr__ok$164 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign { \fus_oper_i__write_cr__ok$164 \fus_oper_i__write_cr__data$163 } { \cr_out_ok \cr_out } + end + sync init + end + process $group_95 + assign \oper_i__output_carry$37 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \oper_i__output_carry$37 \output_carry + end + sync init + end + process $group_96 + assign \oper_i__is_32bit$38 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \oper_i__is_32bit$38 \is_32bit + end + sync init + end + process $group_97 + assign \oper_i__is_signed$39 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \oper_i__is_signed$39 \is_signed + end + sync init + end + process $group_98 + assign \oper_i__data_len$40 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \oper_i__data_len$40 \data_len + end + sync init + end + process $group_99 + assign \fus_oper_i__insn$165 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \fus_oper_i__insn$165 \insn + end + sync init + end + process $group_100 + assign \issue_i$41 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + switch { \en_logical0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + case 1'1 + assign \issue_i$41 \issue_i + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" + wire width 2 $289 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" + cell $not $290 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A { \reg2_ok \reg1_ok } - connect \Y $236 + connect \Y $289 end - process $group_78 - assign \fus_rdmaskn$134 2'00 + process $group_101 + assign \fus_rdmaskn$166 2'00 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_logical0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \fus_rdmaskn$134 $236 + assign \fus_rdmaskn$166 $289 end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $238 + wire width 1 $291 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $239 + wire width 10 $292 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $240 + cell $and $293 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -130542,184 +250813,184 @@ module \core parameter \Y_WIDTH 10 connect \A \fn_unit connect \B 4'1000 - connect \Y $239 + connect \Y $292 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $241 + cell $reduce_bool $294 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 - connect \A $239 - connect \Y $238 + connect \A $292 + connect \Y $291 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $242 + wire width 1 $295 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $243 + cell $and $296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $238 - connect \Y $242 + connect \B $291 + connect \Y $295 end - process $group_79 + process $group_102 assign \en_shiftrot0 1'0 - assign \en_shiftrot0 $242 + assign \en_shiftrot0 $295 sync init end - process $group_80 - assign \oper_i__insn_type$31 7'0000000 + process $group_103 + assign \oper_i__insn_type$43 7'0000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \oper_i__insn_type$31 \insn_type + assign \oper_i__insn_type$43 \insn_type end sync init end - process $group_81 - assign \fus_oper_i__fn_unit$135 10'0000000000 + process $group_104 + assign \fus_oper_i__fn_unit$167 10'0000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \fus_oper_i__fn_unit$135 \fn_unit + assign \fus_oper_i__fn_unit$167 \fn_unit end sync init end - process $group_82 - assign \fus_oper_i__imm_data__imm$136 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i__imm_data__imm_ok$137 1'0 + process $group_105 + assign \fus_oper_i__imm_data__imm$168 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i__imm_data__imm_ok$169 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign { \fus_oper_i__imm_data__imm_ok$137 \fus_oper_i__imm_data__imm$136 } { \imm_ok \imm } + assign { \fus_oper_i__imm_data__imm_ok$169 \fus_oper_i__imm_data__imm$168 } { \imm_ok \imm } end sync init end - process $group_84 - assign \fus_oper_i__rc__rc$138 1'0 - assign \fus_oper_i__rc__rc_ok$139 1'0 + process $group_107 + assign \fus_oper_i__rc__rc$170 1'0 + assign \fus_oper_i__rc__rc_ok$171 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign { \fus_oper_i__rc__rc_ok$139 \fus_oper_i__rc__rc$138 } { \rc_ok \rc } + assign { \fus_oper_i__rc__rc_ok$171 \fus_oper_i__rc__rc$170 } { \rc_ok \rc } end sync init end - process $group_86 - assign \fus_oper_i__oe__oe$140 1'0 - assign \fus_oper_i__oe__oe_ok$141 1'0 + process $group_109 + assign \fus_oper_i__oe__oe$172 1'0 + assign \fus_oper_i__oe__oe_ok$173 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign { \fus_oper_i__oe__oe_ok$141 \fus_oper_i__oe__oe$140 } { \oe_ok \oe } + assign { \fus_oper_i__oe__oe_ok$173 \fus_oper_i__oe__oe$172 } { \oe_ok \oe } end sync init end - process $group_88 - assign \fus_oper_i__write_cr__data$142 3'000 - assign \fus_oper_i__write_cr__ok$143 1'0 + process $group_111 + assign \fus_oper_i__write_cr__data$174 3'000 + assign \fus_oper_i__write_cr__ok$175 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign { \fus_oper_i__write_cr__ok$143 \fus_oper_i__write_cr__data$142 } { \cr_out_ok \cr_out } + assign { \fus_oper_i__write_cr__ok$175 \fus_oper_i__write_cr__data$174 } { \cr_out_ok \cr_out } end sync init end - process $group_90 - assign \oper_i__input_carry$32 2'00 + process $group_113 + assign \oper_i__input_carry$44 2'00 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \oper_i__input_carry$32 \input_carry + assign \oper_i__input_carry$44 \input_carry end sync init end - process $group_91 - assign \oper_i__output_carry$33 1'0 + process $group_114 + assign \oper_i__output_carry$45 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \oper_i__output_carry$33 \output_carry + assign \oper_i__output_carry$45 \output_carry end sync init end - process $group_92 - assign \oper_i__input_cr$34 1'0 + process $group_115 + assign \oper_i__input_cr$46 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \oper_i__input_cr$34 \input_cr + assign \oper_i__input_cr$46 \input_cr end sync init end - process $group_93 - assign \oper_i__output_cr$35 1'0 + process $group_116 + assign \oper_i__output_cr$47 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \oper_i__output_cr$35 \output_cr + assign \oper_i__output_cr$47 \output_cr end sync init end - process $group_94 - assign \oper_i__is_32bit$36 1'0 + process $group_117 + assign \oper_i__is_32bit$48 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \oper_i__is_32bit$36 \is_32bit + assign \oper_i__is_32bit$48 \is_32bit end sync init end - process $group_95 - assign \oper_i__is_signed$37 1'0 + process $group_118 + assign \oper_i__is_signed$49 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \oper_i__is_signed$37 \is_signed + assign \oper_i__is_signed$49 \is_signed end sync init end - process $group_96 - assign \fus_oper_i__insn$144 32'00000000000000000000000000000000 + process $group_119 + assign \fus_oper_i__insn$176 32'00000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \fus_oper_i__insn$144 \insn + assign \fus_oper_i__insn$176 \insn end sync init end - process $group_97 - assign \issue_i$38 1'0 + process $group_120 + assign \issue_i$50 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \issue_i$38 \issue_i + assign \issue_i$50 \issue_i end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 4 $244 + wire width 4 $297 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" - wire width 1 $245 + wire width 1 $298 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" - cell $eq $246 + cell $eq $299 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -130727,32 +250998,32 @@ module \core parameter \Y_WIDTH 1 connect \A \input_carry connect \B 2'10 - connect \Y $245 + connect \Y $298 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $247 + cell $not $300 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A { $245 \reg3_ok \reg2_ok \reg1_ok } - connect \Y $244 + connect \A { $298 \reg3_ok \reg2_ok \reg1_ok } + connect \Y $297 end - process $group_98 - assign \fus_rdmaskn$145 4'0000 + process $group_121 + assign \fus_rdmaskn$177 4'0000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_shiftrot0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \fus_rdmaskn$145 $244 + assign \fus_rdmaskn$177 $297 end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $248 + wire width 1 $301 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $249 + wire width 10 $302 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $250 + cell $and $303 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -130760,56 +251031,56 @@ module \core parameter \Y_WIDTH 10 connect \A \fn_unit connect \B 3'100 - connect \Y $249 + connect \Y $302 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $251 + cell $reduce_bool $304 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 - connect \A $249 - connect \Y $248 + connect \A $302 + connect \Y $301 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $252 + wire width 1 $305 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $253 + cell $and $306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $248 - connect \Y $252 + connect \B $301 + connect \Y $305 end - process $group_99 + process $group_122 assign \en_ldst0 1'0 - assign \en_ldst0 $252 + assign \en_ldst0 $305 sync init end - process $group_100 - assign \oper_i__insn_type$40 7'0000000 + process $group_123 + assign \oper_i__insn_type$52 7'0000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_ldst0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \oper_i__insn_type$40 \insn_type + assign \oper_i__insn_type$52 \insn_type end sync init end - process $group_101 - assign \fus_oper_i__imm_data__imm$146 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i__imm_data__imm_ok$147 1'0 + process $group_124 + assign \fus_oper_i__imm_data__imm$178 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i__imm_data__imm_ok$179 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_ldst0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign { \fus_oper_i__imm_data__imm_ok$147 \fus_oper_i__imm_data__imm$146 } { \imm_ok \imm } + assign { \fus_oper_i__imm_data__imm_ok$179 \fus_oper_i__imm_data__imm$178 } { \imm_ok \imm } end sync init end - process $group_103 + process $group_126 assign \oper_i__zero_a 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_ldst0 } @@ -130819,57 +251090,57 @@ module \core end sync init end - process $group_104 - assign \oper_i__is_32bit$41 1'0 + process $group_127 + assign \oper_i__is_32bit$53 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_ldst0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \oper_i__is_32bit$41 \is_32bit + assign \oper_i__is_32bit$53 \is_32bit end sync init end - process $group_105 - assign \oper_i__is_signed$42 1'0 + process $group_128 + assign \oper_i__is_signed$54 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_ldst0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \oper_i__is_signed$42 \is_signed + assign \oper_i__is_signed$54 \is_signed end sync init end - process $group_106 - assign \oper_i__data_len$43 4'0000 + process $group_129 + assign \oper_i__data_len$55 4'0000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_ldst0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \oper_i__data_len$43 \data_len + assign \oper_i__data_len$55 \data_len end sync init end - process $group_107 - assign \oper_i__byte_reverse$44 1'0 + process $group_130 + assign \oper_i__byte_reverse$56 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_ldst0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \oper_i__byte_reverse$44 \byte_reverse + assign \oper_i__byte_reverse$56 \byte_reverse end sync init end - process $group_108 - assign \oper_i__sign_extend$45 1'0 + process $group_131 + assign \oper_i__sign_extend$57 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_ldst0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \oper_i__sign_extend$45 \sign_extend + assign \oper_i__sign_extend$57 \sign_extend end sync init end - process $group_109 + process $group_132 assign \oper_i__update 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_ldst0 } @@ -130879,47 +251150,47 @@ module \core end sync init end - process $group_110 - assign \issue_i$46 1'0 + process $group_133 + assign \issue_i$58 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_ldst0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \issue_i$46 \issue_i + assign \issue_i$58 \issue_i end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 3 $254 + wire width 3 $307 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $255 + cell $not $308 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { \reg3_ok \reg2_ok \reg1_ok } - connect \Y $254 + connect \Y $307 end - process $group_111 - assign \fus_rdmaskn$148 3'000 + process $group_134 + assign \fus_rdmaskn$180 3'000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" switch { \en_ldst0 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" case 1'1 - assign \fus_rdmaskn$148 $254 + assign \fus_rdmaskn$180 $307 end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" wire width 1 \rdflag_INT_ra - process $group_112 + process $group_135 assign \rdflag_INT_ra 1'0 assign \rdflag_INT_ra \reg1_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:47" - wire width 32 $256 + wire width 32 $309 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:47" - cell $sshl $257 + cell $sshl $310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -130927,22 +251198,22 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \reg1 - connect \Y $256 + connect \Y $309 end - process $group_113 + process $group_136 assign \int_src1__ren 32'00000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" switch { \rdpick_INT_ra_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" case 1'1 - assign \int_src1__ren $256 + assign \int_src1__ren $309 end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $258 + wire width 1 $311 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $259 + cell $and $312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -130950,251 +251221,290 @@ module \core parameter \Y_WIDTH 1 connect \A \rd__rel [0] connect \B \fu_enable [0] - connect \Y $258 + connect \Y $311 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $260 + wire width 1 $313 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $261 + cell $and $314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $258 + connect \A $311 connect \B \rdflag_INT_ra - connect \Y $260 + connect \Y $313 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $262 + wire width 1 $315 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $263 + cell $and $316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$48 [0] + connect \A \rd__rel$60 [0] connect \B \fu_enable [1] - connect \Y $262 + connect \Y $315 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $264 + wire width 1 $317 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $265 + cell $and $318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $262 + connect \A $315 connect \B \rdflag_INT_ra - connect \Y $264 + connect \Y $317 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $266 + wire width 1 $319 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $267 + cell $and $320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$51 [0] + connect \A \rd__rel$63 [0] connect \B \fu_enable [3] - connect \Y $266 + connect \Y $319 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $268 + wire width 1 $321 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $269 + cell $and $322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $266 + connect \A $319 connect \B \rdflag_INT_ra - connect \Y $268 + connect \Y $321 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $270 + wire width 1 $323 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $271 + cell $and $324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$54 [0] + connect \A \rd__rel$66 [0] connect \B \fu_enable [4] - connect \Y $270 + connect \Y $323 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $272 + wire width 1 $325 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $273 + cell $and $326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $270 + connect \A $323 connect \B \rdflag_INT_ra - connect \Y $272 + connect \Y $325 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $274 + wire width 1 $327 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $275 + cell $and $328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$57 [0] + connect \A \rd__rel$69 [0] connect \B \fu_enable [5] - connect \Y $274 + connect \Y $327 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $276 + wire width 1 $329 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $277 + cell $and $330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $274 + connect \A $327 connect \B \rdflag_INT_ra - connect \Y $276 + connect \Y $329 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $278 + wire width 1 $331 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $279 + cell $and $332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$60 [0] + connect \A \rd__rel$72 [0] connect \B \fu_enable [6] - connect \Y $278 + connect \Y $331 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $280 + wire width 1 $333 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $281 + cell $and $334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $278 + connect \A $331 connect \B \rdflag_INT_ra - connect \Y $280 + connect \Y $333 end - process $group_114 - assign \rdpick_INT_ra_i 6'000000 - assign \rdpick_INT_ra_i [0] $260 - assign \rdpick_INT_ra_i [1] $264 - assign \rdpick_INT_ra_i [2] $268 - assign \rdpick_INT_ra_i [3] $272 - assign \rdpick_INT_ra_i [4] $276 - assign \rdpick_INT_ra_i [5] $280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" + wire width 1 $335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" + cell $and $336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rd__rel$75 [0] + connect \B \fu_enable [7] + connect \Y $335 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" + wire width 1 $337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" + cell $and $338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $335 + connect \B \rdflag_INT_ra + connect \Y $337 + end + process $group_137 + assign \rdpick_INT_ra_i 7'0000000 + assign \rdpick_INT_ra_i [0] $313 + assign \rdpick_INT_ra_i [1] $317 + assign \rdpick_INT_ra_i [2] $321 + assign \rdpick_INT_ra_i [3] $325 + assign \rdpick_INT_ra_i [4] $329 + assign \rdpick_INT_ra_i [5] $333 + assign \rdpick_INT_ra_i [6] $337 sync init end - process $group_115 + process $group_138 assign \rd__go 4'0000 assign \rd__go [0] \rdpick_INT_ra_o [0] assign \rd__go [1] \rdpick_INT_rb_o [0] - assign \rd__go [2] \rdpick_XER_xer_so_o + assign \rd__go [2] \rdpick_XER_xer_so_o [0] assign \rd__go [3] \rdpick_XER_xer_ca_o [0] sync init end - process $group_116 + process $group_139 assign \src1_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \src1_i \int_src1__data_o sync init end - process $group_117 - assign \rd__go$49 6'000000 - assign \rd__go$49 [0] \rdpick_INT_ra_o [1] - assign \rd__go$49 [1] \rdpick_INT_rb_o [1] - assign \rd__go$49 [2] \rdpick_CR_full_cr_o - assign \rd__go$49 [3] \rdpick_CR_cr_a_o [0] - assign \rd__go$49 [4] \rdpick_CR_cr_b_o - assign \rd__go$49 [5] \rdpick_CR_cr_c_o + process $group_140 + assign \rd__go$61 6'000000 + assign \rd__go$61 [0] \rdpick_INT_ra_o [1] + assign \rd__go$61 [1] \rdpick_INT_rb_o [1] + assign \rd__go$61 [2] \rdpick_CR_full_cr_o + assign \rd__go$61 [3] \rdpick_CR_cr_a_o [0] + assign \rd__go$61 [4] \rdpick_CR_cr_b_o + assign \rd__go$61 [5] \rdpick_CR_cr_c_o sync init end - process $group_118 - assign \src1_i$50 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_i$50 \int_src1__data_o + process $group_141 + assign \src1_i$62 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$62 \int_src1__data_o sync init end - process $group_119 - assign \rd__go$52 6'000000 - assign \rd__go$52 [0] \rdpick_INT_ra_o [2] - assign \rd__go$52 [1] \rdpick_INT_rb_o [2] - assign \rd__go$52 [2] \rdpick_FAST_spr1_o [1] - assign \rd__go$52 [3] \rdpick_FAST_spr2_o [1] - assign \rd__go$52 [4] \rdpick_FAST_cia_o [1] - assign \rd__go$52 [5] \rdpick_FAST_msr_o + process $group_142 + assign \rd__go$64 6'000000 + assign \rd__go$64 [0] \rdpick_INT_ra_o [2] + assign \rd__go$64 [1] \rdpick_INT_rb_o [2] + assign \rd__go$64 [2] \rdpick_FAST_spr1_o [1] + assign \rd__go$64 [3] \rdpick_FAST_spr2_o [1] + assign \rd__go$64 [4] \rdpick_FAST_cia_o [1] + assign \rd__go$64 [5] \rdpick_FAST_msr_o sync init end - process $group_120 - assign \src1_i$53 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_i$53 \int_src1__data_o + process $group_143 + assign \src1_i$65 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$65 \int_src1__data_o sync init end - process $group_121 - assign \rd__go$55 2'00 - assign \rd__go$55 [0] \rdpick_INT_ra_o [3] - assign \rd__go$55 [1] \rdpick_INT_rb_o [3] + process $group_144 + assign \rd__go$67 3'000 + assign \rd__go$67 [0] \rdpick_INT_ra_o [3] + assign \rd__go$67 [1] \rdpick_INT_rb_o [3] + assign \rd__go$67 [2] \rdpick_XER_xer_so_o [1] sync init end - process $group_122 - assign \src1_i$56 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_i$56 \int_src1__data_o + process $group_145 + assign \src1_i$68 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$68 \int_src1__data_o sync init end - process $group_123 - assign \rd__go$58 4'0000 - assign \rd__go$58 [0] \rdpick_INT_ra_o [4] - assign \rd__go$58 [1] \rdpick_INT_rb_o [4] - assign \rd__go$58 [2] \rdpick_INT_rc_o [0] - assign \rd__go$58 [3] \rdpick_XER_xer_ca_o [1] + process $group_146 + assign \rd__go$70 2'00 + assign \rd__go$70 [0] \rdpick_INT_ra_o [4] + assign \rd__go$70 [1] \rdpick_INT_rb_o [4] sync init end - process $group_124 - assign \src1_i$59 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_i$59 \int_src1__data_o + process $group_147 + assign \src1_i$71 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$71 \int_src1__data_o sync init end - process $group_125 - assign \rd__go$61 3'000 - assign \rd__go$61 [0] \rdpick_INT_ra_o [5] - assign \rd__go$61 [1] \rdpick_INT_rb_o [5] - assign \rd__go$61 [2] \rdpick_INT_rc_o [1] + process $group_148 + assign \rd__go$73 4'0000 + assign \rd__go$73 [0] \rdpick_INT_ra_o [5] + assign \rd__go$73 [1] \rdpick_INT_rb_o [5] + assign \rd__go$73 [2] \rdpick_INT_rc_o [0] + assign \rd__go$73 [3] \rdpick_XER_xer_ca_o [1] sync init end - process $group_126 - assign \src1_i$62 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_i$62 \int_src1__data_o + process $group_149 + assign \src1_i$74 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$74 \int_src1__data_o + sync init + end + process $group_150 + assign \rd__go$76 3'000 + assign \rd__go$76 [0] \rdpick_INT_ra_o [6] + assign \rd__go$76 [1] \rdpick_INT_rb_o [6] + assign \rd__go$76 [2] \rdpick_INT_rc_o [1] + sync init + end + process $group_151 + assign \src1_i$77 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$77 \int_src1__data_o sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" wire width 1 \rdflag_INT_rb - process $group_127 + process $group_152 assign \rdflag_INT_rb 1'0 assign \rdflag_INT_rb \reg2_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:49" - wire width 32 $282 + wire width 32 $339 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:49" - cell $sshl $283 + cell $sshl $340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -131202,22 +251512,22 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \reg2 - connect \Y $282 + connect \Y $339 end - process $group_128 + process $group_153 assign \int_src2__ren 32'00000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" switch { \rdpick_INT_rb_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" case 1'1 - assign \int_src2__ren $282 + assign \int_src2__ren $339 end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $284 + wire width 1 $341 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $285 + cell $and $342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -131225,202 +251535,234 @@ module \core parameter \Y_WIDTH 1 connect \A \rd__rel [1] connect \B \fu_enable [0] - connect \Y $284 + connect \Y $341 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $286 + wire width 1 $343 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $287 + cell $and $344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $284 + connect \A $341 connect \B \rdflag_INT_rb - connect \Y $286 + connect \Y $343 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $288 + wire width 1 $345 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $289 + cell $and $346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$48 [1] + connect \A \rd__rel$60 [1] connect \B \fu_enable [1] - connect \Y $288 + connect \Y $345 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $290 + wire width 1 $347 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $291 + cell $and $348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $288 + connect \A $345 connect \B \rdflag_INT_rb - connect \Y $290 + connect \Y $347 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $292 + wire width 1 $349 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $293 + cell $and $350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$51 [1] + connect \A \rd__rel$63 [1] connect \B \fu_enable [3] - connect \Y $292 + connect \Y $349 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $294 + wire width 1 $351 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $295 + cell $and $352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $292 + connect \A $349 connect \B \rdflag_INT_rb - connect \Y $294 + connect \Y $351 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $296 + wire width 1 $353 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $297 + cell $and $354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$54 [1] + connect \A \rd__rel$66 [1] connect \B \fu_enable [4] - connect \Y $296 + connect \Y $353 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $298 + wire width 1 $355 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $299 + cell $and $356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $296 + connect \A $353 connect \B \rdflag_INT_rb - connect \Y $298 + connect \Y $355 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $300 + wire width 1 $357 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $301 + cell $and $358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$57 [1] + connect \A \rd__rel$69 [1] connect \B \fu_enable [5] - connect \Y $300 + connect \Y $357 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $302 + wire width 1 $359 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $303 + cell $and $360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $300 + connect \A $357 connect \B \rdflag_INT_rb - connect \Y $302 + connect \Y $359 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $304 + wire width 1 $361 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $305 + cell $and $362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$60 [1] + connect \A \rd__rel$72 [1] connect \B \fu_enable [6] - connect \Y $304 + connect \Y $361 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $306 + wire width 1 $363 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $307 + cell $and $364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $304 + connect \A $361 connect \B \rdflag_INT_rb - connect \Y $306 + connect \Y $363 end - process $group_129 - assign \rdpick_INT_rb_i 6'000000 - assign \rdpick_INT_rb_i [0] $286 - assign \rdpick_INT_rb_i [1] $290 - assign \rdpick_INT_rb_i [2] $294 - assign \rdpick_INT_rb_i [3] $298 - assign \rdpick_INT_rb_i [4] $302 - assign \rdpick_INT_rb_i [5] $306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" + wire width 1 $365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" + cell $and $366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rd__rel$75 [1] + connect \B \fu_enable [7] + connect \Y $365 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" + wire width 1 $367 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" + cell $and $368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $365 + connect \B \rdflag_INT_rb + connect \Y $367 + end + process $group_154 + assign \rdpick_INT_rb_i 7'0000000 + assign \rdpick_INT_rb_i [0] $343 + assign \rdpick_INT_rb_i [1] $347 + assign \rdpick_INT_rb_i [2] $351 + assign \rdpick_INT_rb_i [3] $355 + assign \rdpick_INT_rb_i [4] $359 + assign \rdpick_INT_rb_i [5] $363 + assign \rdpick_INT_rb_i [6] $367 sync init end - process $group_130 + process $group_155 assign \src2_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \src2_i \int_src2__data_o sync init end - process $group_131 - assign \src2_i$63 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_i$63 \int_src2__data_o + process $group_156 + assign \src2_i$78 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$78 \int_src2__data_o sync init end - process $group_132 - assign \src2_i$64 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_i$64 \int_src2__data_o + process $group_157 + assign \src2_i$79 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$79 \int_src2__data_o sync init end - process $group_133 - assign \src2_i$65 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_i$65 \int_src2__data_o + process $group_158 + assign \src2_i$80 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$80 \int_src2__data_o sync init end - process $group_134 - assign \src2_i$66 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_i$66 \int_src2__data_o + process $group_159 + assign \src2_i$81 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$81 \int_src2__data_o sync init end - process $group_135 - assign \src2_i$67 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_i$67 \int_src2__data_o + process $group_160 + assign \src2_i$82 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$82 \int_src2__data_o + sync init + end + process $group_161 + assign \src2_i$83 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$83 \int_src2__data_o sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" wire width 1 \rdflag_INT_rc - process $group_136 + process $group_162 assign \rdflag_INT_rc 1'0 assign \rdflag_INT_rc \reg3_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - wire width 32 $308 + wire width 32 $369 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - cell $sshl $309 + cell $sshl $370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -131428,82 +251770,82 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \reg3 - connect \Y $308 + connect \Y $369 end - process $group_137 + process $group_163 assign \int_src3__ren 32'00000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" switch { \rdpick_INT_rc_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" case 1'1 - assign \int_src3__ren $308 + assign \int_src3__ren $369 end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $310 + wire width 1 $371 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $311 + cell $and $372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$57 [2] - connect \B \fu_enable [5] - connect \Y $310 + connect \A \rd__rel$72 [2] + connect \B \fu_enable [6] + connect \Y $371 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $312 + wire width 1 $373 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $313 + cell $and $374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $310 + connect \A $371 connect \B \rdflag_INT_rc - connect \Y $312 + connect \Y $373 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $314 + wire width 1 $375 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $315 + cell $and $376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$60 [2] - connect \B \fu_enable [6] - connect \Y $314 + connect \A \rd__rel$75 [2] + connect \B \fu_enable [7] + connect \Y $375 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $316 + wire width 1 $377 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $317 + cell $and $378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $314 + connect \A $375 connect \B \rdflag_INT_rc - connect \Y $316 + connect \Y $377 end - process $group_138 + process $group_164 assign \rdpick_INT_rc_i 2'00 - assign \rdpick_INT_rc_i [0] $312 - assign \rdpick_INT_rc_i [1] $316 + assign \rdpick_INT_rc_i [0] $373 + assign \rdpick_INT_rc_i [1] $377 sync init end - process $group_139 + process $group_165 assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \fus_src3_i \int_src3__data_o sync init end - process $group_140 + process $group_166 assign \src3_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \src3_i \int_src3__data_o sync init @@ -131511,9 +251853,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" wire width 1 \rdflag_XER_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71" - wire width 1 $318 + wire width 1 $379 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71" - cell $and $319 + cell $and $380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -131521,14 +251863,14 @@ module \core parameter \Y_WIDTH 1 connect \A \oe connect \B \oe_ok - connect \Y $318 + connect \Y $379 end - process $group_141 + process $group_167 assign \rdflag_XER_xer_so 1'0 - assign \rdflag_XER_xer_so $318 + assign \rdflag_XER_xer_so $379 sync init end - process $group_142 + process $group_168 assign \xer_src1__ren 3'000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" switch { \rdpick_XER_xer_so_en_o } @@ -131539,9 +251881,9 @@ module \core sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $320 + wire width 1 $381 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $321 + cell $and $382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -131549,37 +251891,69 @@ module \core parameter \Y_WIDTH 1 connect \A \rd__rel [2] connect \B \fu_enable [0] - connect \Y $320 + connect \Y $381 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $322 + wire width 1 $383 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $323 + cell $and $384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $320 + connect \A $381 connect \B \rdflag_XER_xer_so - connect \Y $322 + connect \Y $383 end - process $group_143 - assign \rdpick_XER_xer_so_i 1'0 - assign \rdpick_XER_xer_so_i $322 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" + wire width 1 $385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" + cell $and $386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rd__rel$66 [2] + connect \B \fu_enable [4] + connect \Y $385 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" + wire width 1 $387 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" + cell $and $388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $385 + connect \B \rdflag_XER_xer_so + connect \Y $387 + end + process $group_169 + assign \rdpick_XER_xer_so_i 2'00 + assign \rdpick_XER_xer_so_i [0] $383 + assign \rdpick_XER_xer_so_i [1] $387 sync init end - process $group_144 - assign \fus_src3_i$149 1'0 - assign \fus_src3_i$149 \xer_src1__data_o [0] + process $group_170 + assign \fus_src3_i$181 1'0 + assign \fus_src3_i$181 \xer_src1__data_o [0] + sync init + end + process $group_171 + assign \fus_src3_i$182 1'0 + assign \fus_src3_i$182 \xer_src1__data_o [0] sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" wire width 1 \rdflag_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" - wire width 1 $324 + wire width 1 $389 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" - cell $eq $325 + cell $eq $390 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -131587,14 +251961,14 @@ module \core parameter \Y_WIDTH 1 connect \A \input_carry connect \B 2'10 - connect \Y $324 + connect \Y $389 end - process $group_145 + process $group_172 assign \rdflag_XER_xer_ca 1'0 - assign \rdflag_XER_xer_ca $324 + assign \rdflag_XER_xer_ca $389 sync init end - process $group_146 + process $group_173 assign \xer_src2__ren 3'000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" switch { \rdpick_XER_xer_ca_en_o } @@ -131605,9 +251979,9 @@ module \core sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $326 + wire width 1 $391 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $327 + cell $and $392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -131615,71 +251989,71 @@ module \core parameter \Y_WIDTH 1 connect \A \rd__rel [3] connect \B \fu_enable [0] - connect \Y $326 + connect \Y $391 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $328 + wire width 1 $393 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $329 + cell $and $394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $326 + connect \A $391 connect \B \rdflag_XER_xer_ca - connect \Y $328 + connect \Y $393 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $330 + wire width 1 $395 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $331 + cell $and $396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$57 [3] - connect \B \fu_enable [5] - connect \Y $330 + connect \A \rd__rel$72 [3] + connect \B \fu_enable [6] + connect \Y $395 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $332 + wire width 1 $397 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $333 + cell $and $398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $330 + connect \A $395 connect \B \rdflag_XER_xer_ca - connect \Y $332 + connect \Y $397 end - process $group_147 + process $group_174 assign \rdpick_XER_xer_ca_i 2'00 - assign \rdpick_XER_xer_ca_i [0] $328 - assign \rdpick_XER_xer_ca_i [1] $332 + assign \rdpick_XER_xer_ca_i [0] $393 + assign \rdpick_XER_xer_ca_i [1] $397 sync init end - process $group_148 + process $group_175 assign \fus_src4_i 2'00 assign \fus_src4_i \xer_src2__data_o sync init end - process $group_149 - assign \fus_src4_i$150 2'00 - assign \fus_src4_i$150 \xer_src2__data_o + process $group_176 + assign \fus_src4_i$183 2'00 + assign \fus_src4_i$183 \xer_src2__data_o sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" wire width 1 \rdflag_CR_full_cr - process $group_150 + process $group_177 assign \rdflag_CR_full_cr 1'0 assign \rdflag_CR_full_cr \read_cr_whole sync init end - process $group_151 + process $group_178 assign \cr_full_rd__ren 8'00000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" switch { \rdpick_CR_full_cr_en_o } @@ -131690,54 +252064,54 @@ module \core sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $334 + wire width 1 $399 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $335 + cell $and $400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$48 [2] + connect \A \rd__rel$60 [2] connect \B \fu_enable [1] - connect \Y $334 + connect \Y $399 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $336 + wire width 1 $401 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $337 + cell $and $402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $334 + connect \A $399 connect \B \rdflag_CR_full_cr - connect \Y $336 + connect \Y $401 end - process $group_152 + process $group_179 assign \rdpick_CR_full_cr_i 1'0 - assign \rdpick_CR_full_cr_i $336 + assign \rdpick_CR_full_cr_i $401 sync init end - process $group_153 - assign \fus_src3_i$151 32'00000000000000000000000000000000 - assign \fus_src3_i$151 \cr_full_rd__data_o + process $group_180 + assign \fus_src3_i$184 32'00000000000000000000000000000000 + assign \fus_src3_i$184 \cr_full_rd__data_o sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" wire width 1 \rdflag_CR_cr_a - process $group_154 + process $group_181 assign \rdflag_CR_cr_a 1'0 assign \rdflag_CR_cr_a \cr_in1_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59" - wire width 16 $338 + wire width 16 $403 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59" - wire width 4 $339 + wire width 4 $404 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59" - cell $sub $340 + cell $sub $405 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -131745,121 +252119,121 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \cr_in1 - connect \Y $339 + connect \Y $404 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59" - wire width 16 $341 + wire width 16 $406 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59" - cell $sshl $342 + cell $sshl $407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $339 - connect \Y $341 + connect \B $404 + connect \Y $406 end - connect $338 $341 - process $group_155 + connect $403 $406 + process $group_182 assign \cr_src1__ren 8'00000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" switch { \rdpick_CR_cr_a_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" case 1'1 - assign \cr_src1__ren $338 [7:0] + assign \cr_src1__ren $403 [7:0] end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $343 + wire width 1 $408 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $344 + cell $and $409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$48 [3] + connect \A \rd__rel$60 [3] connect \B \fu_enable [1] - connect \Y $343 + connect \Y $408 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $345 + wire width 1 $410 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $346 + cell $and $411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $343 + connect \A $408 connect \B \rdflag_CR_cr_a - connect \Y $345 + connect \Y $410 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $347 + wire width 1 $412 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $348 + cell $and $413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$68 [2] + connect \A \rd__rel$84 [2] connect \B \fu_enable [2] - connect \Y $347 + connect \Y $412 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $349 + wire width 1 $414 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $350 + cell $and $415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $347 + connect \A $412 connect \B \rdflag_CR_cr_a - connect \Y $349 + connect \Y $414 end - process $group_156 + process $group_183 assign \rdpick_CR_cr_a_i 2'00 - assign \rdpick_CR_cr_a_i [0] $345 - assign \rdpick_CR_cr_a_i [1] $349 + assign \rdpick_CR_cr_a_i [0] $410 + assign \rdpick_CR_cr_a_i [1] $414 sync init end - process $group_157 - assign \fus_src4_i$152 4'0000 - assign \fus_src4_i$152 \cr_src1__data_o + process $group_184 + assign \fus_src4_i$185 4'0000 + assign \fus_src4_i$185 \cr_src1__data_o sync init end - process $group_158 - assign \rd__go$69 4'0000 - assign \rd__go$69 [2] \rdpick_CR_cr_a_o [1] - assign \rd__go$69 [0] \rdpick_FAST_spr1_o [0] - assign \rd__go$69 [1] \rdpick_FAST_spr2_o [0] - assign \rd__go$69 [3] \rdpick_FAST_cia_o [0] + process $group_185 + assign \rd__go$85 4'0000 + assign \rd__go$85 [2] \rdpick_CR_cr_a_o [1] + assign \rd__go$85 [0] \rdpick_FAST_spr1_o [0] + assign \rd__go$85 [1] \rdpick_FAST_spr2_o [0] + assign \rd__go$85 [3] \rdpick_FAST_cia_o [0] sync init end - process $group_159 - assign \fus_src3_i$153 4'0000 - assign \fus_src3_i$153 \cr_src1__data_o + process $group_186 + assign \fus_src3_i$186 4'0000 + assign \fus_src3_i$186 \cr_src1__data_o sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" wire width 1 \rdflag_CR_cr_b - process $group_160 + process $group_187 assign \rdflag_CR_cr_b 1'0 assign \rdflag_CR_cr_b \cr_in2_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61" - wire width 16 $351 + wire width 16 $416 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61" - wire width 4 $352 + wire width 4 $417 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61" - cell $sub $353 + cell $sub $418 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -131867,161 +252241,161 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \cr_in2 - connect \Y $352 + connect \Y $417 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61" - wire width 16 $354 + wire width 16 $419 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61" - cell $sshl $355 + cell $sshl $420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $352 - connect \Y $354 + connect \B $417 + connect \Y $419 end - connect $351 $354 - process $group_161 + connect $416 $419 + process $group_188 assign \cr_src2__ren 8'00000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" switch { \rdpick_CR_cr_b_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" case 1'1 - assign \cr_src2__ren $351 [7:0] + assign \cr_src2__ren $416 [7:0] end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $356 + wire width 1 $421 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $357 + cell $and $422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$48 [4] + connect \A \rd__rel$60 [4] connect \B \fu_enable [1] - connect \Y $356 + connect \Y $421 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $358 + wire width 1 $423 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $359 + cell $and $424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $356 + connect \A $421 connect \B \rdflag_CR_cr_b - connect \Y $358 + connect \Y $423 end - process $group_162 + process $group_189 assign \rdpick_CR_cr_b_i 1'0 - assign \rdpick_CR_cr_b_i $358 + assign \rdpick_CR_cr_b_i $423 sync init end - process $group_163 + process $group_190 assign \fus_src5_i 4'0000 assign \fus_src5_i \cr_src2__data_o sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" wire width 1 \rdflag_CR_cr_c - process $group_164 + process $group_191 assign \rdflag_CR_cr_c 1'0 assign \rdflag_CR_cr_c \cr_in2_ok$5 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63" - wire width 16 $360 + wire width 16 $425 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63" - wire width 4 $361 + wire width 4 $426 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63" - cell $sub $362 + cell $sub $427 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 4 connect \A 3'111 - connect \B \cr_in2$70 - connect \Y $361 + connect \B \cr_in2$86 + connect \Y $426 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63" - wire width 16 $363 + wire width 16 $428 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63" - cell $sshl $364 + cell $sshl $429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $361 - connect \Y $363 + connect \B $426 + connect \Y $428 end - connect $360 $363 - process $group_165 + connect $425 $428 + process $group_192 assign \cr_src3__ren 8'00000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" switch { \rdpick_CR_cr_c_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" case 1'1 - assign \cr_src3__ren $360 [7:0] + assign \cr_src3__ren $425 [7:0] end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $365 + wire width 1 $430 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $366 + cell $and $431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$48 [5] + connect \A \rd__rel$60 [5] connect \B \fu_enable [1] - connect \Y $365 + connect \Y $430 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $367 + wire width 1 $432 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $368 + cell $and $433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $365 + connect \A $430 connect \B \rdflag_CR_cr_c - connect \Y $367 + connect \Y $432 end - process $group_166 + process $group_193 assign \rdpick_CR_cr_c_i 1'0 - assign \rdpick_CR_cr_c_i $367 + assign \rdpick_CR_cr_c_i $432 sync init end - process $group_167 + process $group_194 assign \fus_src6_i 4'0000 assign \fus_src6_i \cr_src3__data_o sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" wire width 1 \rdflag_FAST_spr1 - process $group_168 + process $group_195 assign \rdflag_FAST_spr1 1'0 assign \rdflag_FAST_spr1 \fast1_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:92" - wire width 8 $369 + wire width 8 $434 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:92" - cell $sshl $370 + cell $sshl $435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132029,97 +252403,97 @@ module \core parameter \Y_WIDTH 8 connect \A 1'1 connect \B \fast1 - connect \Y $369 + connect \Y $434 end - process $group_169 + process $group_196 assign \fast_src3__ren 8'00000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" switch { \rdpick_FAST_spr1_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" case 1'1 - assign \fast_src3__ren $369 + assign \fast_src3__ren $434 end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $371 + wire width 1 $436 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $372 + cell $and $437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$68 [0] + connect \A \rd__rel$84 [0] connect \B \fu_enable [2] - connect \Y $371 + connect \Y $436 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $373 + wire width 1 $438 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $374 + cell $and $439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $371 + connect \A $436 connect \B \rdflag_FAST_spr1 - connect \Y $373 + connect \Y $438 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $375 + wire width 1 $440 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $376 + cell $and $441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$51 [2] + connect \A \rd__rel$63 [2] connect \B \fu_enable [3] - connect \Y $375 + connect \Y $440 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $377 + wire width 1 $442 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $378 + cell $and $443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $375 + connect \A $440 connect \B \rdflag_FAST_spr1 - connect \Y $377 + connect \Y $442 end - process $group_170 + process $group_197 assign \rdpick_FAST_spr1_i 2'00 - assign \rdpick_FAST_spr1_i [0] $373 - assign \rdpick_FAST_spr1_i [1] $377 + assign \rdpick_FAST_spr1_i [0] $438 + assign \rdpick_FAST_spr1_i [1] $442 sync init end - process $group_171 - assign \src1_i$71 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_i$71 \fast_src3__data_o + process $group_198 + assign \src1_i$87 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$87 \fast_src3__data_o sync init end - process $group_172 - assign \fus_src3_i$154 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_src3_i$154 \fast_src3__data_o + process $group_199 + assign \fus_src3_i$187 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_src3_i$187 \fast_src3__data_o sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" wire width 1 \rdflag_FAST_spr2 - process $group_173 + process $group_200 assign \rdflag_FAST_spr2 1'0 assign \rdflag_FAST_spr2 \fast2_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:94" - wire width 8 $379 + wire width 8 $444 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:94" - cell $sshl $380 + cell $sshl $445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132127,97 +252501,97 @@ module \core parameter \Y_WIDTH 8 connect \A 1'1 connect \B \fast2 - connect \Y $379 + connect \Y $444 end - process $group_174 + process $group_201 assign \fast_src4__ren 8'00000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" switch { \rdpick_FAST_spr2_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" case 1'1 - assign \fast_src4__ren $379 + assign \fast_src4__ren $444 end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $381 + wire width 1 $446 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $382 + cell $and $447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$68 [1] + connect \A \rd__rel$84 [1] connect \B \fu_enable [2] - connect \Y $381 + connect \Y $446 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $383 + wire width 1 $448 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $384 + cell $and $449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $381 + connect \A $446 connect \B \rdflag_FAST_spr2 - connect \Y $383 + connect \Y $448 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $385 + wire width 1 $450 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $386 + cell $and $451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$51 [3] + connect \A \rd__rel$63 [3] connect \B \fu_enable [3] - connect \Y $385 + connect \Y $450 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $387 + wire width 1 $452 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $388 + cell $and $453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $385 + connect \A $450 connect \B \rdflag_FAST_spr2 - connect \Y $387 + connect \Y $452 end - process $group_175 + process $group_202 assign \rdpick_FAST_spr2_i 2'00 - assign \rdpick_FAST_spr2_i [0] $383 - assign \rdpick_FAST_spr2_i [1] $387 + assign \rdpick_FAST_spr2_i [0] $448 + assign \rdpick_FAST_spr2_i [1] $452 sync init end - process $group_176 - assign \src2_i$72 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_i$72 \fast_src4__data_o + process $group_203 + assign \src2_i$88 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$88 \fast_src4__data_o sync init end - process $group_177 - assign \fus_src4_i$155 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_src4_i$155 \fast_src4__data_o + process $group_204 + assign \fus_src4_i$188 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_src4_i$188 \fast_src4__data_o sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" wire width 1 \rdflag_FAST_cia wire width 1 $verilog_initial_trigger - process $group_178 + process $group_205 assign \rdflag_FAST_cia 1'0 assign \rdflag_FAST_cia 1'1 assign $verilog_initial_trigger $verilog_initial_trigger sync init update $verilog_initial_trigger 1'0 end - process $group_179 + process $group_206 assign \fast_src1__ren 8'00000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" switch { \rdpick_FAST_cia_en_o } @@ -132228,82 +252602,82 @@ module \core sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $389 + wire width 1 $454 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $390 + cell $and $455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$68 [3] + connect \A \rd__rel$84 [3] connect \B \fu_enable [2] - connect \Y $389 + connect \Y $454 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $391 + wire width 1 $456 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $392 + cell $and $457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $389 + connect \A $454 connect \B \rdflag_FAST_cia - connect \Y $391 + connect \Y $456 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $393 + wire width 1 $458 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $394 + cell $and $459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$51 [4] + connect \A \rd__rel$63 [4] connect \B \fu_enable [3] - connect \Y $393 + connect \Y $458 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $395 + wire width 1 $460 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $396 + cell $and $461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $393 + connect \A $458 connect \B \rdflag_FAST_cia - connect \Y $395 + connect \Y $460 end - process $group_180 + process $group_207 assign \rdpick_FAST_cia_i 2'00 - assign \rdpick_FAST_cia_i [0] $391 - assign \rdpick_FAST_cia_i [1] $395 + assign \rdpick_FAST_cia_i [0] $456 + assign \rdpick_FAST_cia_i [1] $460 sync init end - process $group_181 - assign \fus_src4_i$156 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_src4_i$156 \fast_src1__data_o + process $group_208 + assign \fus_src4_i$189 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_src4_i$189 \fast_src1__data_o sync init end - process $group_182 - assign \fus_src5_i$157 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_src5_i$157 \fast_src1__data_o + process $group_209 + assign \fus_src5_i$190 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_src5_i$190 \fast_src1__data_o sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" wire width 1 \rdflag_FAST_msr - process $group_183 + process $group_210 assign \rdflag_FAST_msr 1'0 assign \rdflag_FAST_msr 1'1 assign $verilog_initial_trigger $verilog_initial_trigger sync init end - process $group_184 + process $group_211 assign \fast_src2__ren 8'00000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" switch { \rdpick_FAST_msr_en_o } @@ -132314,45 +252688,45 @@ module \core sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $397 + wire width 1 $462 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $398 + cell $and $463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$51 [5] + connect \A \rd__rel$63 [5] connect \B \fu_enable [3] - connect \Y $397 + connect \Y $462 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $399 + wire width 1 $464 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $400 + cell $and $465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $397 + connect \A $462 connect \B \rdflag_FAST_msr - connect \Y $399 + connect \Y $464 end - process $group_185 + process $group_212 assign \rdpick_FAST_msr_i 1'0 - assign \rdpick_FAST_msr_i $399 + assign \rdpick_FAST_msr_i $464 sync init end - process $group_186 - assign \fus_src6_i$158 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_src6_i$158 \fast_src2__data_o + process $group_213 + assign \fus_src6_i$191 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_src6_i$191 \fast_src2__data_o sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - wire width 32 $401 + wire width 32 $466 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - cell $sshl $402 + cell $sshl $467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132360,15 +252734,15 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \rego - connect \Y $401 + connect \Y $466 end - process $group_187 + process $group_214 assign \int_wen$next \int_wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" switch { \wrpick_INT_o_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" case 1'1 - assign \int_wen$next $401 + assign \int_wen$next $466 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" case assign \int_wen$next 32'00000000000000000000000000000000 @@ -132385,15 +252759,15 @@ module \core end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_alu0_o_0 - process $group_188 + process $group_215 assign \wrflag_alu0_o_0 1'0 assign \wrflag_alu0_o_0 \fus_o_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $403 + wire width 1 $468 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $404 + cell $and $469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132401,87 +252775,101 @@ module \core parameter \Y_WIDTH 1 connect \A \wr__rel [0] connect \B \fu_enable [0] - connect \Y $403 + connect \Y $468 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $405 + wire width 1 $470 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $406 + cell $and $471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$73 [0] + connect \A \wr__rel$89 [0] connect \B \fu_enable [1] - connect \Y $405 + connect \Y $470 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $407 + wire width 1 $472 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $408 + cell $and $473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$75 [0] + connect \A \wr__rel$91 [0] connect \B \fu_enable [3] - connect \Y $407 + connect \Y $472 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $409 + wire width 1 $474 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $410 + cell $and $475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$77 [0] + connect \A \wr__rel$93 [0] connect \B \fu_enable [4] - connect \Y $409 + connect \Y $474 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $411 + wire width 1 $476 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $412 + cell $and $477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$79 [0] + connect \A \wr__rel$95 [0] connect \B \fu_enable [5] - connect \Y $411 + connect \Y $476 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $413 + wire width 1 $478 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $414 + cell $and $479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$81 [0] + connect \A \wr__rel$97 [0] connect \B \fu_enable [6] - connect \Y $413 + connect \Y $478 end - process $group_189 - assign \wrpick_INT_o_i 6'000000 - assign \wrpick_INT_o_i [0] $403 - assign \wrpick_INT_o_i [1] $405 - assign \wrpick_INT_o_i [2] $407 - assign \wrpick_INT_o_i [3] $409 - assign \wrpick_INT_o_i [4] $411 - assign \wrpick_INT_o_i [5] $413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" + wire width 1 $480 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" + cell $and $481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr__rel$99 [0] + connect \B \fu_enable [7] + connect \Y $480 + end + process $group_216 + assign \wrpick_INT_o_i 7'0000000 + assign \wrpick_INT_o_i [0] $468 + assign \wrpick_INT_o_i [1] $470 + assign \wrpick_INT_o_i [2] $472 + assign \wrpick_INT_o_i [3] $474 + assign \wrpick_INT_o_i [4] $476 + assign \wrpick_INT_o_i [5] $478 + assign \wrpick_INT_o_i [6] $480 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $415 + wire width 1 $482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $416 + cell $and $483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132489,12 +252877,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [0] connect \B \wrpick_INT_o_en_o - connect \Y $415 + connect \Y $482 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $417 + wire width 1 $484 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $418 + cell $and $485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132502,12 +252890,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [0] connect \B \wrpick_CR_cr_a_en_o - connect \Y $417 + connect \Y $484 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $419 + wire width 1 $486 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $420 + cell $and $487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132515,41 +252903,41 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [0] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $419 + connect \Y $486 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $421 + wire width 1 $488 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $422 + cell $and $489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o + connect \A \wrpick_XER_xer_ov_o [0] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $421 + connect \Y $488 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $423 + wire width 1 $490 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $424 + cell $and $491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o + connect \A \wrpick_XER_xer_so_o [0] connect \B \wrpick_XER_xer_so_en_o - connect \Y $423 + connect \Y $490 end - process $group_190 + process $group_217 assign \wr__go$next \wr__go - assign \wr__go$next [0] $415 - assign \wr__go$next [1] $417 - assign \wr__go$next [2] $419 - assign \wr__go$next [3] $421 - assign \wr__go$next [4] $423 + assign \wr__go$next [0] $482 + assign \wr__go$next [1] $484 + assign \wr__go$next [2] $486 + assign \wr__go$next [3] $488 + assign \wr__go$next [4] $490 sync init update \wr__go 5'00000 sync posedge \clk @@ -132557,15 +252945,15 @@ module \core end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_cr0_o_0 - process $group_191 + process $group_218 assign \wrflag_cr0_o_0 1'0 - assign \wrflag_cr0_o_0 \fus_o_ok$159 + assign \wrflag_cr0_o_0 \fus_o_ok$192 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $425 + wire width 1 $492 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $426 + cell $and $493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132573,12 +252961,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [1] connect \B \wrpick_INT_o_en_o - connect \Y $425 + connect \Y $492 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $427 + wire width 1 $494 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $428 + cell $and $495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132586,12 +252974,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_full_cr_o connect \B \wrpick_CR_full_cr_en_o - connect \Y $427 + connect \Y $494 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $429 + wire width 1 $496 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $430 + cell $and $497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132599,29 +252987,29 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [1] connect \B \wrpick_CR_cr_a_en_o - connect \Y $429 + connect \Y $496 end - process $group_192 - assign \wr__go$74$next \wr__go$74 - assign \wr__go$74$next [0] $425 - assign \wr__go$74$next [1] $427 - assign \wr__go$74$next [2] $429 + process $group_219 + assign \wr__go$90$next \wr__go$90 + assign \wr__go$90$next [0] $492 + assign \wr__go$90$next [1] $494 + assign \wr__go$90$next [2] $496 sync init - update \wr__go$74 3'000 + update \wr__go$90 3'000 sync posedge \clk - update \wr__go$74 \wr__go$74$next + update \wr__go$90 \wr__go$90$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_trap0_o_0 - process $group_193 + process $group_220 assign \wrflag_trap0_o_0 1'0 - assign \wrflag_trap0_o_0 \fus_o_ok$160 + assign \wrflag_trap0_o_0 \fus_o_ok$193 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $431 + wire width 1 $498 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $432 + cell $and $499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132629,12 +253017,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [2] connect \B \wrpick_INT_o_en_o - connect \Y $431 + connect \Y $498 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $433 + wire width 1 $500 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $434 + cell $and $501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132642,12 +253030,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_spr1_o [1] connect \B \wrpick_FAST_spr1_en_o - connect \Y $433 + connect \Y $500 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $435 + wire width 1 $502 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $436 + cell $and $503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132655,12 +253043,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_spr2_o [1] connect \B \wrpick_FAST_spr2_en_o - connect \Y $435 + connect \Y $502 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $437 + wire width 1 $504 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $438 + cell $and $505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132668,12 +253056,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_nia_o [1] connect \B \wrpick_FAST_nia_en_o - connect \Y $437 + connect \Y $504 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $439 + wire width 1 $506 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $440 + cell $and $507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132681,31 +253069,31 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_msr_o connect \B \wrpick_FAST_msr_en_o - connect \Y $439 + connect \Y $506 end - process $group_194 - assign \wr__go$76$next \wr__go$76 - assign \wr__go$76$next [0] $431 - assign \wr__go$76$next [1] $433 - assign \wr__go$76$next [2] $435 - assign \wr__go$76$next [3] $437 - assign \wr__go$76$next [4] $439 - sync init - update \wr__go$76 5'00000 + process $group_221 + assign \wr__go$92$next \wr__go$92 + assign \wr__go$92$next [0] $498 + assign \wr__go$92$next [1] $500 + assign \wr__go$92$next [2] $502 + assign \wr__go$92$next [3] $504 + assign \wr__go$92$next [4] $506 + sync init + update \wr__go$92 5'00000 sync posedge \clk - update \wr__go$76 \wr__go$76$next + update \wr__go$92 \wr__go$92$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 \wrflag_logical0_o_0 - process $group_195 - assign \wrflag_logical0_o_0 1'0 - assign \wrflag_logical0_o_0 \fus_o_ok$161 + wire width 1 \wrflag_div0_o_0 + process $group_222 + assign \wrflag_div0_o_0 1'0 + assign \wrflag_div0_o_0 \fus_o_ok$194 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $441 + wire width 1 $508 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $442 + cell $and $509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132713,12 +253101,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [3] connect \B \wrpick_INT_o_en_o - connect \Y $441 + connect \Y $508 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $443 + wire width 1 $510 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $444 + cell $and $511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132726,12 +253114,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [2] connect \B \wrpick_CR_cr_a_en_o - connect \Y $443 + connect \Y $510 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $445 + wire width 1 $512 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $446 + cell $and $513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132739,29 +253127,57 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [1] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $445 + connect \Y $512 end - process $group_196 - assign \wr__go$78$next \wr__go$78 - assign \wr__go$78$next [0] $441 - assign \wr__go$78$next [1] $443 - assign \wr__go$78$next [2] $445 - sync init - update \wr__go$78 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" + wire width 1 $514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" + cell $and $515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [1] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $514 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" + wire width 1 $516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" + cell $and $517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_so_o [1] + connect \B \wrpick_XER_xer_so_en_o + connect \Y $516 + end + process $group_223 + assign \wr__go$94$next \wr__go$94 + assign \wr__go$94$next [0] $508 + assign \wr__go$94$next [1] $510 + assign \wr__go$94$next [2] $512 + assign \wr__go$94$next [3] $514 + assign \wr__go$94$next [4] $516 + sync init + update \wr__go$94 5'00000 sync posedge \clk - update \wr__go$78 \wr__go$78$next + update \wr__go$94 \wr__go$94$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 \wrflag_shiftrot0_o_0 - process $group_197 - assign \wrflag_shiftrot0_o_0 1'0 - assign \wrflag_shiftrot0_o_0 \fus_o_ok$162 + wire width 1 \wrflag_logical0_o_0 + process $group_224 + assign \wrflag_logical0_o_0 1'0 + assign \wrflag_logical0_o_0 \fus_o_ok$195 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $447 + wire width 1 $518 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $448 + cell $and $519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132769,12 +253185,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [4] connect \B \wrpick_INT_o_en_o - connect \Y $447 + connect \Y $518 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $449 + wire width 1 $520 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $450 + cell $and $521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132782,12 +253198,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [3] connect \B \wrpick_CR_cr_a_en_o - connect \Y $449 + connect \Y $520 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $451 + wire width 1 $522 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $452 + cell $and $523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132795,42 +253211,98 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [2] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $451 + connect \Y $522 end - process $group_198 - assign \wr__go$80$next \wr__go$80 - assign \wr__go$80$next [0] $447 - assign \wr__go$80$next [1] $449 - assign \wr__go$80$next [2] $451 + process $group_225 + assign \wr__go$96$next \wr__go$96 + assign \wr__go$96$next [0] $518 + assign \wr__go$96$next [1] $520 + assign \wr__go$96$next [2] $522 + sync init + update \wr__go$96 3'000 + sync posedge \clk + update \wr__go$96 \wr__go$96$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 \wrflag_shiftrot0_o_0 + process $group_226 + assign \wrflag_shiftrot0_o_0 1'0 + assign \wrflag_shiftrot0_o_0 \fus_o_ok$196 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" + wire width 1 $524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" + cell $and $525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [5] + connect \B \wrpick_INT_o_en_o + connect \Y $524 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" + wire width 1 $526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" + cell $and $527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_CR_cr_a_o [4] + connect \B \wrpick_CR_cr_a_en_o + connect \Y $526 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" + wire width 1 $528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" + cell $and $529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ca_o [3] + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $528 + end + process $group_227 + assign \wr__go$98$next \wr__go$98 + assign \wr__go$98$next [0] $524 + assign \wr__go$98$next [1] $526 + assign \wr__go$98$next [2] $528 sync init - update \wr__go$80 3'000 + update \wr__go$98 3'000 sync posedge \clk - update \wr__go$80 \wr__go$80$next + update \wr__go$98 \wr__go$98$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_ldst0_o_0 - process $group_199 + process $group_228 assign \wrflag_ldst0_o_0 1'0 assign \wrflag_ldst0_o_0 \o_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $453 + wire width 1 $530 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $454 + cell $and $531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [5] + connect \A \wrpick_INT_o_o [6] connect \B \wrpick_INT_o_en_o - connect \Y $453 + connect \Y $530 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $455 + wire width 1 $532 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $456 + cell $and $533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132838,85 +253310,98 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o1_o connect \B \wrpick_INT_o1_en_o - connect \Y $455 + connect \Y $532 end - process $group_200 - assign \wr__go$82$next \wr__go$82 - assign \wr__go$82$next [0] $453 - assign \wr__go$82$next [1] $455 + process $group_229 + assign \wr__go$100$next \wr__go$100 + assign \wr__go$100$next [0] $530 + assign \wr__go$100$next [1] $532 sync init - update \wr__go$82 2'00 + update \wr__go$100 2'00 sync posedge \clk - update \wr__go$82 \wr__go$82$next + update \wr__go$100 \wr__go$100$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 64 $457 + wire width 64 $534 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $458 + cell $or $535 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_o$163 - connect \B \fus_o$164 - connect \Y $457 + connect \A \fus_o$197 + connect \B \fus_o$198 + connect \Y $534 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - wire width 64 $459 + wire width 64 $536 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - cell $or $460 + cell $or $537 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_o - connect \B $457 - connect \Y $459 + connect \B $534 + connect \Y $536 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + wire width 64 $538 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + cell $or $539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_o$199 + connect \B \fus_o$200 + connect \Y $538 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 64 $461 + wire width 64 $540 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $462 + cell $or $541 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_o$166 + connect \A \fus_o$201 connect \B \o - connect \Y $461 + connect \Y $540 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - wire width 64 $463 + wire width 64 $542 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - cell $or $464 + cell $or $543 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_o$165 - connect \B $461 - connect \Y $463 + connect \A $538 + connect \B $540 + connect \Y $542 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - wire width 64 $465 + wire width 64 $544 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - cell $or $466 + cell $or $545 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $459 - connect \B $463 - connect \Y $465 + connect \A $536 + connect \B $542 + connect \Y $544 end - process $group_201 + process $group_230 assign \int_data_i$next \int_data_i - assign \int_data_i$next $465 + assign \int_data_i$next $544 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -132928,9 +253413,9 @@ module \core update \int_data_i \int_data_i$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:110" - wire width 32 $467 + wire width 32 $546 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:110" - cell $sshl $468 + cell $sshl $547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132938,68 +253423,68 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \ea - connect \Y $467 + connect \Y $546 end - process $group_202 - assign \int_wen$183$next \int_wen$183 + process $group_231 + assign \int_wen$226$next \int_wen$226 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" switch { \wrpick_INT_o1_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" case 1'1 - assign \int_wen$183$next $467 + assign \int_wen$226$next $546 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" case - assign \int_wen$183$next 32'00000000000000000000000000000000 + assign \int_wen$226$next 32'00000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \int_wen$183$next 32'00000000000000000000000000000000 + assign \int_wen$226$next 32'00000000000000000000000000000000 end sync init - update \int_wen$183 32'00000000000000000000000000000000 + update \int_wen$226 32'00000000000000000000000000000000 sync posedge \clk - update \int_wen$183 \int_wen$183$next + update \int_wen$226 \int_wen$226$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_ldst0_o1_1 - process $group_203 + process $group_232 assign \wrflag_ldst0_o1_1 1'0 assign \wrflag_ldst0_o1_1 \ea_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $469 + wire width 1 $548 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $470 + cell $and $549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$81 [1] - connect \B \fu_enable [6] - connect \Y $469 + connect \A \wr__rel$99 [1] + connect \B \fu_enable [7] + connect \Y $548 end - process $group_204 + process $group_233 assign \wrpick_INT_o1_i 1'0 - assign \wrpick_INT_o1_i $469 + assign \wrpick_INT_o1_i $548 sync init end - process $group_205 - assign \int_data_i$184$next \int_data_i$184 - assign \int_data_i$184$next \ea$83 + process $group_234 + assign \int_data_i$227$next \int_data_i$227 + assign \int_data_i$227$next \ea$101 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \int_data_i$184$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \int_data_i$227$next 64'0000000000000000000000000000000000000000000000000000000000000000 end sync init - update \int_data_i$184 64'0000000000000000000000000000000000000000000000000000000000000000 + update \int_data_i$227 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk - update \int_data_i$184 \int_data_i$184$next + update \int_data_i$227 \int_data_i$227$next end - process $group_206 + process $group_235 assign \cr_full_wr__wen$next \cr_full_wr__wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" switch { \wrpick_CR_full_cr_en_o } @@ -133022,30 +253507,30 @@ module \core end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_cr0_full_cr_1 - process $group_207 + process $group_236 assign \wrflag_cr0_full_cr_1 1'0 assign \wrflag_cr0_full_cr_1 \fus_full_cr_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $471 + wire width 1 $550 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $472 + cell $and $551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$73 [1] + connect \A \wr__rel$89 [1] connect \B \fu_enable [1] - connect \Y $471 + connect \Y $550 end - process $group_208 + process $group_237 assign \wrpick_CR_full_cr_i 1'0 - assign \wrpick_CR_full_cr_i $471 + assign \wrpick_CR_full_cr_i $550 sync init end - process $group_209 + process $group_238 assign \cr_full_wr__data_i$next \cr_full_wr__data_i assign \cr_full_wr__data_i$next \fus_full_cr attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -133059,11 +253544,11 @@ module \core update \cr_full_wr__data_i \cr_full_wr__data_i$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118" - wire width 16 $473 + wire width 16 $552 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118" - wire width 4 $474 + wire width 4 $553 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118" - cell $sub $475 + cell $sub $554 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -133071,29 +253556,29 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \cr_out - connect \Y $474 + connect \Y $553 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118" - wire width 16 $476 + wire width 16 $555 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118" - cell $sshl $477 + cell $sshl $556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $474 - connect \Y $476 + connect \B $553 + connect \Y $555 end - connect $473 $476 - process $group_210 + connect $552 $555 + process $group_239 assign \cr_wen$next \cr_wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" switch { \wrpick_CR_cr_a_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" case 1'1 - assign \cr_wen$next $473 [7:0] + assign \cr_wen$next $552 [7:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" case assign \cr_wen$next 8'00000000 @@ -133110,15 +253595,15 @@ module \core end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_alu0_cr_a_1 - process $group_211 + process $group_240 assign \wrflag_alu0_cr_a_1 1'0 assign \wrflag_alu0_cr_a_1 \fus_cr_a_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $478 + wire width 1 $557 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $479 + cell $and $558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133126,118 +253611,152 @@ module \core parameter \Y_WIDTH 1 connect \A \wr__rel [1] connect \B \fu_enable [0] - connect \Y $478 + connect \Y $557 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $480 + wire width 1 $559 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $481 + cell $and $560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$73 [2] + connect \A \wr__rel$89 [2] connect \B \fu_enable [1] - connect \Y $480 + connect \Y $559 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $482 + wire width 1 $561 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $483 + cell $and $562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$77 [1] + connect \A \wr__rel$93 [1] connect \B \fu_enable [4] - connect \Y $482 + connect \Y $561 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $484 + wire width 1 $563 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $485 + cell $and $564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$79 [1] + connect \A \wr__rel$95 [1] connect \B \fu_enable [5] - connect \Y $484 + connect \Y $563 end - process $group_212 - assign \wrpick_CR_cr_a_i 4'0000 - assign \wrpick_CR_cr_a_i [0] $478 - assign \wrpick_CR_cr_a_i [1] $480 - assign \wrpick_CR_cr_a_i [2] $482 - assign \wrpick_CR_cr_a_i [3] $484 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" + wire width 1 $565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" + cell $and $566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr__rel$97 [1] + connect \B \fu_enable [6] + connect \Y $565 + end + process $group_241 + assign \wrpick_CR_cr_a_i 5'00000 + assign \wrpick_CR_cr_a_i [0] $557 + assign \wrpick_CR_cr_a_i [1] $559 + assign \wrpick_CR_cr_a_i [2] $561 + assign \wrpick_CR_cr_a_i [3] $563 + assign \wrpick_CR_cr_a_i [4] $565 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_cr0_cr_a_2 - process $group_213 + process $group_242 assign \wrflag_cr0_cr_a_2 1'0 - assign \wrflag_cr0_cr_a_2 \fus_cr_a_ok$167 + assign \wrflag_cr0_cr_a_2 \fus_cr_a_ok$202 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 \wrflag_div0_cr_a_1 + process $group_243 + assign \wrflag_div0_cr_a_1 1'0 + assign \wrflag_div0_cr_a_1 \fus_cr_a_ok$203 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_logical0_cr_a_1 - process $group_214 + process $group_244 assign \wrflag_logical0_cr_a_1 1'0 - assign \wrflag_logical0_cr_a_1 \fus_cr_a_ok$168 + assign \wrflag_logical0_cr_a_1 \fus_cr_a_ok$204 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_shiftrot0_cr_a_1 - process $group_215 + process $group_245 assign \wrflag_shiftrot0_cr_a_1 1'0 - assign \wrflag_shiftrot0_cr_a_1 \fus_cr_a_ok$169 + assign \wrflag_shiftrot0_cr_a_1 \fus_cr_a_ok$205 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 4 $486 + wire width 4 $567 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $487 + cell $or $568 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_cr_a - connect \B \fus_cr_a$170 - connect \Y $486 + connect \B \fus_cr_a$206 + connect \Y $567 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 4 $488 + wire width 4 $569 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $489 + cell $or $570 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \fus_cr_a$171 - connect \B \fus_cr_a$172 - connect \Y $488 + connect \A \fus_cr_a$208 + connect \B \fus_cr_a$209 + connect \Y $569 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - wire width 4 $490 + wire width 4 $571 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - cell $or $491 + cell $or $572 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $486 - connect \B $488 - connect \Y $490 + connect \A \fus_cr_a$207 + connect \B $569 + connect \Y $571 end - process $group_216 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" + wire width 4 $573 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" + cell $or $574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $567 + connect \B $571 + connect \Y $573 + end + process $group_246 assign \cr_data_i$next \cr_data_i - assign \cr_data_i$next $490 + assign \cr_data_i$next $573 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -133248,7 +253767,7 @@ module \core sync posedge \clk update \cr_data_i \cr_data_i$next end - process $group_217 + process $group_247 assign \xer_wen$next \xer_wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" switch { \wrpick_XER_xer_ca_en_o } @@ -133271,15 +253790,15 @@ module \core end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_alu0_xer_ca_2 - process $group_218 + process $group_248 assign \wrflag_alu0_xer_ca_2 1'0 assign \wrflag_alu0_xer_ca_2 \fus_xer_ca_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $492 + wire width 1 $575 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $493 + cell $and $576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133287,84 +253806,118 @@ module \core parameter \Y_WIDTH 1 connect \A \wr__rel [2] connect \B \fu_enable [0] - connect \Y $492 + connect \Y $575 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $494 + wire width 1 $577 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $495 + cell $and $578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$77 [2] + connect \A \wr__rel$93 [2] connect \B \fu_enable [4] - connect \Y $494 + connect \Y $577 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $496 + wire width 1 $579 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $497 + cell $and $580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$79 [2] + connect \A \wr__rel$95 [2] connect \B \fu_enable [5] - connect \Y $496 + connect \Y $579 end - process $group_219 - assign \wrpick_XER_xer_ca_i 3'000 - assign \wrpick_XER_xer_ca_i [0] $492 - assign \wrpick_XER_xer_ca_i [1] $494 - assign \wrpick_XER_xer_ca_i [2] $496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" + wire width 1 $581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" + cell $and $582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr__rel$97 [2] + connect \B \fu_enable [6] + connect \Y $581 + end + process $group_249 + assign \wrpick_XER_xer_ca_i 4'0000 + assign \wrpick_XER_xer_ca_i [0] $575 + assign \wrpick_XER_xer_ca_i [1] $577 + assign \wrpick_XER_xer_ca_i [2] $579 + assign \wrpick_XER_xer_ca_i [3] $581 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 \wrflag_div0_xer_ca_2 + process $group_250 + assign \wrflag_div0_xer_ca_2 1'0 + assign \wrflag_div0_xer_ca_2 \fus_xer_ca_ok$210 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_logical0_xer_ca_2 - process $group_220 + process $group_251 assign \wrflag_logical0_xer_ca_2 1'0 - assign \wrflag_logical0_xer_ca_2 \fus_xer_ca_ok$173 + assign \wrflag_logical0_xer_ca_2 \fus_xer_ca_ok$211 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_shiftrot0_xer_ca_2 - process $group_221 + process $group_252 assign \wrflag_shiftrot0_xer_ca_2 1'0 - assign \wrflag_shiftrot0_xer_ca_2 \fus_xer_ca_ok$174 + assign \wrflag_shiftrot0_xer_ca_2 \fus_xer_ca_ok$212 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 2 $498 + wire width 2 $583 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $499 + cell $or $584 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \fus_xer_ca$175 - connect \B \fus_xer_ca$176 - connect \Y $498 + connect \A \fus_xer_ca + connect \B \fus_xer_ca$213 + connect \Y $583 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + wire width 2 $585 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + cell $or $586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \fus_xer_ca$214 + connect \B \fus_xer_ca$215 + connect \Y $585 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - wire width 2 $500 + wire width 2 $587 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - cell $or $501 + cell $or $588 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \fus_xer_ca - connect \B $498 - connect \Y $500 + connect \A $583 + connect \B $585 + connect \Y $587 end - process $group_222 + process $group_253 assign \xer_data_i$next \xer_data_i - assign \xer_data_i$next $500 + assign \xer_data_i$next $587 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -133375,38 +253928,38 @@ module \core sync posedge \clk update \xer_data_i \xer_data_i$next end - process $group_223 - assign \xer_wen$185$next \xer_wen$185 + process $group_254 + assign \xer_wen$228$next \xer_wen$228 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" switch { \wrpick_XER_xer_ov_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" case 1'1 - assign \xer_wen$185$next 3'100 + assign \xer_wen$228$next 3'100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" case - assign \xer_wen$185$next 3'000 + assign \xer_wen$228$next 3'000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \xer_wen$185$next 3'000 + assign \xer_wen$228$next 3'000 end sync init - update \xer_wen$185 3'000 + update \xer_wen$228 3'000 sync posedge \clk - update \xer_wen$185 \xer_wen$185$next + update \xer_wen$228 \xer_wen$228$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_alu0_xer_ov_3 - process $group_224 + process $group_255 assign \wrflag_alu0_xer_ov_3 1'0 assign \wrflag_alu0_xer_ov_3 \fus_xer_ov_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $502 + wire width 1 $589 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $503 + cell $and $590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133414,58 +253967,92 @@ module \core parameter \Y_WIDTH 1 connect \A \wr__rel [3] connect \B \fu_enable [0] - connect \Y $502 + connect \Y $589 end - process $group_225 - assign \wrpick_XER_xer_ov_i 1'0 - assign \wrpick_XER_xer_ov_i $502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" + wire width 1 $591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" + cell $and $592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr__rel$93 [3] + connect \B \fu_enable [4] + connect \Y $591 + end + process $group_256 + assign \wrpick_XER_xer_ov_i 2'00 + assign \wrpick_XER_xer_ov_i [0] $589 + assign \wrpick_XER_xer_ov_i [1] $591 sync init end - process $group_226 - assign \xer_data_i$186$next \xer_data_i$186 - assign \xer_data_i$186$next \fus_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 \wrflag_div0_xer_ov_3 + process $group_257 + assign \wrflag_div0_xer_ov_3 1'0 + assign \wrflag_div0_xer_ov_3 \fus_xer_ov_ok$216 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + wire width 2 $593 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + cell $or $594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \fus_xer_ov + connect \B \fus_xer_ov$217 + connect \Y $593 + end + process $group_258 + assign \xer_data_i$229$next \xer_data_i$229 + assign \xer_data_i$229$next $593 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \xer_data_i$186$next 2'00 + assign \xer_data_i$229$next 2'00 end sync init - update \xer_data_i$186 2'00 + update \xer_data_i$229 2'00 sync posedge \clk - update \xer_data_i$186 \xer_data_i$186$next + update \xer_data_i$229 \xer_data_i$229$next end - process $group_227 - assign \xer_wen$187$next \xer_wen$187 + process $group_259 + assign \xer_wen$230$next \xer_wen$230 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" switch { \wrpick_XER_xer_so_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" case 1'1 - assign \xer_wen$187$next 3'001 + assign \xer_wen$230$next 3'001 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" case - assign \xer_wen$187$next 3'000 + assign \xer_wen$230$next 3'000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \xer_wen$187$next 3'000 + assign \xer_wen$230$next 3'000 end sync init - update \xer_wen$187 3'000 + update \xer_wen$230 3'000 sync posedge \clk - update \xer_wen$187 \xer_wen$187$next + update \xer_wen$230 \xer_wen$230$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_alu0_xer_so_4 - process $group_228 + process $group_260 assign \wrflag_alu0_xer_so_4 1'0 assign \wrflag_alu0_xer_so_4 \fus_xer_so_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $504 + wire width 1 $595 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $505 + cell $and $596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133473,40 +254060,74 @@ module \core parameter \Y_WIDTH 1 connect \A \wr__rel [4] connect \B \fu_enable [0] - connect \Y $504 + connect \Y $595 end - process $group_229 - assign \wrpick_XER_xer_so_i 1'0 - assign \wrpick_XER_xer_so_i $504 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" + wire width 1 $597 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" + cell $and $598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr__rel$93 [4] + connect \B \fu_enable [4] + connect \Y $597 + end + process $group_261 + assign \wrpick_XER_xer_so_i 2'00 + assign \wrpick_XER_xer_so_i [0] $595 + assign \wrpick_XER_xer_so_i [1] $597 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 $506 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - cell $pos $507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + wire width 1 \wrflag_div0_xer_so_4 + process $group_262 + assign \wrflag_div0_xer_so_4 1'0 + assign \wrflag_div0_xer_so_4 \fus_xer_so_ok$218 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + wire width 2 $599 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + wire width 1 $600 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + cell $or $601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 connect \A \fus_xer_so - connect \Y $506 + connect \B \fus_xer_so$219 + connect \Y $600 end - process $group_230 - assign \xer_data_i$188$next \xer_data_i$188 - assign \xer_data_i$188$next $506 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + cell $pos $602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A $600 + connect \Y $599 + end + process $group_263 + assign \xer_data_i$231$next \xer_data_i$231 + assign \xer_data_i$231$next $599 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \xer_data_i$188$next 2'00 + assign \xer_data_i$231$next 2'00 end sync init - update \xer_data_i$188 2'00 + update \xer_data_i$231 2'00 sync posedge \clk - update \xer_data_i$188 \xer_data_i$188$next + update \xer_data_i$231 \xer_data_i$231$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:147" - wire width 8 $508 + wire width 8 $603 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:147" - cell $sshl $509 + cell $sshl $604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133514,15 +254135,15 @@ module \core parameter \Y_WIDTH 8 connect \A 1'1 connect \B \fasto1 - connect \Y $508 + connect \Y $603 end - process $group_231 + process $group_264 assign \fast_wen$next \fast_wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" switch { \wrpick_FAST_spr1_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" case 1'1 - assign \fast_wen$next $508 + assign \fast_wen$next $603 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" case assign \fast_wen$next 8'00000000 @@ -133539,47 +254160,47 @@ module \core end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_branch0_spr1_0 - process $group_232 + process $group_265 assign \wrflag_branch0_spr1_0 1'0 assign \wrflag_branch0_spr1_0 \fus_spr1_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $510 + wire width 1 $605 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $511 + cell $and $606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$84 [0] + connect \A \wr__rel$102 [0] connect \B \fu_enable [2] - connect \Y $510 + connect \Y $605 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $512 + wire width 1 $607 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $513 + cell $and $608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$75 [1] + connect \A \wr__rel$91 [1] connect \B \fu_enable [3] - connect \Y $512 + connect \Y $607 end - process $group_233 + process $group_266 assign \wrpick_FAST_spr1_i 2'00 - assign \wrpick_FAST_spr1_i [0] $510 - assign \wrpick_FAST_spr1_i [1] $512 + assign \wrpick_FAST_spr1_i [0] $605 + assign \wrpick_FAST_spr1_i [1] $607 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $514 + wire width 1 $609 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $515 + cell $and $610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133587,12 +254208,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_spr1_o [0] connect \B \wrpick_FAST_spr1_en_o - connect \Y $514 + connect \Y $609 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $516 + wire width 1 $611 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $517 + cell $and $612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133600,12 +254221,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_spr2_o [0] connect \B \wrpick_FAST_spr2_en_o - connect \Y $516 + connect \Y $611 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $518 + wire width 1 $613 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $519 + cell $and $614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133613,41 +254234,41 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_nia_o [0] connect \B \wrpick_FAST_nia_en_o - connect \Y $518 + connect \Y $613 end - process $group_234 - assign \wr__go$85$next \wr__go$85 - assign \wr__go$85$next [0] $514 - assign \wr__go$85$next [1] $516 - assign \wr__go$85$next [2] $518 + process $group_267 + assign \wr__go$103$next \wr__go$103 + assign \wr__go$103$next [0] $609 + assign \wr__go$103$next [1] $611 + assign \wr__go$103$next [2] $613 sync init - update \wr__go$85 3'000 + update \wr__go$103 3'000 sync posedge \clk - update \wr__go$85 \wr__go$85$next + update \wr__go$103 \wr__go$103$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_trap0_spr1_1 - process $group_235 + process $group_268 assign \wrflag_trap0_spr1_1 1'0 - assign \wrflag_trap0_spr1_1 \fus_spr1_ok$177 + assign \wrflag_trap0_spr1_1 \fus_spr1_ok$220 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 64 $520 + wire width 64 $615 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $521 + cell $or $616 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_spr1 - connect \B \fus_spr1$178 - connect \Y $520 + connect \B \fus_spr1$221 + connect \Y $615 end - process $group_236 + process $group_269 assign \fast_data_i$next \fast_data_i - assign \fast_data_i$next $520 + assign \fast_data_i$next $615 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -133659,9 +254280,9 @@ module \core update \fast_data_i \fast_data_i$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:149" - wire width 8 $522 + wire width 8 $617 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:149" - cell $sshl $523 + cell $sshl $618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133669,102 +254290,102 @@ module \core parameter \Y_WIDTH 8 connect \A 1'1 connect \B \fasto2 - connect \Y $522 + connect \Y $617 end - process $group_237 - assign \fast_wen$189$next \fast_wen$189 + process $group_270 + assign \fast_wen$232$next \fast_wen$232 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" switch { \wrpick_FAST_spr2_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" case 1'1 - assign \fast_wen$189$next $522 + assign \fast_wen$232$next $617 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" case - assign \fast_wen$189$next 8'00000000 + assign \fast_wen$232$next 8'00000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \fast_wen$189$next 8'00000000 + assign \fast_wen$232$next 8'00000000 end sync init - update \fast_wen$189 8'00000000 + update \fast_wen$232 8'00000000 sync posedge \clk - update \fast_wen$189 \fast_wen$189$next + update \fast_wen$232 \fast_wen$232$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_branch0_spr2_1 - process $group_238 + process $group_271 assign \wrflag_branch0_spr2_1 1'0 assign \wrflag_branch0_spr2_1 \fus_spr2_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $524 + wire width 1 $619 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $525 + cell $and $620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$84 [1] + connect \A \wr__rel$102 [1] connect \B \fu_enable [2] - connect \Y $524 + connect \Y $619 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $526 + wire width 1 $621 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $527 + cell $and $622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$75 [2] + connect \A \wr__rel$91 [2] connect \B \fu_enable [3] - connect \Y $526 + connect \Y $621 end - process $group_239 + process $group_272 assign \wrpick_FAST_spr2_i 2'00 - assign \wrpick_FAST_spr2_i [0] $524 - assign \wrpick_FAST_spr2_i [1] $526 + assign \wrpick_FAST_spr2_i [0] $619 + assign \wrpick_FAST_spr2_i [1] $621 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_trap0_spr2_2 - process $group_240 + process $group_273 assign \wrflag_trap0_spr2_2 1'0 - assign \wrflag_trap0_spr2_2 \fus_spr2_ok$179 + assign \wrflag_trap0_spr2_2 \fus_spr2_ok$222 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 64 $528 + wire width 64 $623 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $529 + cell $or $624 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_spr2 - connect \B \fus_spr2$180 - connect \Y $528 + connect \B \fus_spr2$223 + connect \Y $623 end - process $group_241 - assign \fast_data_i$190$next \fast_data_i$190 - assign \fast_data_i$190$next $528 + process $group_274 + assign \fast_data_i$233$next \fast_data_i$233 + assign \fast_data_i$233$next $623 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \fast_data_i$190$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast_data_i$233$next 64'0000000000000000000000000000000000000000000000000000000000000000 end sync init - update \fast_data_i$190 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast_data_i$233 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk - update \fast_data_i$190 \fast_data_i$190$next + update \fast_data_i$233 \fast_data_i$233$next end - process $group_242 + process $group_275 assign \fast_nia_wen$next \fast_nia_wen attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" switch { \wrpick_FAST_nia_en_o } @@ -133787,134 +254408,134 @@ module \core end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_branch0_nia_2 - process $group_243 + process $group_276 assign \wrflag_branch0_nia_2 1'0 assign \wrflag_branch0_nia_2 \fus_nia_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $530 + wire width 1 $625 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $531 + cell $and $626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$84 [2] + connect \A \wr__rel$102 [2] connect \B \fu_enable [2] - connect \Y $530 + connect \Y $625 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $532 + wire width 1 $627 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $533 + cell $and $628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$75 [3] + connect \A \wr__rel$91 [3] connect \B \fu_enable [3] - connect \Y $532 + connect \Y $627 end - process $group_244 + process $group_277 assign \wrpick_FAST_nia_i 2'00 - assign \wrpick_FAST_nia_i [0] $530 - assign \wrpick_FAST_nia_i [1] $532 + assign \wrpick_FAST_nia_i [0] $625 + assign \wrpick_FAST_nia_i [1] $627 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_trap0_nia_3 - process $group_245 + process $group_278 assign \wrflag_trap0_nia_3 1'0 - assign \wrflag_trap0_nia_3 \fus_nia_ok$181 + assign \wrflag_trap0_nia_3 \fus_nia_ok$224 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 64 $534 + wire width 64 $629 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $535 + cell $or $630 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_nia - connect \B \fus_nia$182 - connect \Y $534 + connect \B \fus_nia$225 + connect \Y $629 end - process $group_246 - assign \fast_data_i$191$next \fast_data_i$191 - assign \fast_data_i$191$next $534 + process $group_279 + assign \fast_data_i$234$next \fast_data_i$234 + assign \fast_data_i$234$next $629 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \fast_data_i$191$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast_data_i$234$next 64'0000000000000000000000000000000000000000000000000000000000000000 end sync init - update \fast_data_i$191 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast_data_i$234 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk - update \fast_data_i$191 \fast_data_i$191$next + update \fast_data_i$234 \fast_data_i$234$next end - process $group_247 - assign \fast_wen$192$next \fast_wen$192 + process $group_280 + assign \fast_wen$235$next \fast_wen$235 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" switch { \wrpick_FAST_msr_en_o } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" case 1'1 - assign \fast_wen$192$next 8'00000010 + assign \fast_wen$235$next 8'00000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" case - assign \fast_wen$192$next 8'00000000 + assign \fast_wen$235$next 8'00000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \fast_wen$192$next 8'00000000 + assign \fast_wen$235$next 8'00000000 end sync init - update \fast_wen$192 8'00000000 + update \fast_wen$235 8'00000000 sync posedge \clk - update \fast_wen$192 \fast_wen$192$next + update \fast_wen$235 \fast_wen$235$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" wire width 1 \wrflag_trap0_msr_4 - process $group_248 + process $group_281 assign \wrflag_trap0_msr_4 1'0 assign \wrflag_trap0_msr_4 \fus_msr_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $536 + wire width 1 $631 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $537 + cell $and $632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$75 [4] + connect \A \wr__rel$91 [4] connect \B \fu_enable [3] - connect \Y $536 + connect \Y $631 end - process $group_249 + process $group_282 assign \wrpick_FAST_msr_i 1'0 - assign \wrpick_FAST_msr_i $536 + assign \wrpick_FAST_msr_i $631 sync init end - process $group_250 - assign \fast_data_i$193$next \fast_data_i$193 - assign \fast_data_i$193$next \fus_msr + process $group_283 + assign \fast_data_i$236$next \fast_data_i$236 + assign \fast_data_i$236$next \fus_msr attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \fast_data_i$193$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast_data_i$236$next 64'0000000000000000000000000000000000000000000000000000000000000000 end sync init - update \fast_data_i$193 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast_data_i$236 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk - update \fast_data_i$193 \fast_data_i$193$next + update \fast_data_i$236 \fast_data_i$236$next end end attribute \generator "nMigen" @@ -134482,58 +255103,173 @@ module \test_issuer attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 7 output 10 \oper_i__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 11 \oper_i__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 12 \oper_i__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 13 \oper_i__invert_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 2 output 14 \oper_i__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 15 \oper_i__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 16 \oper_i__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 17 \oper_i__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 18 \oper_i__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 19 \oper_i__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 4 output 20 \oper_i__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 21 \oper_i__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 1 output 22 \oper_i__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 7 output 10 \oper_i__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 11 \oper_i__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 12 \oper_i__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 13 \oper_i__invert_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 2 output 14 \oper_i__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 15 \oper_i__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 16 \oper_i__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 17 \oper_i__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 18 \oper_i__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 19 \oper_i__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 4 output 20 \oper_i__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 21 \oper_i__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 1 output 22 \oper_i__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 output 23 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 output 24 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" + wire width 1 output 25 \busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 4 output 26 \rd__rel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 5 output 27 \wr__rel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 64 output 28 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 6 output 29 \rd__go$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 output 30 \wr__go$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" + wire width 1 output 31 \issue_i$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" + wire width 1 input 32 \shadown_i$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 1 input 33 \go_die_i$5 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 7 output 34 \oper_i__insn_type$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 32 output 35 \oper_i__insn + attribute \enum_base_type "Function" + attribute \enum_value_0000000000 "NONE" + attribute \enum_value_0000000010 "ALU" + attribute \enum_value_0000000100 "LDST" + attribute \enum_value_0000001000 "SHIFT_ROT" + attribute \enum_value_0000010000 "LOGICAL" + attribute \enum_value_0000100000 "BRANCH" + attribute \enum_value_0001000000 "CR" + attribute \enum_value_0010000000 "TRAP" + attribute \enum_value_0100000000 "MUL" + attribute \enum_value_1000000000 "DIV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 10 output 36 \oper_i__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 1 output 37 \oper_i__read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 1 output 38 \oper_i__write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 23 \src1_i + wire width 64 output 39 \src1_i$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 24 \src2_i + wire width 64 output 40 \src2_i$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 25 \busy_o + wire width 1 output 41 \busy_o$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 26 \rd__rel + wire width 6 output 42 \rd__rel$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 27 \wr__rel + wire width 3 output 43 \wr__rel$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 28 \dest1_o + wire width 64 output 44 \dest1_o$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 29 \rd__go$1 + wire width 4 output 45 \rd__go$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 30 \wr__go$2 + wire width 3 output 46 \wr__go$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 31 \issue_i$3 + wire width 1 output 47 \issue_i$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 32 \shadown_i$4 + wire width 1 input 48 \shadown_i$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 33 \go_die_i$5 + wire width 1 input 49 \go_die_i$17 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -134606,10 +255342,8 @@ module \test_issuer attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 7 output 34 \oper_i__insn_type$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 32 output 35 \oper_i__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 7 output 50 \oper_i__insn_type$18 attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -134621,34 +255355,36 @@ module \test_issuer attribute \enum_value_0010000000 "TRAP" attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 output 36 \oper_i__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 1 output 37 \oper_i__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 1 output 38 \oper_i__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 10 output 51 \oper_i__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 1 output 52 \oper_i__lk$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 1 output 53 \oper_i__is_32bit$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 32 output 54 \oper_i__insn$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 39 \src1_i$7 + wire width 64 output 55 \src1_i$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 40 \src2_i$8 + wire width 64 output 56 \src2_i$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 41 \busy_o$9 + wire width 1 output 57 \busy_o$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 42 \rd__rel$10 + wire width 4 output 58 \rd__rel$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 43 \wr__rel$11 + wire width 3 output 59 \wr__rel$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 44 \dest1_o$12 + wire width 64 output 60 \dest1_o$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 45 \rd__go$13 + wire width 6 output 61 \rd__go$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 46 \wr__go$14 + wire width 5 output 62 \wr__go$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 47 \issue_i$15 + wire width 1 output 63 \issue_i$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 48 \shadown_i$16 + wire width 1 input 64 \shadown_i$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 49 \go_die_i$17 + wire width 1 input 65 \go_die_i$33 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -134721,8 +255457,10 @@ module \test_issuer attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 7 output 50 \oper_i__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 7 output 66 \oper_i__insn_type$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 32 output 67 \oper_i__insn$35 attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -134734,36 +255472,36 @@ module \test_issuer attribute \enum_value_0010000000 "TRAP" attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 output 51 \oper_i__fn_unit$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 output 52 \oper_i__lk$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 output 53 \oper_i__is_32bit$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 32 output 54 \oper_i__insn$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 10 output 68 \oper_i__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 1 output 69 \oper_i__is_32bit$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 4 output 70 \oper_i__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 13 output 71 \oper_i__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 55 \src1_i$23 + wire width 64 output 72 \src1_i$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 56 \src2_i$24 + wire width 64 output 73 \src2_i$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 57 \busy_o$25 + wire width 1 output 74 \busy_o$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 58 \rd__rel$26 + wire width 6 output 75 \rd__rel$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 59 \wr__rel$27 + wire width 5 output 76 \wr__rel$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 60 \dest1_o$28 + wire width 64 output 77 \dest1_o$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 61 \rd__go$29 + wire width 3 output 78 \rd__go$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 62 \wr__go$30 + wire width 5 output 79 \wr__go$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 63 \issue_i$31 + wire width 1 output 80 \issue_i$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 64 \shadown_i$32 + wire width 1 input 81 \shadown_i$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 65 \go_die_i$33 + wire width 1 input 82 \go_die_i$48 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -134836,10 +255574,8 @@ module \test_issuer attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 7 output 66 \oper_i__insn_type$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 32 output 67 \oper_i__insn$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 83 \oper_i__insn_type$49 attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -134851,36 +255587,50 @@ module \test_issuer attribute \enum_value_0010000000 "TRAP" attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 output 68 \oper_i__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 1 output 69 \oper_i__is_32bit$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 output 70 \oper_i__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 13 output 71 \oper_i__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 10 output 84 \oper_i__fn_unit$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 85 \oper_i__lk$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 86 \oper_i__invert_a$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 87 \oper_i__invert_out$53 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 88 \oper_i__input_carry$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 89 \oper_i__output_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 90 \oper_i__is_32bit$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 91 \oper_i__is_signed$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 92 \oper_i__data_len$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 72 \src1_i$38 + wire width 64 output 93 \src1_i$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 73 \src2_i$39 + wire width 64 output 94 \src2_i$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 74 \busy_o$40 + wire width 1 output 95 \busy_o$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 75 \rd__rel$41 + wire width 3 output 96 \rd__rel$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 76 \wr__rel$42 + wire width 5 output 97 \wr__rel$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 77 \dest1_o$43 + wire width 64 output 98 \dest1_o$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 78 \rd__go$44 + wire width 2 output 99 \rd__go$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 79 \wr__go$45 + wire width 3 output 100 \wr__go$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 80 \issue_i$46 + wire width 1 output 101 \issue_i$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 81 \shadown_i$47 + wire width 1 input 102 \shadown_i$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 82 \go_die_i$48 + wire width 1 input 103 \go_die_i$69 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -134954,7 +255704,7 @@ module \test_issuer attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 7 output 83 \oper_i__insn_type$49 + wire width 7 output 104 \oper_i__insn_type$70 attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -134967,49 +255717,49 @@ module \test_issuer attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 output 84 \oper_i__fn_unit$50 + wire width 10 output 105 \oper_i__fn_unit$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 85 \oper_i__lk$51 + wire width 1 output 106 \oper_i__lk$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 86 \oper_i__invert_a$52 + wire width 1 output 107 \oper_i__invert_a$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 87 \oper_i__invert_out$53 + wire width 1 output 108 \oper_i__invert_out$74 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 2 output 88 \oper_i__input_carry$54 + wire width 2 output 109 \oper_i__input_carry$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 89 \oper_i__output_carry$55 + wire width 1 output 110 \oper_i__output_carry$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 90 \oper_i__is_32bit$56 + wire width 1 output 111 \oper_i__is_32bit$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 91 \oper_i__is_signed$57 + wire width 1 output 112 \oper_i__is_signed$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 4 output 92 \oper_i__data_len$58 + wire width 4 output 113 \oper_i__data_len$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 93 \src1_i$59 + wire width 64 output 114 \src1_i$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 94 \src2_i$60 + wire width 64 output 115 \src2_i$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 95 \busy_o$61 + wire width 1 output 116 \busy_o$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 96 \rd__rel$62 + wire width 2 output 117 \rd__rel$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 97 \wr__rel$63 + wire width 3 output 118 \wr__rel$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 98 \dest1_o$64 + wire width 64 output 119 \dest1_o$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 99 \rd__go$65 + wire width 4 output 120 \rd__go$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 100 \wr__go$66 + wire width 3 output 121 \wr__go$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 101 \issue_i$67 + wire width 1 output 122 \issue_i$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 102 \shadown_i$68 + wire width 1 input 123 \shadown_i$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 103 \go_die_i$69 + wire width 1 input 124 \go_die_i$90 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -135083,49 +255833,49 @@ module \test_issuer attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 7 output 104 \oper_i__insn_type$70 + wire width 7 output 125 \oper_i__insn_type$91 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 2 output 105 \oper_i__input_carry$71 + wire width 2 output 126 \oper_i__input_carry$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 106 \oper_i__output_carry$72 + wire width 1 output 127 \oper_i__output_carry$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 107 \oper_i__input_cr$73 + wire width 1 output 128 \oper_i__input_cr$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 108 \oper_i__output_cr$74 + wire width 1 output 129 \oper_i__output_cr$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 109 \oper_i__is_32bit$75 + wire width 1 output 130 \oper_i__is_32bit$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 110 \oper_i__is_signed$76 + wire width 1 output 131 \oper_i__is_signed$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 111 \src1_i$77 + wire width 64 output 132 \src1_i$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 112 \src2_i$78 + wire width 64 output 133 \src2_i$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 113 \busy_o$79 + wire width 1 output 134 \busy_o$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 114 \rd__rel$80 + wire width 4 output 135 \rd__rel$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 115 \wr__rel$81 + wire width 3 output 136 \wr__rel$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 116 \dest1_o$82 + wire width 64 output 137 \dest1_o$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 117 \rd__go$83 + wire width 3 output 138 \rd__go$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 118 \ad__go + wire width 1 output 139 \ad__go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 119 \wr__go$84 + wire width 2 output 140 \wr__go$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 120 \st__go + wire width 1 output 141 \st__go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 121 \issue_i$85 + wire width 1 output 142 \issue_i$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 122 \shadown_i$86 + wire width 1 input 143 \shadown_i$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 123 \go_die_i$87 + wire width 1 input 144 \go_die_i$108 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -135199,55 +255949,55 @@ module \test_issuer attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 7 output 124 \oper_i__insn_type$88 + wire width 7 output 145 \oper_i__insn_type$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 125 \oper_i__is_32bit$89 + wire width 1 output 146 \oper_i__is_32bit$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 126 \oper_i__zero_a + wire width 1 output 147 \oper_i__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 127 \oper_i__is_signed$90 + wire width 1 output 148 \oper_i__is_signed$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 4 output 128 \oper_i__data_len$91 + wire width 4 output 149 \oper_i__data_len$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 129 \oper_i__byte_reverse$92 + wire width 1 output 150 \oper_i__byte_reverse$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 130 \oper_i__sign_extend$93 + wire width 1 output 151 \oper_i__sign_extend$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 131 \oper_i__update + wire width 1 output 152 \oper_i__update attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 132 \src1_i$94 + wire width 64 output 153 \src1_i$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 133 \src2_i$95 + wire width 64 output 154 \src2_i$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 134 \src3_i + wire width 64 output 155 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 135 \busy_o$96 + wire width 1 output 156 \busy_o$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 136 \rd__rel$97 + wire width 3 output 157 \rd__rel$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 137 \ad__rel + wire width 1 output 158 \ad__rel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 138 \st__rel + wire width 1 output 159 \st__rel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 139 \wr__rel$98 + wire width 2 output 160 \wr__rel$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 140 \o + wire width 64 output 161 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 input 141 \o_ok + wire width 1 input 162 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 142 \ea + wire width 64 output 163 \ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 input 143 \ea_ok + wire width 1 input 164 \ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112" - wire width 1 output 144 \load_mem_o + wire width 1 output 165 \load_mem_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" - wire width 1 output 145 \stwd_mem_o + wire width 1 output 166 \stwd_mem_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" - wire width 32 output 146 \raw_opcode_in + wire width 32 output 167 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:319" - wire width 1 output 147 \bigendian + wire width 1 output 168 \bigendian attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" - wire width 32 output 148 \opcode_in + wire width 32 output 169 \opcode_in attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -135260,7 +256010,7 @@ module \test_issuer attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 149 \function_unit + wire width 10 output 170 \function_unit attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -135268,7 +256018,7 @@ module \test_issuer attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 3 output 150 \in1_sel + wire width 3 output 171 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -135285,20 +256035,20 @@ module \test_issuer attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 4 output 151 \in2_sel + wire width 4 output 172 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 2 output 152 \in3_sel + wire width 2 output 173 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 153 \out_sel + wire width 2 output 174 \out_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -135308,7 +256058,7 @@ module \test_issuer attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 3 output 154 \cr_in + wire width 3 output 175 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -135316,7 +256066,7 @@ module \test_issuer attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 155 \cr_out + wire width 3 output 176 \cr_out attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -135324,13 +256074,13 @@ module \test_issuer attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 4 output 156 \ldst_len + wire width 4 output 177 \ldst_len attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 2 output 157 \rc_sel + wire width 2 output 178 \rc_sel attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -135404,7 +256154,7 @@ module \test_issuer attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 7 output 158 \internal_op + wire width 7 output 179 \internal_op attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -135436,33 +256186,33 @@ module \test_issuer attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 5 output 159 \form + wire width 5 output 180 \form attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123" - wire width 8 output 160 \asmcode + wire width 8 output 181 \asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 161 \inv_a + wire width 1 output 182 \inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 162 \inv_out + wire width 1 output 183 \inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 163 \cry_out + wire width 1 output 184 \cry_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 164 \br + wire width 1 output 185 \br attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 165 \sgn_ext + wire width 1 output 186 \sgn_ext attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 166 \upd + wire width 1 output 187 \upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 167 \rsrv + wire width 1 output 188 \rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 168 \is_32b + wire width 1 output 189 \is_32b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 169 \sgn + wire width 1 output 190 \sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 170 \lk + wire width 1 output 191 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 171 \sgl_pipe + wire width 1 output 192 \sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:32" - wire width 1 output 172 \valid + wire width 1 output 193 \valid attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -135536,7 +256286,7 @@ module \test_issuer attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33" - wire width 7 output 173 \insn_type + wire width 7 output 194 \insn_type attribute \enum_base_type "Function" attribute \enum_value_0000000000 "NONE" attribute \enum_value_0000000010 "ALU" @@ -135549,279 +256299,279 @@ module \test_issuer attribute \enum_value_0100000000 "MUL" attribute \enum_value_1000000000 "DIV" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34" - wire width 10 output 174 \fn_unit + wire width 10 output 195 \fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:36" - wire width 8 input 175 \asmcode$99 + wire width 8 input 196 \asmcode$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37" - wire width 64 output 176 \nia + wire width 64 output 197 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 177 \rego + wire width 5 output 198 \rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 178 \rego_ok + wire width 1 output 199 \rego_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 179 \ea$100 + wire width 5 output 200 \ea$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 180 \ea_ok$101 + wire width 1 output 201 \ea_ok$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 181 \reg1 + wire width 5 output 202 \reg1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 182 \reg1_ok + wire width 1 output 203 \reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 183 \reg2 + wire width 5 output 204 \reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 184 \reg2_ok + wire width 1 output 205 \reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 185 \reg3 + wire width 5 output 206 \reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 186 \reg3_ok + wire width 1 output 207 \reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 187 \imm + wire width 64 output 208 \imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 188 \imm_ok + wire width 1 output 209 \imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 10 output 189 \spro + wire width 10 output 210 \spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 190 \spro_ok + wire width 1 output 211 \spro_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 10 output 191 \spr1 + wire width 10 output 212 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 192 \spr1_ok + wire width 1 output 213 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 10 input 193 \spr2 + wire width 10 input 214 \spr2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 input 194 \spr2_ok + wire width 1 input 215 \spr2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 195 \fast1 + wire width 3 output 216 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 196 \fast1_ok + wire width 1 output 217 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 197 \fast2 + wire width 3 output 218 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 198 \fast2_ok + wire width 1 output 219 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 199 \fasto1 + wire width 3 output 220 \fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 200 \fasto1_ok + wire width 1 output 221 \fasto1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 201 \fasto2 + wire width 3 output 222 \fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 202 \fasto2_ok + wire width 1 output 223 \fasto2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 203 \cr_in1 + wire width 3 output 224 \cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 204 \cr_in1_ok + wire width 1 output 225 \cr_in1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 205 \cr_in2 + wire width 3 output 226 \cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 206 \cr_in2_ok + wire width 1 output 227 \cr_in2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 207 \cr_in2$102 + wire width 3 output 228 \cr_in2$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 208 \cr_in2_ok$103 + wire width 1 output 229 \cr_in2_ok$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 output 209 \read_cr_whole + wire width 1 output 230 \read_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 210 \cr_out$104 + wire width 3 output 231 \cr_out$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 211 \cr_out_ok + wire width 1 output 232 \cr_out_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire width 1 output 212 \write_cr_whole + wire width 1 output 233 \write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" - wire width 1 output 213 \lk$105 + wire width 1 output 234 \lk$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 214 \rc + wire width 1 output 235 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 215 \rc_ok + wire width 1 output 236 \rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 216 \oe + wire width 1 output 237 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 217 \oe_ok + wire width 1 output 238 \oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" - wire width 1 output 218 \invert_a + wire width 1 output 239 \invert_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63" - wire width 1 output 219 \zero_a + wire width 1 output 240 \zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64" - wire width 1 output 220 \invert_out + wire width 1 output 241 \invert_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65" - wire width 2 output 221 \input_carry + wire width 2 output 242 \input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66" - wire width 1 output 222 \output_carry + wire width 1 output 243 \output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67" - wire width 1 output 223 \input_cr + wire width 1 output 244 \input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68" - wire width 1 output 224 \output_cr + wire width 1 output 245 \output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69" - wire width 1 output 225 \is_32bit + wire width 1 output 246 \is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70" - wire width 1 output 226 \is_signed + wire width 1 output 247 \is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71" - wire width 32 output 227 \insn + wire width 32 output 248 \insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" - wire width 4 output 228 \data_len + wire width 4 output 249 \data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73" - wire width 1 output 229 \byte_reverse + wire width 1 output 250 \byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74" - wire width 1 output 230 \sign_extend + wire width 1 output 251 \sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:75" - wire width 1 output 231 \update + wire width 1 output 252 \update attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:76" - wire width 4 input 232 \traptype + wire width 4 input 253 \traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:77" - wire width 13 output 233 \trapaddr + wire width 13 output 254 \trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 output 234 \ldst_port0_is_ld_i + wire width 1 output 255 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 output 235 \ldst_port0_is_st_i + wire width 1 output 256 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 output 236 \ldst_port0_data_len + wire width 4 output 257 \ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 1 output 237 \ldst_port0_busy_o + wire width 1 output 258 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" - wire width 1 output 238 \ldst_port0_go_die_i + wire width 1 output 259 \ldst_port0_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 48 output 239 \ldst_port0_addr_i + wire width 48 output 260 \ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 240 \ldst_port0_addr_i_ok + wire width 1 output 261 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 output 241 \ldst_port0_addr_ok_o + wire width 1 output 262 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 input 242 \ldst_port0_addr_exc_o + wire width 1 input 263 \ldst_port0_addr_exc_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 243 \ldst_port0_ld_data_o + wire width 64 output 264 \ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 244 \ldst_port0_ld_data_o_ok + wire width 1 output 265 \ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 245 \ldst_port0_st_data_i + wire width 64 output 266 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 246 \ldst_port0_st_data_i_ok + wire width 1 output 267 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26" - wire width 48 output 247 \x_addr_i + wire width 48 output 268 \x_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27" - wire width 8 output 248 \x_mask_i + wire width 8 output 269 \x_mask_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28" - wire width 1 output 249 \x_ld_i + wire width 1 output 270 \x_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29" - wire width 1 output 250 \x_st_i + wire width 1 output 271 \x_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30" - wire width 64 output 251 \x_st_data_i + wire width 64 output 272 \x_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 input 252 \x_stall_i + wire width 1 input 273 \x_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33" - wire width 1 output 253 \x_valid_i + wire width 1 output 274 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36" - wire width 1 input 254 \m_stall_i + wire width 1 input 275 \m_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37" - wire width 1 output 255 \m_valid_i + wire width 1 output 276 \m_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42" - wire width 1 output 256 \x_busy_o + wire width 1 output 277 \x_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" - wire width 1 output 257 \m_busy_o + wire width 1 output 278 \m_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" - wire width 64 output 258 \m_ld_data_o + wire width 64 output 279 \m_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire width 1 output 259 \m_load_err_o + wire width 1 output 280 \m_load_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" - wire width 1 output 260 \m_store_err_o + wire width 1 output 281 \m_store_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" - wire width 45 output 261 \m_badaddr_o + wire width 45 output 282 \m_badaddr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 45 output 262 \dbus__adr + wire width 45 output 283 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 output 263 \dbus__dat_w + wire width 64 output 284 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 input 264 \dbus__dat_r + wire width 64 input 285 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 8 output 265 \dbus__sel + wire width 8 output 286 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 266 \dbus__cyc + wire width 1 output 287 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 267 \dbus__stb + wire width 1 output 288 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 268 \dbus__ack + wire width 1 input 289 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 269 \dbus__we + wire width 1 output 290 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 3 input 270 \dbus__cti + wire width 3 input 291 \dbus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 2 input 271 \dbus__bte + wire width 2 input 292 \dbus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 272 \dbus__err + wire width 1 input 293 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 output 273 \ldst_port0_is_ld_i$106 + wire width 1 output 294 \ldst_port0_is_ld_i$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 output 274 \ldst_port0_is_st_i$107 + wire width 1 output 295 \ldst_port0_is_st_i$128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 output 275 \ldst_port0_data_len$108 + wire width 4 output 296 \ldst_port0_data_len$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 1 output 276 \ldst_port0_busy_o$109 + wire width 1 output 297 \ldst_port0_busy_o$130 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" - wire width 1 input 277 \ldst_port0_go_die_i$110 + wire width 1 input 298 \ldst_port0_go_die_i$131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 96 output 278 \ldst_port0_addr_i$111 + wire width 96 output 299 \ldst_port0_addr_i$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 279 \ldst_port0_addr_i_ok$112 + wire width 1 output 300 \ldst_port0_addr_i_ok$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 output 280 \ldst_port0_addr_ok_o$113 + wire width 1 output 301 \ldst_port0_addr_ok_o$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 output 281 \ldst_port0_addr_exc_o$114 + wire width 1 output 302 \ldst_port0_addr_exc_o$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 282 \ldst_port0_ld_data_o$115 + wire width 64 output 303 \ldst_port0_ld_data_o$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 283 \ldst_port0_ld_data_o_ok$116 + wire width 1 output 304 \ldst_port0_ld_data_o_ok$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 284 \ldst_port0_st_data_i$117 + wire width 64 output 305 \ldst_port0_st_data_i$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 285 \ldst_port0_st_data_i_ok$118 + wire width 1 output 306 \ldst_port0_st_data_i_ok$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:21" - wire width 48 output 286 \a_pc_i + wire width 48 output 307 \a_pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:22" - wire width 1 input 287 \a_stall_i + wire width 1 input 308 \a_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:23" - wire width 1 output 288 \a_valid_i + wire width 1 output 309 \a_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 1 input 289 \f_stall_i + wire width 1 input 310 \f_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" - wire width 1 output 290 \f_valid_i + wire width 1 output 311 \f_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire width 1 output 291 \a_busy_o + wire width 1 output 312 \a_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:29" - wire width 1 output 292 \f_busy_o + wire width 1 output 313 \f_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:30" - wire width 64 output 293 \f_instr_o + wire width 64 output 314 \f_instr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" - wire width 1 output 294 \f_fetch_err_o + wire width 1 output 315 \f_fetch_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire width 45 output 295 \f_badaddr_o + wire width 45 output 316 \f_badaddr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 45 output 296 \ibus__adr + wire width 45 output 317 \ibus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 64 input 297 \ibus__dat_w + wire width 64 input 318 \ibus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 64 input 298 \ibus__dat_r + wire width 64 input 319 \ibus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 8 input 299 \ibus__sel + wire width 8 input 320 \ibus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 1 output 300 \ibus__cyc + wire width 1 output 321 \ibus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 1 output 301 \ibus__stb + wire width 1 output 322 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 1 input 302 \ibus__ack + wire width 1 input 323 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 1 input 303 \ibus__we + wire width 1 input 324 \ibus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 3 input 304 \ibus__cti + wire width 3 input 325 \ibus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 2 input 305 \ibus__bte + wire width 2 input 326 \ibus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 1 input 306 \ibus__err + wire width 1 input 327 \ibus__err attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" - wire width 1 input 307 \clk + wire width 1 input 328 \clk attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" - wire width 1 input 308 \rst + wire width 1 input 329 \rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 8 \core_d_rd1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -135859,7 +256609,7 @@ module \test_issuer connect \imm \imm connect \imm_ok \imm_ok connect \oper_i__lk \oper_i__lk - connect \lk \lk$105 + connect \lk \lk$126 connect \rc \rc connect \rc_ok \rc_ok connect \oe \oe @@ -135869,7 +256619,7 @@ module \test_issuer connect \zero_a \zero_a connect \oper_i__invert_out \oper_i__invert_out connect \invert_out \invert_out - connect \cr_out \cr_out$104 + connect \cr_out \cr_out$125 connect \cr_out_ok \cr_out_ok connect \oper_i__input_carry \oper_i__input_carry connect \input_carry \input_carry @@ -135905,7 +256655,7 @@ module \test_issuer connect \busy_o$4 \busy_o$9 connect \cr_in1_ok \cr_in1_ok connect \cr_in2_ok \cr_in2_ok - connect \cr_in2_ok$5 \cr_in2_ok$103 + connect \cr_in2_ok$5 \cr_in2_ok$124 connect \oper_i__insn_type$6 \oper_i__insn_type$18 connect \oper_i__fn_unit$7 \oper_i__fn_unit$19 connect \oper_i__lk$8 \oper_i__lk$20 @@ -135938,84 +256688,102 @@ module \test_issuer connect \issue_i$29 \issue_i$46 connect \busy_o$30 \busy_o$61 connect \oper_i__insn_type$31 \oper_i__insn_type$70 - connect \oper_i__input_carry$32 \oper_i__input_carry$71 - connect \oper_i__output_carry$33 \oper_i__output_carry$72 - connect \oper_i__input_cr$34 \oper_i__input_cr$73 - connect \oper_i__output_cr$35 \oper_i__output_cr$74 - connect \oper_i__is_32bit$36 \oper_i__is_32bit$75 - connect \oper_i__is_signed$37 \oper_i__is_signed$76 - connect \issue_i$38 \issue_i$67 - connect \busy_o$39 \busy_o$79 + connect \oper_i__fn_unit$32 \oper_i__fn_unit$71 + connect \oper_i__lk$33 \oper_i__lk$72 + connect \oper_i__invert_a$34 \oper_i__invert_a$73 + connect \oper_i__input_carry$35 \oper_i__input_carry$75 + connect \oper_i__invert_out$36 \oper_i__invert_out$74 + connect \oper_i__output_carry$37 \oper_i__output_carry$76 + connect \oper_i__is_32bit$38 \oper_i__is_32bit$77 + connect \oper_i__is_signed$39 \oper_i__is_signed$78 + connect \oper_i__data_len$40 \oper_i__data_len$79 + connect \issue_i$41 \issue_i$67 + connect \busy_o$42 \busy_o$82 + connect \oper_i__insn_type$43 \oper_i__insn_type$91 + connect \oper_i__input_carry$44 \oper_i__input_carry$92 + connect \oper_i__output_carry$45 \oper_i__output_carry$93 + connect \oper_i__input_cr$46 \oper_i__input_cr$94 + connect \oper_i__output_cr$47 \oper_i__output_cr$95 + connect \oper_i__is_32bit$48 \oper_i__is_32bit$96 + connect \oper_i__is_signed$49 \oper_i__is_signed$97 + connect \issue_i$50 \issue_i$88 + connect \busy_o$51 \busy_o$100 connect \reg3_ok \reg3_ok - connect \oper_i__insn_type$40 \oper_i__insn_type$88 + connect \oper_i__insn_type$52 \oper_i__insn_type$109 connect \oper_i__zero_a \oper_i__zero_a - connect \oper_i__is_32bit$41 \oper_i__is_32bit$89 - connect \oper_i__is_signed$42 \oper_i__is_signed$90 - connect \oper_i__data_len$43 \oper_i__data_len$91 - connect \oper_i__byte_reverse$44 \oper_i__byte_reverse$92 - connect \oper_i__sign_extend$45 \oper_i__sign_extend$93 + connect \oper_i__is_32bit$53 \oper_i__is_32bit$110 + connect \oper_i__is_signed$54 \oper_i__is_signed$111 + connect \oper_i__data_len$55 \oper_i__data_len$112 + connect \oper_i__byte_reverse$56 \oper_i__byte_reverse$113 + connect \oper_i__sign_extend$57 \oper_i__sign_extend$114 connect \oper_i__update \oper_i__update connect \update \update - connect \issue_i$46 \issue_i$85 - connect \busy_o$47 \busy_o$96 + connect \issue_i$58 \issue_i$106 + connect \busy_o$59 \busy_o$117 connect \reg1 \reg1 connect \rd__rel \rd__rel connect \rd__go \rd__go connect \src1_i \src1_i - connect \rd__rel$48 \rd__rel$10 - connect \rd__go$49 \rd__go$1 - connect \src1_i$50 \src1_i$7 - connect \rd__rel$51 \rd__rel$41 - connect \rd__go$52 \rd__go$29 - connect \src1_i$53 \src1_i$38 - connect \rd__rel$54 \rd__rel$62 - connect \rd__go$55 \rd__go$44 - connect \src1_i$56 \src1_i$59 - connect \rd__rel$57 \rd__rel$80 - connect \rd__go$58 \rd__go$65 - connect \src1_i$59 \src1_i$77 - connect \rd__rel$60 \rd__rel$97 - connect \rd__go$61 \rd__go$83 - connect \src1_i$62 \src1_i$94 + connect \rd__rel$60 \rd__rel$10 + connect \rd__go$61 \rd__go$1 + connect \src1_i$62 \src1_i$7 + connect \rd__rel$63 \rd__rel$41 + connect \rd__go$64 \rd__go$29 + connect \src1_i$65 \src1_i$38 + connect \rd__rel$66 \rd__rel$62 + connect \rd__go$67 \rd__go$44 + connect \src1_i$68 \src1_i$59 + connect \rd__rel$69 \rd__rel$83 + connect \rd__go$70 \rd__go$65 + connect \src1_i$71 \src1_i$80 + connect \rd__rel$72 \rd__rel$101 + connect \rd__go$73 \rd__go$86 + connect \src1_i$74 \src1_i$98 + connect \rd__rel$75 \rd__rel$118 + connect \rd__go$76 \rd__go$104 + connect \src1_i$77 \src1_i$115 connect \reg2 \reg2 connect \src2_i \src2_i - connect \src2_i$63 \src2_i$8 - connect \src2_i$64 \src2_i$39 - connect \src2_i$65 \src2_i$60 - connect \src2_i$66 \src2_i$78 - connect \src2_i$67 \src2_i$95 + connect \src2_i$78 \src2_i$8 + connect \src2_i$79 \src2_i$39 + connect \src2_i$80 \src2_i$60 + connect \src2_i$81 \src2_i$81 + connect \src2_i$82 \src2_i$99 + connect \src2_i$83 \src2_i$116 connect \reg3 \reg3 connect \src3_i \src3_i connect \cr_in1 \cr_in1 - connect \rd__rel$68 \rd__rel$26 - connect \rd__go$69 \rd__go$13 + connect \rd__rel$84 \rd__rel$26 + connect \rd__go$85 \rd__go$13 connect \cr_in2 \cr_in2 - connect \cr_in2$70 \cr_in2$102 + connect \cr_in2$86 \cr_in2$123 connect \fast1 \fast1 - connect \src1_i$71 \src1_i$23 + connect \src1_i$87 \src1_i$23 connect \fast2 \fast2 - connect \src2_i$72 \src2_i$24 + connect \src2_i$88 \src2_i$24 connect \rego \rego connect \wr__rel \wr__rel connect \wr__go \wr__go - connect \wr__rel$73 \wr__rel$11 - connect \wr__go$74 \wr__go$2 - connect \wr__rel$75 \wr__rel$42 - connect \wr__go$76 \wr__go$30 - connect \wr__rel$77 \wr__rel$63 - connect \wr__go$78 \wr__go$45 - connect \wr__rel$79 \wr__rel$81 - connect \wr__go$80 \wr__go$66 + connect \wr__rel$89 \wr__rel$11 + connect \wr__go$90 \wr__go$2 + connect \wr__rel$91 \wr__rel$42 + connect \wr__go$92 \wr__go$30 + connect \wr__rel$93 \wr__rel$63 + connect \wr__go$94 \wr__go$45 + connect \wr__rel$95 \wr__rel$84 + connect \wr__go$96 \wr__go$66 + connect \wr__rel$97 \wr__rel$102 + connect \wr__go$98 \wr__go$87 connect \o_ok \o_ok - connect \wr__rel$81 \wr__rel$98 - connect \wr__go$82 \wr__go$84 + connect \wr__rel$99 \wr__rel$119 + connect \wr__go$100 \wr__go$105 connect \o \o - connect \ea \ea$100 + connect \ea \ea$121 connect \ea_ok \ea_ok - connect \ea$83 \ea + connect \ea$101 \ea connect \fasto1 \fasto1 - connect \wr__rel$84 \wr__rel$27 - connect \wr__go$85 \wr__go$14 + connect \wr__rel$102 \wr__rel$27 + connect \wr__go$103 \wr__go$14 connect \fasto2 \fasto2 connect \opcode_in \opcode_in connect \in1_sel \in1_sel @@ -136024,12 +256792,12 @@ module \test_issuer connect \out_sel \out_sel connect \rc_sel \rc_sel connect \cr_in \cr_in - connect \cr_out$86 \cr_out + connect \cr_out$104 \cr_out connect \nia \nia connect \function_unit \function_unit connect \internal_op \internal_op connect \rego_ok \rego_ok - connect \ea_ok$87 \ea_ok$101 + connect \ea_ok$105 \ea_ok$122 connect \spr1 \spr1 connect \spr1_ok \spr1_ok connect \spro \spro @@ -136042,7 +256810,7 @@ module \test_issuer connect \cry_out \cry_out connect \is_32b \is_32b connect \sgn \sgn - connect \lk$88 \lk + connect \lk$106 \lk connect \br \br connect \sgn_ext \sgn_ext connect \upd \upd @@ -136053,60 +256821,63 @@ module \test_issuer connect \go_die_i \go_die_i connect \shadown_i \shadown_i connect \dest1_o \dest1_o - connect \go_die_i$89 \go_die_i$5 - connect \shadown_i$90 \shadown_i$4 - connect \dest1_o$91 \dest1_o$12 - connect \go_die_i$92 \go_die_i$17 - connect \shadown_i$93 \shadown_i$16 - connect \dest1_o$94 \dest1_o$28 - connect \go_die_i$95 \go_die_i$33 - connect \shadown_i$96 \shadown_i$32 - connect \dest1_o$97 \dest1_o$43 - connect \go_die_i$98 \go_die_i$48 - connect \shadown_i$99 \shadown_i$47 - connect \dest1_o$100 \dest1_o$64 - connect \go_die_i$101 \go_die_i$69 - connect \shadown_i$102 \shadown_i$68 - connect \dest1_o$103 \dest1_o$82 - connect \go_die_i$104 \go_die_i$87 + connect \go_die_i$107 \go_die_i$5 + connect \shadown_i$108 \shadown_i$4 + connect \dest1_o$109 \dest1_o$12 + connect \go_die_i$110 \go_die_i$17 + connect \shadown_i$111 \shadown_i$16 + connect \dest1_o$112 \dest1_o$28 + connect \go_die_i$113 \go_die_i$33 + connect \shadown_i$114 \shadown_i$32 + connect \dest1_o$115 \dest1_o$43 + connect \go_die_i$116 \go_die_i$48 + connect \shadown_i$117 \shadown_i$47 + connect \dest1_o$118 \dest1_o$64 + connect \go_die_i$119 \go_die_i$69 + connect \shadown_i$120 \shadown_i$68 + connect \dest1_o$121 \dest1_o$85 + connect \go_die_i$122 \go_die_i$90 + connect \shadown_i$123 \shadown_i$89 + connect \dest1_o$124 \dest1_o$103 + connect \go_die_i$125 \go_die_i$108 connect \load_mem_o \load_mem_o connect \stwd_mem_o \stwd_mem_o - connect \shadown_i$105 \shadown_i$86 - connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i$106 - connect \ldst_port0_is_st_i \ldst_port0_is_st_i$107 - connect \ldst_port0_data_len \ldst_port0_data_len$108 - connect \ldst_port0_addr_i \ldst_port0_addr_i$111 - connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$112 - connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$114 - connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$113 - connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o$115 - connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok$116 - connect \ldst_port0_st_data_i \ldst_port0_st_data_i$117 - connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok$118 - connect \ldst_port0_is_ld_i$106 \ldst_port0_is_ld_i + connect \shadown_i$126 \shadown_i$107 + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i$127 + connect \ldst_port0_is_st_i \ldst_port0_is_st_i$128 + connect \ldst_port0_data_len \ldst_port0_data_len$129 + connect \ldst_port0_addr_i \ldst_port0_addr_i$132 + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$133 + connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$135 + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$134 + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o$136 + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok$137 + connect \ldst_port0_st_data_i \ldst_port0_st_data_i$138 + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok$139 + connect \ldst_port0_is_ld_i$127 \ldst_port0_is_ld_i connect \ldst_port0_busy_o \ldst_port0_busy_o - connect \ldst_port0_is_st_i$107 \ldst_port0_is_st_i - connect \ldst_port0_data_len$108 \ldst_port0_data_len - connect \ldst_port0_addr_i$109 \ldst_port0_addr_i - connect \ldst_port0_addr_i_ok$110 \ldst_port0_addr_i_ok + connect \ldst_port0_is_st_i$128 \ldst_port0_is_st_i + connect \ldst_port0_data_len$129 \ldst_port0_data_len + connect \ldst_port0_addr_i$130 \ldst_port0_addr_i + connect \ldst_port0_addr_i_ok$131 \ldst_port0_addr_i_ok connect \x_mask_i \x_mask_i connect \x_addr_i \x_addr_i - connect \ldst_port0_addr_ok_o$111 \ldst_port0_addr_ok_o + connect \ldst_port0_addr_ok_o$132 \ldst_port0_addr_ok_o connect \m_ld_data_o \m_ld_data_o - connect \ldst_port0_ld_data_o$112 \ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok$113 \ldst_port0_ld_data_o_ok + connect \ldst_port0_ld_data_o$133 \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok$134 \ldst_port0_ld_data_o_ok connect \x_busy_o \x_busy_o - connect \ldst_port0_st_data_i_ok$114 \ldst_port0_st_data_i_ok - connect \ldst_port0_st_data_i$115 \ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok$135 \ldst_port0_st_data_i_ok + connect \ldst_port0_st_data_i$136 \ldst_port0_st_data_i connect \x_st_data_i \x_st_data_i - connect \ldst_port0_addr_exc_o$116 \ldst_port0_addr_exc_o + connect \ldst_port0_addr_exc_o$137 \ldst_port0_addr_exc_o connect \x_ld_i \x_ld_i connect \x_st_i \x_st_i connect \m_valid_i \m_valid_i connect \x_valid_i \x_valid_i connect \ldst_port0_go_die_i \ldst_port0_go_die_i - connect \ldst_port0_go_die_i$117 \ldst_port0_go_die_i$110 - connect \ldst_port0_busy_o$118 \ldst_port0_busy_o$109 + connect \ldst_port0_go_die_i$138 \ldst_port0_go_die_i$131 + connect \ldst_port0_busy_o$139 \ldst_port0_busy_o$130 connect \dbus__cyc \dbus__cyc connect \x_stall_i \x_stall_i connect \dbus__ack \dbus__ack @@ -136163,13 +256934,13 @@ module \test_issuer sync init end attribute \src "simple/issuer.py:79" - wire width 64 \nia$119 + wire width 64 \nia$140 attribute \src "simple/issuer.py:80" - wire width 65 $120 + wire width 65 $141 attribute \src "simple/issuer.py:80" - wire width 65 $121 + wire width 65 $142 attribute \src "simple/issuer.py:80" - cell $add $122 + cell $add $143 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -136177,12 +256948,12 @@ module \test_issuer parameter \Y_WIDTH 65 connect \A \current_pc connect \B 3'100 - connect \Y $121 + connect \Y $142 end - connect $120 $121 + connect $141 $142 process $group_3 - assign \nia$119 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia$119 $120 [63:0] + assign \nia$140 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \nia$140 $141 [63:0] sync init end attribute \src "simple/issuer.py:74" @@ -136194,14 +256965,14 @@ module \test_issuer attribute \src "simple/issuer.py:90" wire width 2 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $123 + wire width 1 $144 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $124 + cell $reduce_bool $145 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \core_fast_nia_wen - connect \Y $123 + connect \Y $144 end process $group_4 assign \pc_changed$next \pc_changed @@ -136218,7 +256989,7 @@ module \test_issuer attribute \nmigen.decoding "INSN_ACTIVE/2" case 2'10 attribute \src "simple/issuer.py:136" - switch { $123 } + switch { $144 } attribute \src "simple/issuer.py:136" case 1'1 assign \pc_changed$next 1'1 @@ -136235,9 +257006,9 @@ module \test_issuer update \pc_changed \pc_changed$next end attribute \src "simple/issuer.py:97" - wire width 64 \pc$125 + wire width 64 \pc$146 process $group_5 - assign \pc$125 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pc$146 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "simple/issuer.py:90" switch \fsm_state attribute \src "simple/issuer.py:93" @@ -136251,10 +257022,10 @@ module \test_issuer switch { \pc_ok } attribute \src "simple/issuer.py:98" case 1'1 - assign \pc$125 \pc + assign \pc$146 \pc attribute \src "simple/issuer.py:101" case - assign \pc$125 \core_d_rd1__data_o + assign \pc$146 \core_d_rd1__data_o end end attribute \src "simple/issuer.py:115" @@ -136306,7 +257077,7 @@ module \test_issuer switch { \go_insn_i } attribute \src "simple/issuer.py:95" case 1'1 - assign \a_pc_i \pc$125 [47:0] + assign \a_pc_i \pc$146 [47:0] end attribute \src "simple/issuer.py:115" attribute \nmigen.decoding "INSN_READ/1" @@ -136388,7 +257159,7 @@ module \test_issuer switch { \go_insn_i } attribute \src "simple/issuer.py:95" case 1'1 - assign \current_pc$next \pc$125 + assign \current_pc$next \pc$146 end attribute \src "simple/issuer.py:115" attribute \nmigen.decoding "INSN_READ/1" @@ -136408,14 +257179,14 @@ module \test_issuer update \current_pc \current_pc$next end attribute \src "simple/issuer.py:138" - wire width 1 $126 + wire width 1 $147 attribute \src "simple/issuer.py:138" - cell $not $127 + cell $not $148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $126 + connect \Y $147 end process $group_11 assign \fsm_state$next \fsm_state @@ -136445,7 +257216,7 @@ module \test_issuer attribute \nmigen.decoding "INSN_ACTIVE/2" case 2'10 attribute \src "simple/issuer.py:138" - switch { $126 } + switch { $147 } attribute \src "simple/issuer.py:138" case 1'1 assign \fsm_state$next 2'00 @@ -136464,11 +257235,11 @@ module \test_issuer attribute \src "simple/issuer.py:72" wire width 32 \current_insn attribute \src "simple/issuer.py:122" - wire width 32 $128 + wire width 32 $149 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 $129 + wire width 7 $150 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $130 + cell $mul $151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -136476,18 +257247,18 @@ module \test_issuer parameter \Y_WIDTH 7 connect \A \current_pc [2] connect \B 6'100000 - connect \Y $129 + connect \Y $150 end attribute \src "simple/issuer.py:122" - cell $shift $131 + cell $shift $152 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 32 connect \A \f_instr_o - connect \B $129 - connect \Y $128 + connect \B $150 + connect \Y $149 end process $group_12 assign \current_insn 32'00000000000000000000000000000000 @@ -136505,7 +257276,7 @@ module \test_issuer case 1'1 attribute \src "simple/issuer.py:120" case - assign \current_insn $128 + assign \current_insn $149 end attribute \src "simple/issuer.py:132" attribute \nmigen.decoding "INSN_ACTIVE/2" @@ -136648,24 +257419,24 @@ module \test_issuer update \ilatch \ilatch$next end attribute \src "simple/issuer.py:138" - wire width 1 $132 + wire width 1 $153 attribute \src "simple/issuer.py:138" - cell $not $133 + cell $not $154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $132 + connect \Y $153 end attribute \src "simple/issuer.py:144" - wire width 1 $134 + wire width 1 $155 attribute \src "simple/issuer.py:144" - cell $not $135 + cell $not $156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_changed - connect \Y $134 + connect \Y $155 end process $group_18 assign \core_wen 8'00000000 @@ -136681,11 +257452,11 @@ module \test_issuer attribute \nmigen.decoding "INSN_ACTIVE/2" case 2'10 attribute \src "simple/issuer.py:138" - switch { $132 } + switch { $153 } attribute \src "simple/issuer.py:138" case 1'1 attribute \src "simple/issuer.py:144" - switch { $134 } + switch { $155 } attribute \src "simple/issuer.py:144" case 1'1 assign \core_wen 8'00000001 @@ -136695,24 +257466,24 @@ module \test_issuer sync init end attribute \src "simple/issuer.py:138" - wire width 1 $136 + wire width 1 $157 attribute \src "simple/issuer.py:138" - cell $not $137 + cell $not $158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $136 + connect \Y $157 end attribute \src "simple/issuer.py:144" - wire width 1 $138 + wire width 1 $159 attribute \src "simple/issuer.py:144" - cell $not $139 + cell $not $160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_changed - connect \Y $138 + connect \Y $159 end process $group_19 assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -136728,14 +257499,14 @@ module \test_issuer attribute \nmigen.decoding "INSN_ACTIVE/2" case 2'10 attribute \src "simple/issuer.py:138" - switch { $136 } + switch { $157 } attribute \src "simple/issuer.py:138" case 1'1 attribute \src "simple/issuer.py:144" - switch { $138 } + switch { $159 } attribute \src "simple/issuer.py:144" case 1'1 - assign \core_data_i \nia$119 + assign \core_data_i \nia$140 end end end