From: lkcl <lkcl@web>
Date: Thu, 24 Dec 2020 21:25:27 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~938
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9727477aac9160f410a3b03d69d8f34a5a162cc4;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 7e42665fa..029c86d8d 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -51,7 +51,7 @@ All of this is *without modifying the OpenPOWER v3.0B ISA*, except to add "wrapp
 In fairness to both VSX and RVV, there are things that are not provided by SimpleV:
 
 * 128 bit or above arithmetic and other operations
-  (VSX Rijndael and SHA primitives; VSX shuffle operations)
+  (VSX Rijndael and SHA primitives; VSX shuffle and bitpermute operations)
 * register files above 128
 * Vector lengths over 64
 * Unit-strided LD/ST and other comprehensive memory operations