From: Gabe Black Date: Thu, 2 May 2019 22:33:32 +0000 (-0700) Subject: arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code. X-Git-Tag: v19.0.0.0~838 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=972c38b1cc5f6f6c649a0e9923695447bc5d6255;p=gem5.git arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code. This code will be preserved through version control, but otherwise creates clutter and will rot in place since it's never compiled. Change-Id: Id265f6deac445116843956ea5cf1210d8127274e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608 Reviewed-by: Jason Lowe-Power Reviewed-by: Brandon Potter Maintainer: Jason Lowe-Power Tested-by: kokoro --- diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc index 33e760fe5..950b773aa 100644 --- a/src/arch/alpha/linux/system.cc +++ b/src/arch/alpha/linux/system.cc @@ -123,10 +123,6 @@ LinuxAlphaSystem::setupFuncEvents() #ifndef NDEBUG kernelPanicEvent = addKernelFuncEventOrPanic("panic"); -#if 0 - kernelDieEvent = addKernelFuncEventOrPanic("die_if_kernel"); -#endif - #endif /** diff --git a/src/arch/alpha/linux/system.hh b/src/arch/alpha/linux/system.hh index 4f030c99f..8ea387e74 100644 --- a/src/arch/alpha/linux/system.hh +++ b/src/arch/alpha/linux/system.hh @@ -89,11 +89,6 @@ class LinuxAlphaSystem : public AlphaSystem /** Event to halt the simulator if the kernel calls panic() */ BreakPCEvent *kernelPanicEvent; -#if 0 - /** Event to halt the simulator if the kernel calls die_if_kernel */ - BreakPCEvent *kernelDieEvent; -#endif - #endif /** diff --git a/src/arch/alpha/osfpal.cc b/src/arch/alpha/osfpal.cc index 58a3d31eb..741189f89 100644 --- a/src/arch/alpha/osfpal.cc +++ b/src/arch/alpha/osfpal.cc @@ -229,72 +229,6 @@ PAL::name(int index) 0, // 0xbd "nphalt", // 0xbe "copypal", // 0xbf -#if 0 - 0, // 0xc0 - 0, // 0xc1 - 0, // 0xc2 - 0, // 0xc3 - 0, // 0xc4 - 0, // 0xc5 - 0, // 0xc6 - 0, // 0xc7 - 0, // 0xc8 - 0, // 0xc9 - 0, // 0xca - 0, // 0xcb - 0, // 0xcc - 0, // 0xcd - 0, // 0xce - 0, // 0xcf - 0, // 0xd0 - 0, // 0xd1 - 0, // 0xd2 - 0, // 0xd3 - 0, // 0xd4 - 0, // 0xd5 - 0, // 0xd6 - 0, // 0xd7 - 0, // 0xd8 - 0, // 0xd9 - 0, // 0xda - 0, // 0xdb - 0, // 0xdc - 0, // 0xdd - 0, // 0xde - 0, // 0xdf - 0, // 0xe0 - 0, // 0xe1 - 0, // 0xe2 - 0, // 0xe3 - 0, // 0xe4 - 0, // 0xe5 - 0, // 0xe6 - 0, // 0xe7 - 0, // 0xe8 - 0, // 0xe9 - 0, // 0xea - 0, // 0xeb - 0, // 0xec - 0, // 0xed - 0, // 0xee - 0, // 0xef - 0, // 0xf0 - 0, // 0xf1 - 0, // 0xf2 - 0, // 0xf3 - 0, // 0xf4 - 0, // 0xf5 - 0, // 0xf6 - 0, // 0xf7 - 0, // 0xf8 - 0, // 0xf9 - 0, // 0xfa - 0, // 0xfb - 0, // 0xfc - 0, // 0xfd - 0, // 0xfe - 0 // 0xff -#endif }; if (index > NumCodes || index < 0) diff --git a/src/base/loader/coff_sym.h b/src/base/loader/coff_sym.h index be0631141..acca2f159 100644 --- a/src/base/loader/coff_sym.h +++ b/src/base/loader/coff_sym.h @@ -215,32 +215,6 @@ typedef struct pdr { #define pdNil ((pPDR) 0) #define ipdNil -1 -/* - * The structure of the runtime procedure descriptor created by the loader - * for use by the static exception system. - */ -/* - * If 0'd out because exception_info chokes Visual C++ and because there - * don't seem to be any references to this structure elsewhere in gdb. - */ -#if 0 -typedef struct runtime_pdr { - coff_addr adr; /* memory address of start of procedure */ - coff_uint regmask; /* save register mask */ - coff_int regoffset; /* save register offset */ - coff_uint fregmask; /* save floating point register mask */ - coff_int fregoffset; /* save floating point register offset */ - coff_int frameoffset; /* frame size */ - coff_ushort framereg; /* frame pointer register */ - coff_ushort pcreg; /* offset or reg of return pc */ - coff_int irpss; /* index into the runtime string table */ - coff_uint reserved; - struct exception_info *exception_info;/* pointer to exception array */ -} RPDR, *pRPDR; -#define cbRPDR sizeof(RPDR) -#define rpdNil ((pRPDR) 0) -#endif - /* * Line Numbers * diff --git a/src/base/statistics.hh b/src/base/statistics.hh index 8a5420f05..69a2afffc 100644 --- a/src/base/statistics.hh +++ b/src/base/statistics.hh @@ -1294,12 +1294,6 @@ class Vector2dBase : public DataWrapVec2d zero() const { return data(0)->zero(); -#if 0 - for (off_type i = 0; i < size(); ++i) - if (!data(i)->zero()) - return false; - return true; -#endif } /** diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 50de81b2a..f2e0f60b7 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -351,11 +351,6 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) commit.setROB(&rob); lastActivatedCycle = 0; -#if 0 - // Give renameMap & rename stage access to the freeList; - for (ThreadID tid = 0; tid < numThreads; tid++) - globalSeqNum[tid] = 1; -#endif DPRINTF(O3CPU, "Creating O3CPU object.\n"); diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 8ef3b6ac1..f0a97e429 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1587,12 +1587,6 @@ template ThreadID DefaultFetch::branchCount() { -#if 0 - list::iterator thread = activeThreads->begin(); - assert(thread != activeThreads->end()); - ThreadID tid = *thread; -#endif - panic("Branch Count Fetch policy unimplemented\n"); return InvalidThreadID; } diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index 4a5262fd6..20b41e51d 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -1481,36 +1481,7 @@ template int InstructionQueue::countInsts() { -#if 0 - //ksewell:This works but definitely could use a cleaner write - //with a more intuitive way of counting. Right now it's - //just brute force .... - // Change the #if if you want to use this method. - int total_insts = 0; - - for (ThreadID tid = 0; tid < numThreads; ++tid) { - ListIt count_it = instList[tid].begin(); - - while (count_it != instList[tid].end()) { - if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { - if (!(*count_it)->isIssued()) { - ++total_insts; - } else if ((*count_it)->isMemRef() && - !(*count_it)->memOpDone) { - // Loads that have not been marked as executed still count - // towards the total instructions. - ++total_insts; - } - } - - ++count_it; - } - } - - return total_insts; -#else return numEntries - freeEntries; -#endif } template diff --git a/src/cpu/pred/2bit_local.cc b/src/cpu/pred/2bit_local.cc index e61c1e3f6..79fb2a588 100644 --- a/src/cpu/pred/2bit_local.cc +++ b/src/cpu/pred/2bit_local.cc @@ -86,17 +86,6 @@ LocalBP::lookup(ThreadID tid, Addr branch_addr, void * &bp_history) taken = getPrediction(counter_val); -#if 0 - // Speculative update. - if (taken) { - DPRINTF(Fetch, "Branch updated as taken.\n"); - localCtrs[local_predictor_idx]++; - } else { - DPRINTF(Fetch, "Branch updated as not taken.\n"); - localCtrs[local_predictor_idx]--; - } -#endif - return taken; } diff --git a/src/dev/alpha/tsunami_pchip.cc b/src/dev/alpha/tsunami_pchip.cc index d8f9fd1d3..bf172209a 100644 --- a/src/dev/alpha/tsunami_pchip.cc +++ b/src/dev/alpha/tsunami_pchip.cc @@ -264,23 +264,6 @@ TsunamiPChip::dmaAddr(const PciBusAddr &dev, Addr busAddr) const Addr pteAddr; Addr dmaAddr; -#if 0 - DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr); - for (int i = 0; i < 4; i++) { - DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n", - i, wsba[i], wsm[i]); - - windowBase = wsba[i]; - windowMask = ~wsm[i] & (ULL(0xfff) << 20); - - if ((busAddr & windowMask) == (windowBase & windowMask)) { - DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n", - i, windowBase, windowMask, (busAddr & windowMask), - (windowBase & windowMask)); - } - } -#endif - for (int i = 0; i < 4; i++) { windowBase = wsba[i]; diff --git a/src/dev/net/ns_gige.cc b/src/dev/net/ns_gige.cc index 29e886717..e180e7c8e 100644 --- a/src/dev/net/ns_gige.cc +++ b/src/dev/net/ns_gige.cc @@ -485,41 +485,6 @@ NSGigE::write(PacketPtr pkt) CFGR_PCI64_DET); } -// all these #if 0's are because i don't THINK the kernel needs to -// have these implemented. if there is a problem relating to one of -// these, you may need to add functionality in. - -// grouped together and #if 0'ed to avoid empty if body and make clang happy -#if 0 - if (reg & CFGR_TBI_EN) ; - if (reg & CFGR_MODE_1000) ; - - if (reg & CFGR_PINT_DUPSTS || - reg & CFGR_PINT_LNKSTS || - reg & CFGR_PINT_SPDSTS) - ; - - if (reg & CFGR_TMRTEST) ; - if (reg & CFGR_MRM_DIS) ; - if (reg & CFGR_MWI_DIS) ; - - if (reg & CFGR_DATA64_EN) ; - if (reg & CFGR_M64ADDR) ; - if (reg & CFGR_PHY_RST) ; - if (reg & CFGR_PHY_DIS) ; - - if (reg & CFGR_REQALG) ; - if (reg & CFGR_SB) ; - if (reg & CFGR_POW) ; - if (reg & CFGR_EXD) ; - if (reg & CFGR_PESEL) ; - if (reg & CFGR_BROM_DIS) ; - if (reg & CFGR_EXT_125) ; - if (reg & CFGR_BEM) ; - - if (reg & CFGR_T64ADDR) ; - // panic("CFGR_T64ADDR is read only register!\n"); -#endif if (reg & CFGR_AUTO_1000) panic("CFGR_AUTO_1000 not implemented!\n"); @@ -553,13 +518,6 @@ NSGigE::write(PacketPtr pkt) eepromClk = reg & MEAR_EECLK; // since phy is completely faked, MEAR_MD* don't matter - -// grouped together and #if 0'ed to avoid empty if body and make clang happy -#if 0 - if (reg & MEAR_MDIO) ; - if (reg & MEAR_MDDIR) ; - if (reg & MEAR_MDC) ; -#endif break; case PTSCR: @@ -603,26 +561,6 @@ NSGigE::write(PacketPtr pkt) case TX_CFG: regs.txcfg = reg; -#if 0 - if (reg & TX_CFG_CSI) ; - if (reg & TX_CFG_HBI) ; - if (reg & TX_CFG_MLB) ; - if (reg & TX_CFG_ATP) ; - if (reg & TX_CFG_ECRETRY) { - /* - * this could easily be implemented, but considering - * the network is just a fake pipe, wouldn't make - * sense to do this - */ - } - - if (reg & TX_CFG_BRST_DIS) ; -#endif - -#if 0 - /* we handle our own DMA, ignore the kernel's exhortations */ - if (reg & TX_CFG_MXDMA) ; -#endif // also, we currently don't care about fill/drain // thresholds though this may change in the future with @@ -651,22 +589,6 @@ NSGigE::write(PacketPtr pkt) case RX_CFG: regs.rxcfg = reg; -#if 0 - if (reg & RX_CFG_AEP) ; - if (reg & RX_CFG_ARP) ; - if (reg & RX_CFG_STRIPCRC) ; - if (reg & RX_CFG_RX_RD) ; - if (reg & RX_CFG_ALP) ; - if (reg & RX_CFG_AIRL) ; - - /* we handle our own DMA, ignore what kernel says about it */ - if (reg & RX_CFG_MXDMA) ; - - //also, we currently don't care about fill/drain thresholds - //though this may change in the future with more realistic - //networks or a driver which changes it according to feedback - if (reg & (RX_CFG_DRTH | RX_CFG_DRTH0)) ; -#endif break; case PQCR: @@ -695,10 +617,6 @@ NSGigE::write(PacketPtr pkt) acceptArp = (reg & RFCR_AARP) ? true : false; multicastHashEnable = (reg & RFCR_MHEN) ? true : false; -#if 0 - if (reg & RFCR_APAT) - panic("RFCR_APAT not implemented!\n"); -#endif if (reg & RFCR_UHEN) panic("Unicast hash filtering not used by drivers!\n"); @@ -780,10 +698,6 @@ NSGigE::write(PacketPtr pkt) regs.tbisr |= (TBISR_MR_AN_COMPLETE | TBISR_MR_LINK_STATUS); } -#if 0 - if (reg & TBICR_MR_RESTART_AN) ; -#endif - break; case TBISR: @@ -795,11 +709,6 @@ NSGigE::write(PacketPtr pkt) regs.tanar |= reg & ~(TANAR_RF1 | TANAR_RF2 | TANAR_UNUSED); // Pause capability unimplemented -#if 0 - if (reg & TANAR_PS2) ; - if (reg & TANAR_PS1) ; -#endif - break; case TANLPAR: @@ -1309,26 +1218,6 @@ NSGigE::rxKick() cmdsts &= 0xffff0000; cmdsts += rxPacket->length; //i.e. set CMDSTS_SIZE -#if 0 - /* - * all the driver uses these are for its own stats keeping - * which we don't care about, aren't necessary for - * functionality and doing this would just slow us down. - * if they end up using this in a later version for - * functional purposes, just undef - */ - if (rxFilterEnable) { - cmdsts &= ~CMDSTS_DEST_MASK; - const EthAddr &dst = rxFifoFront()->dst(); - if (dst->unicast()) - cmdsts |= CMDSTS_DEST_SELF; - if (dst->multicast()) - cmdsts |= CMDSTS_DEST_MULTI; - if (dst->broadcast()) - cmdsts |= CMDSTS_DEST_MASK; - } -#endif - IpPtr ip(rxPacket); if (extstsEnable && ip) { extsts |= EXTSTS_IPPKT; diff --git a/src/dev/net/ns_gige.hh b/src/dev/net/ns_gige.hh index 5745c3040..7f0752a89 100644 --- a/src/dev/net/ns_gige.hh +++ b/src/dev/net/ns_gige.hh @@ -170,10 +170,6 @@ class NSGigE : public EtherDevBase /** pci settings */ bool ioEnable; -#if 0 - bool memEnable; - bool bmEnable; -#endif /*** BASIC STRUCTURES FOR TX/RX ***/ /* Data FIFOs */ diff --git a/src/dev/net/sinic.cc b/src/dev/net/sinic.cc index 8d73d1542..c6260078c 100644 --- a/src/dev/net/sinic.cc +++ b/src/dev/net/sinic.cc @@ -1170,40 +1170,6 @@ Device::rxFilter(const EthPacketPtr &packet) panic("receive filter not implemented\n"); bool drop = true; - -#if 0 - string type; - - EthHdr *eth = packet->eth(); - if (eth->unicast()) { - // If we're accepting all unicast addresses - if (acceptUnicast) - drop = false; - - // If we make a perfect match - if (acceptPerfect && params->eaddr == eth.dst()) - drop = false; - - if (acceptArp && eth->type() == ETH_TYPE_ARP) - drop = false; - - } else if (eth->broadcast()) { - // if we're accepting broadcasts - if (acceptBroadcast) - drop = false; - - } else if (eth->multicast()) { - // if we're accepting all multicasts - if (acceptMulticast) - drop = false; - - } - - if (drop) { - DPRINTF(Ethernet, "rxFilter drop\n"); - DDUMP(EthernetData, packet->data, packet->length); - } -#endif return drop; } diff --git a/src/dev/storage/simple_disk.cc b/src/dev/storage/simple_disk.cc index bc52e7ec5..26141c48c 100644 --- a/src/dev/storage/simple_disk.cc +++ b/src/dev/storage/simple_disk.cc @@ -83,14 +83,6 @@ void SimpleDisk::write(Addr addr, baddr_t block, int count) { panic("unimplemented!\n"); - -#if 0 - uint8_t *data = physmem->dma_addr(addr, count); - if (!data) - panic("dma out of range! write addr=%#x count=%d\n", addr, count); - - image->write(data, block, count); -#endif } SimpleDisk * diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc index ee405e872..cfde2ccc3 100644 --- a/src/gpu-compute/gpu_tlb.cc +++ b/src/gpu-compute/gpu_tlb.cc @@ -98,12 +98,6 @@ namespace X86ISA */ setMask = numSets - 1; - #if 0 - // GpuTLB doesn't yet support full system - walker = p->walker; - walker->setTLB(this); - #endif - maxCoalescedReqs = p->maxOutstandingReqs; // Do not allow maxCoalescedReqs to be more than the TLB associativity diff --git a/src/kern/linux/printk.cc b/src/kern/linux/printk.cc index 788a343b3..21aa34ed9 100644 --- a/src/kern/linux/printk.cc +++ b/src/kern/linux/printk.cc @@ -218,19 +218,11 @@ Printk(stringstream &out, Arguments args) case 'n': case 'N': { args += 2; -#if 0 - uint64_t n = (uint64_t)args++; - struct reg_values *rv = (struct reg_values *)args++; -#endif } break; case 'r': case 'R': { args += 2; -#if 0 - uint64_t n = (uint64_t)args++; - struct reg_desc *rd = (struct reg_desc *)args++; -#endif } break; case '%': diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index 89293430f..1536ada6e 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -2328,38 +2328,6 @@ BaseCache::regStats() overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); } -#if 0 - // MSHR access formulas - for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { - MemCmd cmd(access_idx); - const string &cstr = cmd.toString(); - - mshrAccesses[access_idx] - .name(name() + "." + cstr + "_mshr_accesses") - .desc("number of " + cstr + " mshr accesses(hits+misses)") - .flags(total | nozero | nonan) - ; - mshrAccesses[access_idx] = - mshr_hits[access_idx] + mshr_misses[access_idx] - + mshr_uncacheable[access_idx]; - } - - demandMshrAccesses - .name(name() + ".demand_mshr_accesses") - .desc("number of demand (read+write) mshr accesses") - .flags(total | nozero | nonan) - ; - demandMshrAccesses = demandMshrHits + demandMshrMisses; - - overallMshrAccesses - .name(name() + ".overall_mshr_accesses") - .desc("number of overall (read+write) mshr accesses") - .flags(total | nozero | nonan) - ; - overallMshrAccesses = overallMshrHits + overallMshrMisses - + overallMshrUncacheable; -#endif - // MSHR miss rate formulas for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { MemCmd cmd(access_idx); diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index bf190a591..c4e39716f 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -1007,15 +1007,6 @@ class BaseCache : public ClockedObject /** Total cycle latency of overall MSHR misses. */ Stats::Formula overallMshrUncacheableLatency; -#if 0 - /** The total number of MSHR accesses per command and thread. */ - Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; - /** The total number of demand MSHR accesses. */ - Stats::Formula demandMshrAccesses; - /** The total number of MSHR accesses. */ - Stats::Formula overallMshrAccesses; -#endif - /** The miss rate in the MSHRs pre command and thread. */ Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; /** The demand miss rate in the MSHRs. */ diff --git a/src/mem/ruby/system/GPUCoalescer.cc b/src/mem/ruby/system/GPUCoalescer.cc index 5f8725249..61ee2ae28 100644 --- a/src/mem/ruby/system/GPUCoalescer.cc +++ b/src/mem/ruby/system/GPUCoalescer.cc @@ -984,9 +984,6 @@ GPUCoalescer::print(ostream& out) const void GPUCoalescer::checkCoherence(Addr addr) { -#ifdef CHECK_COHERENCE - m_ruby_system->checkGlobalCoherenceInvariant(addr); -#endif } void diff --git a/src/mem/ruby/system/RubySystem.cc b/src/mem/ruby/system/RubySystem.cc index 3d0470ca3..572f5fe07 100644 --- a/src/mem/ruby/system/RubySystem.cc +++ b/src/mem/ruby/system/RubySystem.cc @@ -508,58 +508,6 @@ RubySystem::functionalWrite(PacketPtr pkt) return true; } -#ifdef CHECK_COHERENCE -// This code will check for cases if the given cache block is exclusive in -// one node and shared in another-- a coherence violation -// -// To use, the SLICC specification must call sequencer.checkCoherence(address) -// when the controller changes to a state with new permissions. Do this -// in setState. The SLICC spec must also define methods "isBlockShared" -// and "isBlockExclusive" that are specific to that protocol -// -void -RubySystem::checkGlobalCoherenceInvariant(const Address& addr) -{ -#if 0 - NodeID exclusive = -1; - bool sharedDetected = false; - NodeID lastShared = -1; - - for (int i = 0; i < m_chip_vector.size(); i++) { - if (m_chip_vector[i]->isBlockExclusive(addr)) { - if (exclusive != -1) { - // coherence violation - WARN_EXPR(exclusive); - WARN_EXPR(m_chip_vector[i]->getID()); - WARN_EXPR(addr); - WARN_EXPR(getTime()); - ERROR_MSG("Coherence Violation Detected -- 2 exclusive chips"); - } else if (sharedDetected) { - WARN_EXPR(lastShared); - WARN_EXPR(m_chip_vector[i]->getID()); - WARN_EXPR(addr); - WARN_EXPR(getTime()); - ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared"); - } else { - exclusive = m_chip_vector[i]->getID(); - } - } else if (m_chip_vector[i]->isBlockShared(addr)) { - sharedDetected = true; - lastShared = m_chip_vector[i]->getID(); - - if (exclusive != -1) { - WARN_EXPR(lastShared); - WARN_EXPR(exclusive); - WARN_EXPR(addr); - WARN_EXPR(getTime()); - ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared"); - } - } - } -#endif -} -#endif - RubySystem * RubySystemParams::create() { diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index a282995da..ba67311c7 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -685,9 +685,6 @@ Sequencer::print(ostream& out) const void Sequencer::checkCoherence(Addr addr) { -#ifdef CHECK_COHERENCE - m_ruby_system->checkGlobalCoherenceInvariant(addr); -#endif } void diff --git a/src/sim/process.cc b/src/sim/process.cc index d400b5def..9d6f3d17f 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -387,11 +387,6 @@ Process::serialize(CheckpointOut &cp) const */ warn("Checkpoints for file descriptors currently do not work."); -#if 0 - for (int x = 0; x < fds->getSize(); x++) - (*fds)[x].serializeSection(cp, csprintf("FDEntry%d", x)); -#endif - } void @@ -404,11 +399,6 @@ Process::unserialize(CheckpointIn &cp) * come back and fix them at a later date. */ warn("Checkpoints for file descriptors currently do not work."); -#if 0 - for (int x = 0; x < fds->getSize(); x++) - (*fds)[x]->unserializeSection(cp, csprintf("FDEntry%d", x)); - fds->restoreFileOffsets(); -#endif // The above returns a bool so that you could do something if you don't // find the param in the checkpoint if you wanted to, like set a default // but in this case we'll just stick with the instantiated value if not