From: Renlin Li <renlin.li@arm.com>
Date: Fri, 9 Oct 2015 16:22:33 +0000 (+0000)
Subject: [PATCH][ARM]Add earlyclobber modifier for neon_(vtrn, vuzp, vzip)<mode>_insn rtx
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=97400916d7e9f621e37ee1c09d30335b95c453ab;p=gcc.git

[PATCH][ARM]Add earlyclobber modifier for neon_(vtrn, vuzp, vzip)<mode>_insn rtx
pattern.

gcc/

2015-10-09  Renlin Li  <renlin.li@arm.com>

	* config/arm/neon.md (neon_vuzp<mode>_insn): Add & modifier for
        operands[0] and operands[2].
        (neon_vtrn<mode>_insn): Likewise.
        (neon_vzip<mode>_insn): Likewise.

From-SVN: r228662
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6156bd09c02..932253da4c1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2015-10-09  Renlin Li  <renlin.li@arm.com>
+
+	* config/arm/neon.md (neon_vuzp<mode>_insn): Add & modifier for
+	operands[0] and operands[2].
+	(neon_vtrn<mode>_insn): Likewise.
+	(neon_vzip<mode>_insn): Likewise.
+
 2015-10-09  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 
 	* match.pd: ((X inner_op C0) outer_op C1) New pattern.
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 26678663a64..e5a2b0f1c9a 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -4074,11 +4074,11 @@ if (BYTES_BIG_ENDIAN)
 
 ;; Note: Different operand numbering to handle tied registers correctly.
 (define_insn "*neon_vtrn<mode>_insn"
-  [(set (match_operand:VDQW 0 "s_register_operand" "=w")
+  [(set (match_operand:VDQW 0 "s_register_operand" "=&w")
         (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
                       (match_operand:VDQW 3 "s_register_operand" "2")]
                      UNSPEC_VTRN1))
-   (set (match_operand:VDQW 2 "s_register_operand" "=w")
+   (set (match_operand:VDQW 2 "s_register_operand" "=&w")
          (unspec:VDQW [(match_dup 1) (match_dup 3)]
                      UNSPEC_VTRN2))]
   "TARGET_NEON"
@@ -4100,11 +4100,11 @@ if (BYTES_BIG_ENDIAN)
 
 ;; Note: Different operand numbering to handle tied registers correctly.
 (define_insn "*neon_vzip<mode>_insn"
-  [(set (match_operand:VDQW 0 "s_register_operand" "=w")
+  [(set (match_operand:VDQW 0 "s_register_operand" "=&w")
         (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
                       (match_operand:VDQW 3 "s_register_operand" "2")]
                      UNSPEC_VZIP1))
-   (set (match_operand:VDQW 2 "s_register_operand" "=w")
+   (set (match_operand:VDQW 2 "s_register_operand" "=&w")
         (unspec:VDQW [(match_dup 1) (match_dup 3)]
                      UNSPEC_VZIP2))]
   "TARGET_NEON"
@@ -4126,11 +4126,11 @@ if (BYTES_BIG_ENDIAN)
 
 ;; Note: Different operand numbering to handle tied registers correctly.
 (define_insn "*neon_vuzp<mode>_insn"
-  [(set (match_operand:VDQW 0 "s_register_operand" "=w")
+  [(set (match_operand:VDQW 0 "s_register_operand" "=&w")
         (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
                       (match_operand:VDQW 3 "s_register_operand" "2")]
                      UNSPEC_VUZP1))
-   (set (match_operand:VDQW 2 "s_register_operand" "=w")
+   (set (match_operand:VDQW 2 "s_register_operand" "=&w")
         (unspec:VDQW [(match_dup 1) (match_dup 3)]
                      UNSPEC_VUZP2))]
   "TARGET_NEON"