From: Florent Kermarrec Date: Tue, 10 Feb 2015 15:23:12 +0000 (+0100) Subject: targets/udp: create udp loopback on port 8000 with dw=32 (to test data_width converters) X-Git-Tag: 24jan2021_ls180~2604^2~43 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=974169218f1070f138b62c7577e18ad78da32eb5;p=litex.git targets/udp: create udp loopback on port 8000 with dw=32 (to test data_width converters) --- diff --git a/targets/udp.py b/targets/udp.py index 27b605e0..32d8ee9c 100644 --- a/targets/udp.py +++ b/targets/udp.py @@ -114,13 +114,17 @@ class UDPSoC(GenSoC, AutoCSR): self.submodules.phy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth")) self.submodules.core = LiteEthUDPIPCore(self.phy, 0x10e2d5000000, convert_ip("192.168.1.40"), clk_freq) - # Create loopback on UDP port 6000 - loopback_port = self.core.udp.crossbar.get_port(6000) - self.submodules.loopback_buffer = PacketBuffer(eth_udp_user_description(8), 8192, 8) - self.comb += [ - Record.connect(loopback_port.source, self.loopback_buffer.sink), - Record.connect(self.loopback_buffer.source, loopback_port.sink) - ] + # Create loopback on UDP port 6000 (dw=8) + loopback_port = self.core.udp.crossbar.get_port(6000, dw=8) + loopback_buffer = PacketBuffer(eth_udp_user_description(8), 8192, 8) + self.submodules += loopback_buffer + self.comb += Port.connect(loopback_port, loopback_buffer) + + # Create loopback on UDP port 8000 (dw=32) + loopback_port = self.core.udp.crossbar.get_port(8000, dw=32) + loopback_buffer = PacketBuffer(eth_udp_user_description(32), 2048, 8) + self.submodules += loopback_buffer + self.comb += Port.connect(loopback_port, loopback_buffer) class UDPSoCDevel(UDPSoC, AutoCSR): csr_map = {