From: Luke Kenneth Casson Leighton Date: Sat, 25 May 2019 22:48:40 +0000 (+0100) Subject: separate out go_die from go_rd/go_wr to stop reg read/write triggering X-Git-Tag: div_pipeline~1943 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9743229f80f9b26a0dc81f64ed77b8861cbf7984;p=soc.git separate out go_die from go_rd/go_wr to stop reg read/write triggering --- diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index 9f7776d5..617fc32f 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -143,6 +143,7 @@ class FunctionUnits(Elaboratable): self.go_rd_i = Signal(n_int_alus, reset_less=True) self.go_wr_i = Signal(n_int_alus, reset_less=True) + self.go_die_i = Signal(n_int_alus, reset_less=True) self.req_rel_o = Signal(n_int_alus, reset_less=True) self.fn_issue_i = Signal(n_int_alus, reset_less=True) @@ -175,6 +176,7 @@ class FunctionUnits(Elaboratable): comb += intfudeps.issue_i.eq(self.fn_issue_i) comb += intfudeps.go_rd_i.eq(self.go_rd_i) comb += intfudeps.go_wr_i.eq(self.go_wr_i) + comb += intfudeps.go_die_i.eq(self.go_die_i) comb += self.readable_o.eq(intfudeps.readable_o) comb += self.writable_o.eq(intfudeps.writable_o) @@ -185,6 +187,7 @@ class FunctionUnits(Elaboratable): comb += intregdeps.go_rd_i.eq(self.go_rd_i) comb += intregdeps.go_wr_i.eq(self.go_wr_i) + comb += intregdeps.go_die_i.eq(self.go_die_i) comb += intregdeps.issue_i.eq(self.fn_issue_i) comb += self.dest_rsel_o.eq(intregdeps.dest_rsel_o) @@ -273,9 +276,6 @@ class Scoreboard(Elaboratable): m.submodules.shadows = shadows = ShadowMatrix(n_int_fus, n_int_fus) m.submodules.bshadow = bshadow = ShadowMatrix(n_int_fus, 1) - # combined go_rd/wr + go_die (go_die used to reset latches) - go_rd_rst = Signal(n_int_fus, reset_less=True) - go_wr_rst = Signal(n_int_fus, reset_less=True) # record previous instruction to cast shadow on current instruction fn_issue_prev = Signal(n_int_fus) prev_shadow = Signal(n_int_fus) @@ -319,6 +319,17 @@ class Scoreboard(Elaboratable): comb += issueunit.i.busy_i.eq(cu.busy_o) comb += self.busy_o.eq(cu.busy_o.bool()) + #--------- + # merge shadow matrices outputs + #--------- + + # these are explained in ShadowMatrix docstring, and are to be + # connected to the FUReg and FUFU Matrices, to get them to reset + anydie = Signal(n_int_fus, reset_less=True) + allshadown = Signal(n_int_fus, reset_less=True) + comb += allshadown.eq(shadows.shadown_o & bshadow.shadown_o) + comb += anydie.eq(shadows.go_die_o | bshadow.go_die_o) + #--------- # connect fu-fu matrix #--------- @@ -328,9 +339,11 @@ class Scoreboard(Elaboratable): go_wr_o = intpick1.go_wr_o go_rd_i = intfus.go_rd_i go_wr_i = intfus.go_wr_i + go_die_i = intfus.go_die_i # NOTE: connect to the shadowed versions so that they can "die" (reset) - comb += go_rd_i[0:n_int_fus].eq(go_rd_rst[0:n_int_fus]) # rd - comb += go_wr_i[0:n_int_fus].eq(go_wr_rst[0:n_int_fus]) # wr + comb += go_rd_i[0:n_int_fus].eq(go_rd_o[0:n_int_fus]) # rd + comb += go_wr_i[0:n_int_fus].eq(go_wr_o[0:n_int_fus]) # wr + comb += go_die_i[0:n_int_fus].eq(anydie[0:n_int_fus]) # die # Connect Picker #--------- @@ -346,17 +359,6 @@ class Scoreboard(Elaboratable): #--------- comb += shadows.issue_i.eq(fn_issue_o) - # these are explained in ShadowMatrix docstring, and are to be - # connected to the FUReg and FUFU Matrices, to get them to reset - # NOTE: do NOT connect these to the Computation Units. The CUs need to - # do something slightly different (due to the revolving-door SRLatches) - anydie = Signal(n_int_fus, reset_less=True) - allshadown = Signal(n_int_fus, reset_less=True) - comb += allshadown.eq(shadows.shadown_o & bshadow.shadown_o) - comb += anydie.eq(shadows.go_die_o | bshadow.go_die_o) - comb += go_rd_rst.eq(go_rd_o | anydie) - comb += go_wr_rst.eq(go_wr_o | anydie) - #--------- # NOTE; this setup is for the instruction order preservation... diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py index 242c5a43..e12f2163 100644 --- a/src/scoreboard/dependence_cell.py +++ b/src/scoreboard/dependence_cell.py @@ -31,6 +31,7 @@ class DepCell(Elaboratable): self.issue_i = Signal(reset_less=True) # Issue in (top) self.hazard_i = Signal(reset_less=True) # to check hazard self.go_i = Signal(reset_less=True) # Go read/write in (left) + self.die_i = Signal(reset_less=True) # Die in (left) self.q_o = Signal(reset_less=True) # Latch out (register active) # for Register File Select Lines (vertical) @@ -44,14 +45,14 @@ class DepCell(Elaboratable): # reset on go HI, set on dest and issue m.d.comb += l.s.eq(self.issue_i & self.reg_i) - m.d.comb += l.r.eq(self.go_i) + m.d.comb += l.r.eq(self.go_i | self.die_i) # Function Unit "Forward Progress". m.d.comb += self.fwd_o.eq((l.q) & self.hazard_i) # & ~self.issue_i) # Register Select. Activated on go read/write and *current* latch set m.d.comb += self.q_o.eq(l.qlq) - m.d.comb += self.rsel_o.eq(self.q_o & self.go_i) + m.d.comb += self.rsel_o.eq(l.qlq & self.go_i) return m @@ -60,6 +61,7 @@ class DepCell(Elaboratable): yield self.hazard_i yield self.issue_i yield self.go_i + yield self.die_i yield self.q_o yield self.rsel_o yield self.fwd_o @@ -85,6 +87,7 @@ class DependenceCell(Elaboratable): self.go_wr_i = Signal(reset_less=True) # Go Write in (left) self.go_rd_i = Signal(reset_less=True) # Go Read in (left) + self.go_die_i = Signal(reset_less=True) # Go Die in (left) # for Register File Select Lines (vertical) self.dest_rsel_o = Signal(reset_less=True) # dest reg sel (bottom) @@ -102,9 +105,10 @@ class DependenceCell(Elaboratable): m.submodules.src1_c = src1_c = DepCell() m.submodules.src2_c = src2_c = DepCell() - # connect issue + # connect issue and die for c in [dest_c, src1_c, src2_c]: m.d.comb += c.issue_i.eq(self.issue_i) + m.d.comb += c.die_i.eq(self.go_die_i) # connect go_rd / go_wr (dest->wr, src->rd) m.d.comb += dest_c.go_i.eq(self.go_wr_i) @@ -152,6 +156,7 @@ class DependenceCell(Elaboratable): yield self.issue_i yield self.go_wr_i yield self.go_rd_i + yield self.go_die_i yield self.dest_rsel_o yield self.src1_rsel_o yield self.src2_rsel_o @@ -183,6 +188,7 @@ class DependencyRow(Elaboratable): self.issue_i = Signal(reset_less=True) self.go_wr_i = Signal(reset_less=True) self.go_rd_i = Signal(reset_less=True) + self.go_die_i = Signal(reset_less=True) self.dest_rsel_o = Signal(n_reg_col, reset_less=True) self.src1_rsel_o = Signal(n_reg_col, reset_less=True) @@ -229,13 +235,14 @@ class DependencyRow(Elaboratable): ] # --- - # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr + # connect Dep die/issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr # --- for rn in range(self.n_reg_col): dc = rcell[rn] m.d.comb += [dc.go_rd_i.eq(self.go_rd_i), dc.go_wr_i.eq(self.go_wr_i), dc.issue_i.eq(self.issue_i), + dc.go_die_i.eq(self.go_die_i), ] # --- @@ -282,6 +289,7 @@ class DependencyRow(Elaboratable): yield self.issue_i yield self.go_wr_i yield self.go_rd_i + yield self.go_die_i yield self.dest_rsel_o yield self.src1_rsel_o yield self.src2_rsel_o diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py index 4ac2a6da..a631a652 100644 --- a/src/scoreboard/fu_dep_cell.py +++ b/src/scoreboard/fu_dep_cell.py @@ -12,6 +12,7 @@ class DepCell(Elaboratable): self.pend_i = Signal(reset_less=True) # pending bit in (left) self.issue_i = Signal(reset_less=True) # Issue in (top) self.go_i = Signal(reset_less=True) # Go read/write in (left) + self.die_i = Signal(reset_less=True) # Go die in (left) # wait self.wait_o = Signal(reset_less=True) # wait out (right) @@ -22,7 +23,7 @@ class DepCell(Elaboratable): # reset on go HI, set on dest and issue m.d.comb += l.s.eq(self.issue_i & self.pend_i) - m.d.comb += l.r.eq(self.go_i) + m.d.comb += l.r.eq(self.go_i | self.die_i) # wait out m.d.comb += self.wait_o.eq(l.qlq & ~self.issue_i) @@ -33,6 +34,7 @@ class DepCell(Elaboratable): yield self.pend_i yield self.issue_i yield self.go_i + yield self.die_i yield self.wait_o def ports(self): @@ -50,6 +52,7 @@ class FUDependenceCell(Elaboratable): self.go_wr_i = Signal(reset_less=True) # Go Write in (left) self.go_rd_i = Signal(reset_less=True) # Go Read in (left) + self.go_die_i = Signal(reset_less=True) # Go Die in (left) # outputs (latched rd/wr wait) self.rd_wait_o = Signal(reset_less=True) # read waiting out (right) @@ -63,6 +66,7 @@ class FUDependenceCell(Elaboratable): # connect issue for c in [rd_c, wr_c]: m.d.comb += c.issue_i.eq(self.issue_i) + m.d.comb += c.die_i.eq(self.go_die_i) # connect go_rd / go_wr m.d.comb += wr_c.go_i.eq(self.go_wr_i) @@ -84,6 +88,7 @@ class FUDependenceCell(Elaboratable): yield self.issue_i yield self.go_wr_i yield self.go_rd_i + yield self.go_die_i yield self.rd_wait_o yield self.wr_wait_o diff --git a/src/scoreboard/fu_fu_matrix.py b/src/scoreboard/fu_fu_matrix.py index d8eaa858..5d8b2cb2 100644 --- a/src/scoreboard/fu_fu_matrix.py +++ b/src/scoreboard/fu_fu_matrix.py @@ -25,6 +25,7 @@ class FUFUDepMatrix(Elaboratable): self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left) self.go_rd_i = Signal(n_fu_row, reset_less=True) # Go Read in (left) + self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left) # for Function Unit Readable/Writable (horizontal) self.readable_o = Signal(n_fu_col, reset_less=True) # readable (bot) @@ -98,14 +99,17 @@ class FUFUDepMatrix(Elaboratable): for y in range(self.n_fu_row): go_rd_i = [] go_wr_i = [] + go_die_i = [] for x in range(self.n_fu_col): dc = dm[x][y] # accumulate cell go_rd/go_wr go_rd_i.append(dc.go_rd_i) go_wr_i.append(dc.go_wr_i) + go_die_i.append(dc.go_die_i) # wire up inputs from module to row cell inputs (Cat is gooood) m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i), Cat(*go_wr_i).eq(self.go_wr_i), + Cat(*go_die_i).eq(self.go_die_i), ] # --- diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py index 8ead6c2e..f774fb9f 100644 --- a/src/scoreboard/fu_reg_matrix.py +++ b/src/scoreboard/fu_reg_matrix.py @@ -42,9 +42,10 @@ class FURegDepMatrix(Elaboratable): self.wr_rsel_o = Signal(n_reg_col, reset_less=True) # wr pending (bot) self.rd_rsel_o = Signal(n_reg_col, reset_less=True) # rd pending (bot) - self.issue_i = Signal(n_fu_row, reset_less=True) # Issue in (top) - self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left) + self.issue_i = Signal(n_fu_row, reset_less=True) # Issue in (top) + self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left) self.go_rd_i = Signal(n_fu_row, reset_less=True) # Go Read in (left) + self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left) # for Register File Select Lines (horizontal), per-reg self.dest_rsel_o = Signal(n_reg_col, reset_less=True) # dest reg (bot) @@ -181,16 +182,19 @@ class FURegDepMatrix(Elaboratable): # --- go_rd_i = [] go_wr_i = [] + go_die_i = [] issue_i = [] for fu in range(self.n_fu_row): dc = dm[fu] # accumulate cell fwd outputs for dest/src1/src2 go_rd_i.append(dc.go_rd_i) go_wr_i.append(dc.go_wr_i) + go_die_i.append(dc.go_die_i) issue_i.append(dc.issue_i) # wire up inputs from module to row cell inputs (Cat is gooood) m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i), Cat(*go_wr_i).eq(self.go_wr_i), + Cat(*go_die_i).eq(self.go_die_i), Cat(*issue_i).eq(self.issue_i), ] @@ -203,6 +207,7 @@ class FURegDepMatrix(Elaboratable): yield self.issue_i yield self.go_wr_i yield self.go_rd_i + yield self.go_die_i yield self.dest_rsel_o yield self.src1_rsel_o yield self.src2_rsel_o