From: lkcl <lkcl@web>
Date: Tue, 28 Jun 2022 18:13:32 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1477
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9746262f7ec2bce8502db17bbba3c2363a04e006;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index cb7a21faf..88ef46df8 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -466,7 +466,10 @@ uint64_t grevlutr(uint64_t RA, uint64_t RB, bool iv, bool is32b)
 | -- | -- | --- | ---  | -----   | -----|--| ------ | ----- |
 | NN | RT | RA  | s0-4 | im0-7   | 1 iv |s5| grevlogi |      |
 | NN | RT | RA  | RB   | im0-7   | 01   |0 | grevlog |           |
-| NN | RT | RA  | RB   | im0-7   | 01   |1 | grevlogw |           |
+
+An equivalent to `grevlogw` may be synthesised by setting the
+appropriate bits in RB to set the top half of RT to zero.
+Thus an explicit grevlogw instruction is not necessary.
 
 # xperm