From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 1 Oct 2018 13:37:34 +0000 (+0200)
Subject: platforms/genesys2: add eth clock timing constraint
X-Git-Tag: 24jan2021_ls180~1576
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=975be6686fc06ca3364d8ce32edd14eada56aa14;p=litex.git

platforms/genesys2: add eth clock timing constraint
---

diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py
index 0a454ab8..89f72120 100644
--- a/litex/boards/platforms/genesys2.py
+++ b/litex/boards/platforms/genesys2.py
@@ -117,3 +117,7 @@ class Platform(XilinxPlatform):
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
+        try:
+            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
+        except ConstraintError:
+            pass