From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 Aug 2020 18:29:59 +0000 (+0100)
Subject: test in sram for deliberately delaying response
X-Git-Tag: 24jan2021_ls180~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9762a3c9a014c6ab6cb8f70a09bdcd0f7a8a3e6d;p=nmigen-soc.git

test in sram for deliberately delaying response
---

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index dbb7615..22b0efd 100644
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -98,6 +98,13 @@ class SRAM(Elaboratable):
         # generate ack
         m.d.sync += self.bus.ack.eq(0)
         with m.If(self.bus.cyc & self.bus.stb & ~self.bus.ack):
-            m.d.sync += self.bus.ack.eq(1)
+            if False: # test which deliberately delays response
+                counter = Signal(3)
+                m.d.sync += counter.eq(counter + 1)
+                with m.If(counter == 7):
+                    m.d.sync += self.bus.ack.eq(1)
+                    m.d.sync += counter.eq(0)
+            else:
+                m.d.sync += self.bus.ack.eq(1)
 
         return m