From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 26 Apr 2019 02:59:33 +0000 (-0700)
Subject: Actually use pm.st.shiftxB
X-Git-Tag: working-ls180~1208^2~309
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=976d8030dce8cd242401933ac8ea6c8ffe8af224;p=yosys.git

Actually use pm.st.shiftxB
---

diff --git a/passes/pmgen/split_shiftx.cc b/passes/pmgen/split_shiftx.cc
index 2af0ebecf..3cbabcd76 100644
--- a/passes/pmgen/split_shiftx.cc
+++ b/passes/pmgen/split_shiftx.cc
@@ -30,10 +30,11 @@ void create_split_shiftx(split_shiftx_pm &pm)
 	if (pm.blacklist_cells.count(pm.st.shiftx))
 		return;
 	SigSpec A = pm.st.shiftx->getPort("\\A");
-	SigSpec B = pm.st.shiftx->getPort("\\B");
+	SigSpec B = pm.st.shiftxB;
+	log_assert(!B.empty());
 	SigSpec Y = pm.st.shiftx->getPort("\\Y");
 	const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int();
-	const int B_WIDTH = pm.st.shiftx->getParam("\\B_WIDTH").as_int();
+	const int B_WIDTH = GetSize(pm.st.shiftxB);
 	const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int();
 	int trailing_zeroes = 0;
 	for (; B[trailing_zeroes] == RTLIL::S0; ++trailing_zeroes) ;
diff --git a/passes/pmgen/split_shiftx.pmg b/passes/pmgen/split_shiftx.pmg
index c9e0ff995..3aafe1975 100644
--- a/passes/pmgen/split_shiftx.pmg
+++ b/passes/pmgen/split_shiftx.pmg
@@ -12,11 +12,13 @@ match macc
 endmatch
 
 code shiftxB
+	shiftxB = port(shiftx, \B);
+
 	if (macc) {
-		shiftxB = port(shiftx, \B);
 		const int b_width = param(shiftx, \B_WIDTH).as_int();
 		if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0)
 			shiftxB = shiftxB.extract(0, b_width-1);
+
 		if (port(macc, \Y) != shiftxB) {
 			blacklist(shiftx);
 			reject;