From: Michael Nolan <mtnolan2640@gmail.com>
Date: Wed, 20 May 2020 15:15:10 +0000 (-0400)
Subject: Add test for edge cases that were previously buggy
X-Git-Tag: div_pipeline~1031
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9772d66af3f4f97fd4e4787ecf1dbb61cbb0e6c3;p=soc.git

Add test for edge cases that were previously buggy
---

diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py
index 6223a3dd..05e1a816 100644
--- a/src/soc/fu/logical/test/test_pipe_caller.py
+++ b/src/soc/fu/logical/test/test_pipe_caller.py
@@ -153,6 +153,14 @@ class LogicalTestCase(FHDLTestCase):
             initial_regs[1] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst), initial_regs)
 
+    def test_popcnt_edge(self):
+        insns = ["popcntb", "popcntw", "popcntd"]
+        for choice in insns:
+            lst = [f"{choice} 3, 1"]
+            initial_regs = [0] * 32
+            initial_regs[1] = -1
+            self.run_tst_program(Program(lst), initial_regs)
+
     def test_cmpb(self):
         lst = ["cmpb 3, 1, 2"]
         initial_regs = [0] * 32