From: whitequark Date: Wed, 16 Jan 2019 17:20:30 +0000 (+0000) Subject: back.rtlil: slightly nicer naming for $next signals. NFC. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9792ec711d419213085f45ea3bf88e769e68d521;p=nmigen.git back.rtlil: slightly nicer naming for $next signals. NFC. --- diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 9a9ef7c..ec157fe 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -262,7 +262,7 @@ class _ValueCompilerState: port_id=port_id, port_kind=port_kind, src=src(signal.src_loc)) if signal in self.driven: - wire_next = self.rtlil.wire(width=signal.nbits, name="$next$" + wire_curr, + wire_next = self.rtlil.wire(width=signal.nbits, name="$next" + wire_curr, src=src(signal.src_loc)) else: wire_next = None @@ -670,7 +670,7 @@ def convert_fragment(builder, fragment, name, top): verilog_trigger_sync_emitted = False # Register all signals driven in the current fragment. This must be done first, as it - # affects further codegen; e.g. whether $next$sig signals will be generated and used. + # affects further codegen; e.g. whether $next\sig signals will be generated and used. for domain, signal in fragment.iter_drivers(): compiler_state.add_driven(signal, sync=domain is not None) @@ -754,8 +754,8 @@ def convert_fragment(builder, fragment, name, top): with module.process(name="$group_{}".format(group)) as process: with process.case() as case: - # For every signal in comb domain, assign $next$sig to the reset value. - # For every signal in sync domains, assign $next$sig to the current + # For every signal in comb domain, assign $next\sig to the reset value. + # For every signal in sync domains, assign $next\sig to the current # value (\sig). for domain, signal in fragment.iter_drivers(): if signal not in group_signals: @@ -797,7 +797,7 @@ def convert_fragment(builder, fragment, name, top): sync.update(verilog_trigger, "1'0") verilog_trigger_sync_emitted = True - # For every signal in every domain, assign \sig to $next$sig. The sensitivity list, + # For every signal in every domain, assign \sig to $next\sig. The sensitivity list, # however, differs between domains: for comb domains, it is `always`, for sync # domains with sync reset, it is `posedge clk`, for sync domains with async reset # it is `posedge clk or posedge rst`.