From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 1 Aug 2014 13:25:42 +0000 (+0200)
Subject: Packed SigBit::data and SigBit::offset in a union
X-Git-Tag: yosys-0.4~337
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=97a17d39e2f0088e02ed8496d905528722115674;p=yosys.git

Packed SigBit::data and SigBit::offset in a union
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 012253144..79ddd2e02 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1681,9 +1681,11 @@ RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
 RTLIL::SigChunk::SigChunk(RTLIL::SigBit bit)
 {
 	wire = bit.wire;
+	offset = 0;
 	if (wire == NULL)
 		data = RTLIL::Const(bit.data);
-	offset = bit.offset;
+	else
+		offset = bit.offset;
 	width = 1;
 }
 
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 796d45df1..43c7e1050 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -707,15 +707,17 @@ struct RTLIL::SigChunk
 struct RTLIL::SigBit
 {
 	RTLIL::Wire *wire;
-	RTLIL::State data;
-	int offset;
-
-	SigBit() : wire(NULL), data(RTLIL::State::S0), offset(0) { }
-	SigBit(RTLIL::State bit) : wire(NULL), data(bit), offset(0) { }
-	SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { log_assert(wire && wire->width == 1); }
-	SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { log_assert(wire); }
-	SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { log_assert(chunk.width == 1); }
-	SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[index]), offset(chunk.wire ? chunk.offset + index : 0) { }
+	union {
+		RTLIL::State data;
+		int offset;
+	};
+
+	SigBit() : wire(NULL), data(RTLIL::State::S0) { }
+	SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
+	SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0) { log_assert(wire && wire->width == 1); }
+	SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); }
+	SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; log_assert(chunk.width == 1); }
+	SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data.bits[index]; }
 	SigBit(const RTLIL::SigSpec &sig);
 
 	bool operator <(const RTLIL::SigBit &other) const {