From: lkcl <lkcl@web>
Date: Wed, 29 Mar 2023 16:47:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~240
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=97a7ba3783858769ab7c5292b6cfd7cc3f1cb834;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 8363a1422..5b6b403e9 100644
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -21,7 +21,7 @@ Links:
 # Introduction
 
 Simple-V is a type of Vectorisation best described as a "Prefix Loop
-Subsystem" similar to the Z80 `LDIR` instruction and to the x86 `REP`
+Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR` instruction and to the 8086 `REP`
 Prefix instruction.  More advanced features are similar to the Z80
 `CPIR` instruction. If viewed as an actual Vector ISA it introduces
 over 1.5 million 64-bit Vector instructions.  SVP64, the instruction