From: Steve Reinhardt <steve.reinhardt@amd.com>
Date: Tue, 21 Apr 2009 15:17:36 +0000 (-0700)
Subject: Minor tweaks for future Ruby compatibility.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=97b6947eb767ba1a7750525123c0c517223cee43;p=gem5.git

Minor tweaks for future Ruby compatibility.
---

diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index a771710fa..0004e4fe6 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -31,7 +31,6 @@ from os.path import join as joinpath
 import m5
 from m5.objects import *
 m5.AddToPath('../common')
-from Caches import L1Cache
 
 def setCPUClass(options):
 
@@ -151,9 +150,8 @@ def run(options, root, testsys, cpu_class):
 
             if not options.caches:
                 # O3 CPU must have a cache to work.
-                switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
-                                                         L1Cache(size = '64kB'))
-                switch_cpus_1[i].connectMemPorts(testsys.membus)
+                print "O3 CPU must be used with caches"
+                sys.exit(1)
 
             testsys.switch_cpus = switch_cpus
             testsys.switch_cpus_1 = switch_cpus_1
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 8dbadccc4..f027168a4 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -49,6 +49,8 @@
 //
 class PhysicalMemory : public MemObject
 {
+  protected:
+
     class MemoryPort : public SimpleTimingPort
     {
         PhysicalMemory *memory;