From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 17 Nov 2021 15:52:41 +0000 (+0000)
Subject: XER regspec_decode_write was not sophisticated enough.
X-Git-Tag: sv_maxu_works-initial~733
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=97bf4ecf9795ca02a2f6af9f5fa5a951320b5901;p=openpower-isa.git

XER regspec_decode_write was not sophisticated enough.

XER is being written to without the hazard vector being set.
this previously did not matter because the TestIssuer FSM was
only allowing one pipeline access to all regfiles at a time.

in-order now will have overlapping instructions so it matters
---

diff --git a/src/openpower/decoder/decode2execute1.py b/src/openpower/decoder/decode2execute1.py
index 9020e7e8..e7deff5b 100644
--- a/src/openpower/decoder/decode2execute1.py
+++ b/src/openpower/decoder/decode2execute1.py
@@ -57,6 +57,7 @@ class IssuerDecode2ToOperand(RecordObject):
         self.rc = Data(1, "rc")
         self.oe = Data(1, "oe")
         self.input_carry = Signal(CryIn, reset_less=True)
+        self.output_carry = Signal(reset_less=True)
         self.traptype  = Signal(TT.size, reset_less=True) # trap main_stage.py
         self.ldst_exc  = LDSTException("exc")
         self.trapaddr  = Signal(13, reset_less=True)
diff --git a/src/openpower/decoder/power_regspec_map.py b/src/openpower/decoder/power_regspec_map.py
index 5ec5f629..c9b1c074 100644
--- a/src/openpower/decoder/power_regspec_map.py
+++ b/src/openpower/decoder/power_regspec_map.py
@@ -155,11 +155,14 @@ def regspec_decode_write(e, regfile, name):
         CA = 1<<XERRegsEnum.CA
         OV = 1<<XERRegsEnum.OV
         if name == 'xer_so':
-            return e.xer_out, SO # hmmm
+            return (e.xer_out | (e.do.oe.oe[0] & e.do.oe.ok),
+                    SO) # hmmm
         if name == 'xer_ov':
-            return e.xer_out, OV # hmmm
+            return (e.xer_out | (e.do.oe.oe[0] & e.do.oe.ok),
+                    OV) # hmmm
         if name == 'xer_ca':
-            return e.xer_out, CA # hmmm
+            return (e.xer_out | (e.do.output_carry),
+                    CA) # hmmm
 
     # STATE regfile
 
diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index 63c556fd..e03ee7a7 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -126,6 +126,19 @@ class ALUTestCase(TestAccumulatorBase):
                 self.add_case(Program(lst, bigendian),
                               initial_regs, initial_sprs)
 
+    def case_addme_ca_so_4(self):
+        """test of SO being set
+        """
+        lst = ["addmeo. 6, 16"]
+        initial_regs = [0] * 32
+        initial_regs[16] = 0x7fffffffffffffff
+        initial_sprs = {}
+        xer = SelectableInt(0, 64)
+        xer[XER_bits['CA']] = 1
+        initial_sprs[special_sprs['XER']] = xer
+        self.add_case(Program(lst, bigendian),
+                      initial_regs, initial_sprs)
+
     def case_addme_ca_so_3(self):
         """bug where SO does not get passed through to CR0
         """