From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 7 Dec 2006 23:49:10 +0000 (-0500)
Subject: Compilation fixes
X-Git-Tag: m5_2.0_beta3~274^2~14
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=97cdd5198b9c1a5b881833a71f24a22430a2b07b;p=gem5.git

Compilation fixes

--HG--
extra : convert_revision : 974e91a960251a35d5ebb76c7e6c7ac330339896
---

diff --git a/src/cpu/o3/sparc/cpu.hh b/src/cpu/o3/sparc/cpu.hh
index 73c859367..08ebd2710 100644
--- a/src/cpu/o3/sparc/cpu.hh
+++ b/src/cpu/o3/sparc/cpu.hh
@@ -128,6 +128,24 @@ class SparcO3CPU : public FullO3CPU<Impl>
      */
     void squashFromTC(unsigned tid);
 
+#if FULL_SYSTEM
+    /** Posts an interrupt. */
+    void post_interrupt(int int_num, int index);
+    /** HW return from error interrupt. */
+    Fault hwrei(unsigned tid);
+
+    bool simPalCheck(int palFunc, unsigned tid);
+
+    /** Returns the Fault for any valid interrupt. */
+    Fault getInterrupts();
+
+    /** Processes any an interrupt fault. */
+    void processInterrupts(Fault interrupt);
+
+    /** Halts the CPU. */
+    void halt() { panic("Halt not implemented!\n"); }
+#endif
+
     /** Traps to handle given fault. */
     void trap(Fault fault, unsigned tid);
 
diff --git a/src/cpu/o3/sparc/cpu_builder.cc b/src/cpu/o3/sparc/cpu_builder.cc
index 81f419ee0..3cac89bad 100644
--- a/src/cpu/o3/sparc/cpu_builder.cc
+++ b/src/cpu/o3/sparc/cpu_builder.cc
@@ -55,8 +55,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
 #if FULL_SYSTEM
     SimObjectParam<System *> system;
     Param<int> cpu_id;
-    SimObjectParam<AlphaISA::ITB *> itb;
-    SimObjectParam<AlphaISA::DTB *> dtb;
+    SimObjectParam<SparcISA::ITB *> itb;
+    SimObjectParam<SparcISA::DTB *> dtb;
     Param<Tick> profile;
 
     Param<bool> do_quiesce;
diff --git a/src/cpu/o3/sparc/dyn_inst_impl.hh b/src/cpu/o3/sparc/dyn_inst_impl.hh
index daf93d4a8..b830ee7bd 100644
--- a/src/cpu/o3/sparc/dyn_inst_impl.hh
+++ b/src/cpu/o3/sparc/dyn_inst_impl.hh
@@ -126,7 +126,8 @@ template <class Impl>
 bool
 SparcDynInst<Impl>::simPalCheck(int palFunc)
 {
-    return this->cpu->simPalCheck(palFunc, this->threadNumber);
+    panic("simPalCheck called, but there's no PAL in SPARC!\n");
+    return false;
 }
 #else
 template <class Impl>
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 0849001e8..4987d6eb4 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -68,10 +68,10 @@ class O3ThreadContext : public ThreadContext
 
 #if FULL_SYSTEM
     /** Returns a pointer to the ITB. */
-    virtual AlphaISA::ITB *getITBPtr() { return cpu->itb; }
+    TheISA::ITB *getITBPtr() { return cpu->itb; }
 
     /** Returns a pointer to the DTB. */
-    virtual AlphaISA::DTB *getDTBPtr() { return cpu->dtb; }
+    TheISA::DTB *getDTBPtr() { return cpu->dtb; }
 #endif
 
     /** Returns a pointer to this CPU. */