From: Timothy M. Jones <tjones1@inf.ed.ac.uk>
Date: Thu, 22 Jul 2010 17:54:37 +0000 (+0100)
Subject: Power: The condition register should be set or cleared upon a system call
X-Git-Tag: stable_2012_02_02~981
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=97d245278d4b4bee844c141c3b6f370e27f73a45;p=gem5.git

Power: The condition register should be set or cleared upon a system call
return to indicate success or failure.
---

diff --git a/src/arch/power/miscregs.hh b/src/arch/power/miscregs.hh
index cd9815b2a..34732dad1 100644
--- a/src/arch/power/miscregs.hh
+++ b/src/arch/power/miscregs.hh
@@ -44,7 +44,12 @@ const char * const miscRegName[NUM_MISCREGS] = {
 };
 
 BitUnion32(Cr)
-    Bitfield<31,28> cr0;
+    SubBitUnion(cr0, 31, 28)
+        Bitfield<31> lt;
+        Bitfield<30> gt;
+        Bitfield<29> eq;
+        Bitfield<28> so;
+    EndSubBitUnion(cr0)
     Bitfield<27,24> cr1;
 EndBitUnion(Cr)
 
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index 92f993e4c..12b216e50 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -284,5 +284,12 @@ void
 PowerLiveProcess::setSyscallReturn(ThreadContext *tc,
         SyscallReturn return_value)
 {
+    Cr cr = tc->readIntReg(INTREG_CR);
+    if (return_value.successful()) {
+        cr.cr0.so = 0;
+    } else {
+        cr.cr0.so = 1;
+    }
+    tc->setIntReg(INTREG_CR, cr);
     tc->setIntReg(ReturnValueReg, return_value.value());
 }