From: Timothy Hayes <timothy.hayes@arm.com>
Date: Thu, 7 May 2020 11:03:03 +0000 (+0100)
Subject: mem-ruby: MESI_Two_Level missing function compilation fix
X-Git-Tag: v20.0.0.0~50
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=97daaf1f2e57e067d8630445de12d508dd83a31f;p=gem5.git

mem-ruby: MESI_Two_Level missing function compilation fix

The recent commit dd6cd33 removed the Ruby Sequencer function
invalidateSC in favour of doing this implicitely via
evictionCallback. The protocol MESI_Two_Level still contains one
explicit call to this function, however, this is now superflous
as forward_eviction_to_cpu is called in the same transition. This
patch removes the remaining calls to invalidateSC.

JIRA: https://gem5.atlassian.net/browse/GEM5-499

Change-Id: If51d8bebf6aa39d20789639aab0d262d5173ca59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28747
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
index 3e3580f70..3e07e0302 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -816,11 +828,6 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
     }
   }
 
-  action(dg_invalidate_sc, "dg",
-         desc="Invalidate store conditional as the cache lost permissions") {
-    sequencer.invalidateSC(address);
-  }
-
   action(h_load_hit, "hd",
          desc="Notify sequencer the load completed.")
   {
@@ -1394,7 +1401,6 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
   transition(SM, Inv, IM) {
     forward_eviction_to_cpu;
     fi_sendInvAck;
-    dg_invalidate_sc;
     l_popRequestQueue;
   }
 
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 6ab0f3f76..e3a136f24 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -132,7 +132,6 @@ structure (Sequencer, external = "yes") {
   void evictionCallback(Addr);
   void recordRequestType(SequencerRequestType);
   bool checkResourceAvailable(CacheResourceType, Addr);
-  void invalidateSC(Addr);
 }
 
 structure (GPUCoalescer, external = "yes") {