From: bugzilla-daemon Date: Tue, 9 Jun 2020 22:08:49 +0000 (+0000) Subject: [libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt,... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=97ddff45ae523d0b51e1f35b0de53568ff61ebbe;p=libre-riscv-dev.git [libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, microwatt, simulator, side-by-side --- diff --git a/e8/2a65e167856476d2562fcada8f7129b7838eeb b/e8/2a65e167856476d2562fcada8f7129b7838eeb new file mode 100644 index 0000000..234983c --- /dev/null +++ b/e8/2a65e167856476d2562fcada8f7129b7838eeb @@ -0,0 +1,75 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Tue, 09 Jun 2020 23:08:52 +0100 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jimQN-0005B3-Pc; Tue, 09 Jun 2020 23:08:51 +0100 +Received: from localhost ([127.0.0.1] helo=bugs.libre-soc.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) id 1jimQL-0005At-IG + for libre-riscv-dev@lists.libre-riscv.org; Tue, 09 Jun 2020 23:08:49 +0100 +From: bugzilla-daemon@libre-soc.org +To: libre-riscv-dev@lists.libre-riscv.org +Date: Tue, 09 Jun 2020 22:08:49 +0000 +X-Bugzilla-Reason: CC +X-Bugzilla-Type: changed +X-Bugzilla-Watch-Reason: None +X-Bugzilla-Product: Libre-SOC's first SoC +X-Bugzilla-Component: Source Code +X-Bugzilla-Version: unspecified +X-Bugzilla-Keywords: +X-Bugzilla-Severity: enhancement +X-Bugzilla-Who: lkcl@lkcl.net +X-Bugzilla-Status: CONFIRMED +X-Bugzilla-Resolution: +X-Bugzilla-Priority: --- +X-Bugzilla-Assigned-To: lkcl@lkcl.net +X-Bugzilla-Flags: +X-Bugzilla-Changed-Fields: +Message-ID: +In-Reply-To: +References: +X-Bugzilla-URL: https://bugs.libre-soc.org/ +Auto-Submitted: auto-generated +MIME-Version: 1.0 +Subject: [libre-riscv-dev] [Bug 370] need a way to co-simulate hardware, qemu, + microwatt, simulator, side-by-side +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: text/plain; charset="utf-8" +Content-Transfer-Encoding: base64 +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + +aHR0cHM6Ly9idWdzLmxpYnJlLXNvYy5vcmcvc2hvd19idWcuY2dpP2lkPTM3MAoKLS0tIENvbW1l +bnQgIzMgZnJvbSBMdWtlIEtlbm5ldGggQ2Fzc29uIExlaWdodG9uIDxsa2NsQGxrY2wubmV0PiAt +LS0KcG93ZXJwYzY0LWxpbnV4LWdudS1nZGIgLWludGVycHJldGVyPW1pCn4tZGF0YS1saXN0LXJl +Z2lzdGVyLW5hbWVzCl5kb25lLHJlZ2lzdGVyLW5hbWVzPVsicjAiLCJyMSIsInIyIiwicjMiLCJy +NCIsInI1IiwicjYiLCJyNyIsInI4IiwicjkiLCJyMTAiLCJyMTEiLCJyMTIiLCJyMTMiLCJyMTQi +LCJyMTUiLCJyMTYiLCJyMTciLCJyMTgiLCJyMTkiLCJyMjAiLCJyMjEiLCJyMjIiLCJyMjMiLCJy +MjQiLCJyMjUiLCJyMjYiLCJyMjciLCJyMjgiLCJyMjkiLCJyMzAiLCJyMzEiLCJmMCIsImYxIiwi +ZjIiLCJmMyIsImY0IiwiZjUiLCJmNiIsImY3IiwiZjgiLCJmOSIsImYxMCIsImYxMSIsImYxMiIs +ImYxMyIsImYxNCIsImYxNSIsImYxNiIsImYxNyIsImYxOCIsImYxOSIsImYyMCIsImYyMSIsImYy +MiIsImYyMyIsImYyNCIsImYyNSIsImYyNiIsImYyNyIsImYyOCIsImYyOSIsImYzMCIsImYzMSIs +InBjIiwibXNyIiwiY25kIiwibHIiLCJjbnQiLCJ4ZXIiLCJmcHNjciIsIm1xIgoKdGhhdCBzaG91 +bGQgZG8gdGhlIHRyaWNrLiAgd2UgY2FuIGdldCBhdCBNU1IsIENSMC03IChjbmQpLCBYRVIsIFBD +LCBMUiwgY250IGlzCnByb2JhYmx5IENUUiwgbXEgaSBoYXZlIG5vIGlkZWEuCgotLSAKWW91IGFy +ZSByZWNlaXZpbmcgdGhpcyBtYWlsIGJlY2F1c2U6CllvdSBhcmUgb24gdGhlIENDIGxpc3QgZm9y +IHRoZSBidWcuCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f +CmxpYnJlLXJpc2N2LWRldiBtYWlsaW5nIGxpc3QKbGlicmUtcmlzY3YtZGV2QGxpc3RzLmxpYnJl +LXJpc2N2Lm9yZwpodHRwOi8vbGlzdHMubGlicmUtcmlzY3Yub3JnL21haWxtYW4vbGlzdGluZm8v +bGlicmUtcmlzY3YtZGV2Cg== +