From: Claudiu Zissulescu <claziss@synopsys.com>
Date: Mon, 1 Oct 2018 09:37:33 +0000 (+0200)
Subject: [ARC] Check for odd-even register when emitting double mac ops.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=97e1d32c5e6efdfac3a9d6c56e8127b958fff88f;p=gcc.git

[ARC] Check for odd-even register when emitting double mac ops.

gcc/
	Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (maddsidi4_split): Don't use dmac if the
	destination register is not odd-even.
	(umaddsidi4_split): Likewise.

gcc/testsuite/
	Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/tmac-3.c: New file.

From-SVN: r264736
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7783d0994e2..87730390518 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-10-01  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* config/arc/arc.md (maddsidi4_split): Don't use dmac if the
+	destination register is not odd-even.
+	(umaddsidi4_split): Likewise.
+
 2018-10-01  Richard Biener  <rguenther@suse.de>
 
 	* tree-inline.c (expand_call_inline): Store origin of fn
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 181a738f3ab..95cfa450888 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -6309,7 +6309,7 @@ archs4x, archs4xd, archs4xd_slow"
   "{
    rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
    emit_move_insn (acc_reg, operands[3]);
-   if (TARGET_PLUS_MACD)
+   if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode))
      emit_insn (gen_macd (operands[0], operands[1], operands[2]));
    else
      {
@@ -6409,7 +6409,7 @@ archs4x, archs4xd, archs4xd_slow"
   "{
    rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
    emit_move_insn (acc_reg, operands[3]);
-   if (TARGET_PLUS_MACD)
+   if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode))
      emit_insn (gen_macdu (operands[0], operands[1], operands[2]));
    else
      {
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 4dc292aded6..fe679c6bc6e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2018-10-01  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* gcc.target/arc/tmac-3.c: New file.
+
 2018-09-30  Paul Thomas  <pault@gcc.gnu.org>
 
 	PR fortran/87359
diff --git a/gcc/testsuite/gcc.target/arc/tmac-3.c b/gcc/testsuite/gcc.target/arc/tmac-3.c
new file mode 100644
index 00000000000..23ef173b890
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/tmac-3.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
+/* { dg-options "-mcpu=hs38 -Os" } */
+
+/* The compiler will assign r1r2 as a DI register, but it doesn't fit
+   the macd operation, hence we need to fall back on the mac
+   instruction.  */
+typedef long long myint64_t;
+
+extern int d (int, myint64_t);
+int b (int c)
+{
+  int x = (int) d;
+  d (c, (myint64_t)x * 2 + 1);
+}
+
+/* { dg-final { scan-assembler "mac\\\s+r1" } } */