From: Luke Kenneth Casson Leighton Date: Mon, 26 Apr 2021 09:19:26 +0000 (+0100) Subject: incorrect indentation in dcache rams X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=97e61ddac293bfd9537e9a6a8cd2c17c5e03c8d6;p=soc.git incorrect indentation in dcache rams --- diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index aea4a28b..b94a7cad 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1128,9 +1128,9 @@ class DCache(Elaboratable): comb += wr_addr.eq(r1.store_row) comb += wr_sel.eq(~0) # all 1s - with m.If((r1.state == State.RELOAD_WAIT_ACK) - & wb_in.ack & (replace_way == i)): - comb += do_write.eq(1) + with m.If((r1.state == State.RELOAD_WAIT_ACK) + & wb_in.ack & (replace_way == i)): + comb += do_write.eq(1) # Mask write selects with do_write since BRAM # doesn't have a global write-enable