From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 23 May 2020 17:50:57 +0000 (+0100)
Subject: split out RegSpec API into separate class (TODO: move to separate file)
X-Git-Tag: div_pipeline~907
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=97f1169aa91bc8a69102c36178bdffe9e60f5485;p=soc.git

split out RegSpec API into separate class (TODO: move to separate file)
---

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 3e41739c..fe42f07d 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -154,7 +154,35 @@ class CompUnitRecord(RecordObject):
         return get_regspec_bitwidth(self._rwid, 0, i)
 
 
-class MultiCompUnit(Elaboratable):
+class RegSpecALUAPI:
+    def __init__(self, rwid, alu):
+        """RegSpecAPI
+
+        * :rwid:       regspec
+        * :alu:        ALU covered by this regspec
+        """
+        self.rwid = rwid
+        self.alu = alu # actual ALU - set as a "submodule" of the CU
+
+    def get_out(self, i):
+        if isinstance(self.rwid, int): # old - testing - API (rwid is int)
+            return self.alu.out[i]
+        # regspec-based API: look up variable through regspec according to row number
+        return getattr(self.alu.n.data_o, self.rwid[1][i][1])
+
+    def get_in(self, i):
+        if isinstance(self.rwid, int): # old - testing - API (rwid is int)
+            return self.alu.i[i]
+        # regspec-based API: look up variable through regspec according to row number
+        return getattr(self.alu.p.data_i, self.rwid[0][i][1])
+
+    def get_op(self):
+        if isinstance(self.rwid, int): # old - testing - API (rwid is int)
+            return self.alu.op
+        return self.alu.p.data_i.ctx.op
+
+
+class MultiCompUnit(RegSpecALUAPI, Elaboratable):
     def __init__(self, rwid, alu, opsubsetkls, n_src=2, n_dst=1):
         """MultiCompUnit
 
@@ -164,10 +192,9 @@ class MultiCompUnit(Elaboratable):
         * :n_src:       number of src operands
         * :n_dst:       number of destination operands
         """
+        RegSpecALUAPI.__init__(self, rwid, alu)
         self.n_src, self.n_dst = n_src, n_dst
-        self.rwid = rwid
         self.opsubsetkls = opsubsetkls
-        self.alu = alu # actual ALU - set as a "submodule" of the CU
         self.cu = cu = CompUnitRecord(opsubsetkls, rwid, n_src, n_dst)
 
         for i in range(n_src):
@@ -200,22 +227,6 @@ class MultiCompUnit(Elaboratable):
         self.data_o = self.dest[0] # Dest out
         self.done_o = cu.done_o
 
-    def get_out(self, i):
-        if isinstance(self.rwid, int): # old - testing - API (rwid is int)
-            return self.alu.out[i]
-        # regspec-based API: look up variable through regspec according to row number
-        return getattr(self.alu.n.data_o, self.rwid[1][i][1])
-
-    def get_in(self, i):
-        if isinstance(self.rwid, int): # old - testing - API (rwid is int)
-            return self.alu.i[i]
-        # regspec-based API: look up variable through regspec according to row number
-        return getattr(self.alu.p.data_i, self.rwid[0][i][1])
-
-    def get_op(self):
-        if isinstance(self.rwid, int): # old - testing - API (rwid is int)
-            return self.alu.op
-        return self.alu.p.data_i.ctx.op
     def elaborate(self, platform):
         m = Module()
         m.submodules.alu = self.alu