From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Fri, 27 Oct 2023 10:34:45 +0000 (+0100)
Subject: added english language description for lwasx instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=97fc0395c0a869c3120712bc857b0b00680dc50e;p=openpower-isa.git

added english language description for lwasx instruction
---

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index 903019cd..8e61cdbd 100644
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -230,7 +230,6 @@ Description:
 
     If RA=0 or RA=RT, the instruction form is invalid.
 
-
 Special Registers Altered:
 
     None
@@ -247,6 +246,14 @@ Pseudo-code:
     EA <- b + (RB) << (SH+1)
     RT <- EXTS(MEM(EA, 4))
 
+Description:
+
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and (RA|0).
+
+    The word in storage addressed by EA is loaded into RT[32:63].
+    RT[0:31] are filled with a copy of bit 0 of the loaded word.
+
 Special Registers Altered:
 
     None