From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 17 Oct 2019 15:24:53 +0000 (+0200)
Subject: Make equivalence work with latest master
X-Git-Tag: working-ls180~990^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=980df499abb63e5dfadc29b3326032b55b6dbf18;p=yosys.git

Make equivalence work with latest master
---

diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 2d23749ac..9e8ba44ab 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 proc
 hierarchy -top adff
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -15,7 +15,7 @@ select -assert-none t:BUFG t:FDCE %% t:* %D
 design -load read
 proc
 hierarchy -top adffn
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -28,7 +28,7 @@ select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
 design -load read
 proc
 hierarchy -top dffs
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -41,7 +41,7 @@ select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
 design -load read
 proc
 hierarchy -top ndffnr
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys
index 3bb3a8eb0..459541656 100644
--- a/tests/xilinx/counter.ys
+++ b/tests/xilinx/counter.ys
@@ -2,7 +2,7 @@ read_verilog counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 68ca42b10..52e96834d 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -3,7 +3,7 @@ design -save read
 
 proc
 hierarchy -top latchp
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE
@@ -14,7 +14,7 @@ select -assert-none t:LDCE %% t:* %D
 design -load read
 proc
 hierarchy -top latchn
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE
@@ -26,7 +26,7 @@ select -assert-none t:LDCE t:LUT1 %% t:* %D
 design -load read
 proc
 hierarchy -top latchsr
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE