From: Connor Abbott <cwabbott0@gmail.com>
Date: Thu, 16 Jul 2020 13:48:41 +0000 (+0200)
Subject: freedreno/a6xx: Add stencilref register info
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=981608ad04ce36dec6d1b551cd5bc550b4ca5cb8;p=mesa.git

freedreno/a6xx: Add stencilref register info

Found by guessing.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5936>
---

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index 63e8e01058f..2124d8e3a2f 100644
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -2211,7 +2211,7 @@ to upconvert to 32b float internally?
 		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
 		<bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
 		<bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
-		<bitfield name="UNK3" pos="3" type="boolean"/>
+		<bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/>
 	</reg32>
 	<reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
 		<bitfield name="MRT" low="0" high="3" type="uint"/>
@@ -3203,6 +3203,7 @@ to upconvert to 32b float internally?
 		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
 		<bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
 		<bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
+		<bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/>
 	</reg32>
 	<reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
 		<bitfield name="MRT" low="0" high="3" type="uint"/>