From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 19:43:19 +0000 (-0700)
Subject: Consistency
X-Git-Tag: working-ls180~1003^2~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=983068103e24c33a1b70eb90dd72fdfaf292e1bd;p=yosys.git

Consistency
---

diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg
index a20d3cdce..38a5a8d24 100644
--- a/passes/pmgen/xilinx_dsp_CREG.pmg
+++ b/passes/pmgen/xilinx_dsp_CREG.pmg
@@ -45,7 +45,7 @@ match dsp
 	select nusers(port(dsp, \C, SigSpec())) > 1
 endmatch
 
-code sigC sigP
+code sigC sigP clock
 	unextend = [](const SigSpec &sig) {
 		int i;
 		for (i = GetSize(sig)-1; i > 0; i--)
@@ -71,6 +71,8 @@ code sigC sigP
 	}
 	else
 		sigP = P;
+
+	clock = port(dsp, \CLK, SigBit());
 endcode
 
 // (2) Match the driver of the 'C' input to a possible $dff cell (CREG)
@@ -82,8 +84,6 @@ code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
 	if (sigC == sigP)
 		reject;
 
-	clock = port(dsp, \CLK, SigBit());
-
 	argQ = sigC;
 	subpattern(in_dffe);
 	if (dff) {