From: Andreas Hansson Date: Mon, 2 Mar 2015 09:00:37 +0000 (-0500) Subject: mem: Tidy up the cache debug messages X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=987de4f5ccc5639ca03cc3c90e48bc06b5429823;p=gem5.git mem: Tidy up the cache debug messages Avoid redundant inclusion of the name in the DPRINTF string. --- diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc index cf55b8591..b474aeedc 100644 --- a/src/mem/cache/base.cc +++ b/src/mem/cache/base.cc @@ -92,13 +92,13 @@ void BaseCache::CacheSlavePort::setBlocked() { assert(!blocked); - DPRINTF(CachePort, "Cache port %s blocking new requests\n", name()); + DPRINTF(CachePort, "Port is blocking new requests\n"); blocked = true; // if we already scheduled a retry in this cycle, but it has not yet // happened, cancel it if (sendRetryEvent.scheduled()) { owner.deschedule(sendRetryEvent); - DPRINTF(CachePort, "Cache port %s deschedule retry\n", name()); + DPRINTF(CachePort, "Port descheduled retry\n"); mustSendRetry = true; } } @@ -107,10 +107,10 @@ void BaseCache::CacheSlavePort::clearBlocked() { assert(blocked); - DPRINTF(CachePort, "Cache port %s accepting new requests\n", name()); + DPRINTF(CachePort, "Port is accepting new requests\n"); blocked = false; if (mustSendRetry) { - // @TODO: need to find a better time (next bus cycle?) + // @TODO: need to find a better time (next cycle?) owner.schedule(sendRetryEvent, curTick() + 1); } } @@ -118,7 +118,7 @@ BaseCache::CacheSlavePort::clearBlocked() void BaseCache::CacheSlavePort::processSendRetry() { - DPRINTF(CachePort, "Cache port %s sending retry\n", name()); + DPRINTF(CachePort, "Port is sending retry\n"); // reset the flag and call retry mustSendRetry = false; diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh index bda3df34a..cd2f55246 100644 --- a/src/mem/cache/base.hh +++ b/src/mem/cache/base.hh @@ -129,7 +129,8 @@ class BaseCache : public MemObject */ void requestBus(RequestCause cause, Tick time) { - DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); + DPRINTF(CachePort, "Scheduling request at %llu due to %d\n", + time, cause); reqQueue.schedSendEvent(time); } diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 803b3bad8..32eae66d9 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -261,8 +261,7 @@ Cache::markInService(MSHR *mshr, bool pending_dirty_resp) markInServiceInternal(mshr, pending_dirty_resp); #if 0 if (mshr->originalCmd == MemCmd::HardPFReq) { - DPRINTF(HWPrefetch, "%s:Marking a HW_PF in service\n", - name()); + DPRINTF(HWPrefetch, "Marking a HW_PF in service\n"); //Also clear pending if need be if (!prefetcher->havePending()) { @@ -324,10 +323,10 @@ Cache::access(PacketPtr pkt, BlkType *&blk, // that can modify its value. blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id); - DPRINTF(Cache, "%s%s %x (%s) %s %s\n", pkt->cmdString(), + DPRINTF(Cache, "%s%s %x (%s) %s\n", pkt->cmdString(), pkt->req->isInstFetch() ? " (ifetch)" : "", pkt->getAddr(), pkt->isSecure() ? "s" : "ns", - blk ? "hit" : "miss", blk ? blk->print() : ""); + blk ? "hit " + blk->print() : "miss"); // Writeback handling is special case. We can write the block into // the cache without having a writeable copy (or any copy at all).