From: Luke Kenneth Casson Leighton Date: Thu, 13 May 2021 19:01:20 +0000 (+0100) Subject: fix wb_get error where data was being corrupted X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9885585d097ca1f26283fa9dc0f22a4fa7bc026c;p=soc.git fix wb_get error where data was being corrupted (not WB classic compliant) --- diff --git a/src/soc/experiment/test/test_ldst_pi.py b/src/soc/experiment/test/test_ldst_pi.py index c529372a..8688bd94 100644 --- a/src/soc/experiment/test/test_ldst_pi.py +++ b/src/soc/experiment/test/test_ldst_pi.py @@ -79,13 +79,14 @@ def wb_get(wb): yield wb.ack.eq(1) yield yield wb.ack.eq(0) + yield def mmu_lookup(dut, addr): mmu = dut.submodules.mmu global stop - print("pi_ld") + print("pi_ld", hex(addr)) data = yield from pi_ld(dut.submodules.ldst.pi, addr, 4, msr_pr=1) print("pi_ld done, data", hex(data)) """ @@ -123,20 +124,30 @@ def ldst_sim(dut): yield mmu.rin.prtbl.eq(0x1000000) # set process table yield + # expecting this data to return + # 0x1000: 0xdeadbeef01234567, + # 0x1008: 0xfeedf00ff001a5a5 + addr = 0x1000 print("pi_ld") # TODO mmu_lookup using port interface # set inputs - phys_addr = yield from mmu_lookup(dut, addr) - #assert phys_addr == addr # happens to be the same (for this example) + data = yield from mmu_lookup(dut, addr) + assert data == 0x1234567 - phys_addr = yield from mmu_lookup(dut, addr) + data = yield from mmu_lookup(dut, addr+8) + assert data == 0xf001a5a5 #assert phys_addr == addr # happens to be the same (for this example) - phys_addr = yield from mmu_lookup(dut, addr+4) + data = yield from mmu_lookup(dut, addr+4) + assert data == 0xdeadbeef - phys_addr = yield from mmu_lookup(dut, addr+8) + data = yield from mmu_lookup(dut, addr+8) + assert data == 0xf001a5a5 + + yield + yield stop = True diff --git a/src/soc/experiment/test/test_mmu_dcache.py b/src/soc/experiment/test/test_mmu_dcache.py index 0748a05a..1528d7d4 100644 --- a/src/soc/experiment/test/test_mmu_dcache.py +++ b/src/soc/experiment/test/test_mmu_dcache.py @@ -89,6 +89,7 @@ def wb_get(c, mem, name): yield c.wb_in.ack.eq(1) yield yield c.wb_in.ack.eq(0) + yield def icache_sim(dut, mem): diff --git a/src/soc/experiment/test/test_mmu_dcache_pi.py b/src/soc/experiment/test/test_mmu_dcache_pi.py index 35d58081..2f219e63 100644 --- a/src/soc/experiment/test/test_mmu_dcache_pi.py +++ b/src/soc/experiment/test/test_mmu_dcache_pi.py @@ -170,6 +170,7 @@ def wb_get(dc): yield dc.wb_in.ack.eq(1) yield yield dc.wb_in.ack.eq(0) + yield def mmu_lookup(dut, addr):