From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 23 Apr 2020 00:50:30 +0000 (-0700)
Subject: tests: read +/xilinx/cell_sim.v before xilinx_dsp test
X-Git-Tag: working-ls180~594^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=988d47af8533a0c7728095862dbc6a7311c1f8b7;p=yosys.git

tests: read +/xilinx/cell_sim.v before xilinx_dsp test
---

diff --git a/tests/arch/xilinx/xilinx_dsp.ys b/tests/arch/xilinx/xilinx_dsp.ys
index 3b9f52930..59d8296ab 100644
--- a/tests/arch/xilinx/xilinx_dsp.ys
+++ b/tests/arch/xilinx/xilinx_dsp.ys
@@ -8,4 +8,5 @@ assign o4 = a * b;
 DSP48E1 m3 (.A(a), .B(b), .P(o5));
 endmodule
 EOT
+read_verilog -lib +/xilinx/cells_sim.v
 xilinx_dsp