From: Benjamin Herrenschmidt Date: Thu, 31 Oct 2019 08:43:58 +0000 (+1100) Subject: control: Reduce pipeline depth to 1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=98bd8b73c0e2c545ef3f100f1754c7fff47ad57a;p=microwatt.git control: Reduce pipeline depth to 1 To match our one stage execute. This might change back if we end up adding 2 stages to match the LSU, but in that case we'll want forwards as well. Signed-off-by: Benjamin Herrenschmidt --- diff --git a/control.vhdl b/control.vhdl index 44c6374..0555b06 100644 --- a/control.vhdl +++ b/control.vhdl @@ -57,7 +57,7 @@ architecture rtl of control is begin gpr_hazard0: entity work.gpr_hazard generic map ( - PIPELINE_DEPTH => 2 + PIPELINE_DEPTH => PIPELINE_DEPTH ) port map ( clk => clk, @@ -72,7 +72,7 @@ begin gpr_hazard1: entity work.gpr_hazard generic map ( - PIPELINE_DEPTH => 2 + PIPELINE_DEPTH => PIPELINE_DEPTH ) port map ( clk => clk, @@ -87,7 +87,7 @@ begin gpr_hazard2: entity work.gpr_hazard generic map ( - PIPELINE_DEPTH => 2 + PIPELINE_DEPTH => PIPELINE_DEPTH ) port map ( clk => clk, @@ -102,7 +102,7 @@ begin cr_hazard0: entity work.cr_hazard generic map ( - PIPELINE_DEPTH => 2 + PIPELINE_DEPTH => PIPELINE_DEPTH ) port map ( clk => clk, diff --git a/decode2.vhdl b/decode2.vhdl index c8dee48..1307e7d 100644 --- a/decode2.vhdl +++ b/decode2.vhdl @@ -152,7 +152,7 @@ architecture behaviour of decode2 is begin control_0: entity work.control generic map ( - PIPELINE_DEPTH => 2 + PIPELINE_DEPTH => 1 ) port map ( clk => clk,