From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 19:44:10 +0000 (-0700)
Subject: ABC to read_box before reading netlist
X-Git-Tag: working-ls180~1208^2~338
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=98c297fabfb960beadedaccf7cc9f765f20e044b;p=yosys.git

ABC to read_box before reading netlist
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index fbf3a47ee..f5f7add9a 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -322,7 +322,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 	log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
 			module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
 
-	std::string abc_script = stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str());
+	std::string abc_script;
 
 	if (!liberty_file.empty()) {
 		abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
@@ -343,6 +343,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 	else
 		abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
 
+	abc_script += stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str());
+
 	if (!script_file.empty()) {
 		if (script_file[0] == '+') {
 			for (size_t i = 1; i < script_file.size(); i++)