From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Thu, 4 Feb 2021 11:12:59 +0000 (+0100)
Subject: Add check of begin/end labels for genblock
X-Git-Tag: working-ls180~92^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=98c4feb72ff52f12aadd34b0deccb819d701ff2c;p=yosys.git

Add check of begin/end labels for genblock

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 6255a4204..fb5846f7b 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2794,6 +2794,8 @@ gen_block:
 		ast_stack.push_back(node);
 	} module_gen_body TOK_END opt_label {
 		exitTypeScope();
+		if ($3 != NULL && $7 != NULL && *$3 != *$7)
+			frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1);
 		delete $3;
 		delete $7;
 		SET_AST_NODE_LOC(ast_stack.back(), @1, @7);
diff --git a/tests/verilog/block_labels.ys b/tests/verilog/block_labels.ys
new file mode 100644
index 000000000..e76bcf771
--- /dev/null
+++ b/tests/verilog/block_labels.ys
@@ -0,0 +1,26 @@
+read_verilog <<EOT
+module foo;
+
+	genvar a = 0;
+	for (a = 0; a < 10; a++) begin : a
+	end : a
+endmodule
+EOT
+read_verilog <<EOT
+module foo2;
+
+	genvar a = 0;
+	for (a = 0; a < 10; a++) begin : a
+	end
+endmodule
+EOT
+
+logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1
+read_verilog <<EOT
+module foo3;
+
+	genvar a = 0;
+	for (a = 0; a < 10; a++) begin : a
+	end : b
+endmodule
+EOT