From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 7 Dec 2019 01:05:02 +0000 (-0800)
Subject: techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
X-Git-Tag: working-ls180~913^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=98c9ea605b5cb2eb540ae5b804a18f8921f0bc46;p=yosys.git

techmap/aigmap of whiteboxes to occur before abc9 instead of in write_xaiger
---

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 4cbb56ea1..b099c25d3 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -312,6 +312,11 @@ struct SynthEcp5Pass : public ScriptPass
 			run("techmap " + techmap_args);
 
 			if (abc9) {
+				run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
+				run("wbflip @abc9_boxes");
+				run("techmap -autoproc @abc9_boxes");
+				run("aigmap @abc9_boxes");
+				run("wbflip @abc9_boxes");
 				run("read_verilog -icells -lib +/ecp5/abc9_model.v");
 				if (nowidelut)
 					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs");
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 901194b06..2f0bdb130 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -350,6 +350,11 @@ struct SynthIce40Pass : public ScriptPass
 			}
 			if (!noabc) {
 				if (abc == "abc9") {
+					run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
+					run("wbflip @abc9_boxes");
+					run("techmap -autoproc @abc9_boxes");
+					run("aigmap @abc9_boxes");
+					run("wbflip @abc9_boxes");
 					run("read_verilog -icells -lib +/ice40/abc9_model.v");
 					int wire_delay;
 					if (device_opt == "lp")
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 2c5686a35..8c30148c0 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -533,6 +533,11 @@ struct SynthXilinxPass : public ScriptPass
 					log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
 							"will use timing for 'xc7' instead.\n", family.c_str());
 				run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
+				run("select -set abc9_boxes A:abc9_box_id A:whitebox=1");
+				run("wbflip @abc9_boxes");
+				run("techmap -autoproc @abc9_boxes");
+				run("aigmap @abc9_boxes");
+				run("wbflip @abc9_boxes");
 				run("read_verilog -icells -lib +/xilinx/abc9_model.v");
 				std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
 				abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);