From: Luke Kenneth Casson Leighton Date: Sun, 5 Jul 2020 12:22:56 +0000 (+0000) Subject: add SPR pipeline (but not DIV for now) X-Git-Tag: partial-core-ls180-gdsii~106 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=98cff9b0fffe05dd015b4f688640c66c6a42dd74;p=soclayout.git add SPR pipeline (but not DIV for now) --- diff --git a/experiments9/non_generated/test_issuer.il b/experiments9/non_generated/test_issuer.il index 6c7e903..1dbe32a 100644 --- a/experiments9/non_generated/test_issuer.il +++ b/experiments9/non_generated/test_issuer.il @@ -4,18 +4,19 @@ module \dec19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -232,57 +233,57 @@ module \dec19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257" wire width 5 \opcode_switch$1 process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'0000000000 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'0100000001 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'0010000001 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'0100100001 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'0011100001 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'0000100001 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'0111000001 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'0110100001 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'0011000001 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'1000010000 - assign \function_unit 10'0000100000 + assign \function_unit 11'00000100000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'0000010000 - assign \function_unit 10'0000100000 + assign \function_unit 11'00000100000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'1000110000 - assign \function_unit 10'0000100000 + assign \function_unit 11'00000100000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'0010010110 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 10'0000010010 - assign \function_unit 10'0010000000 + assign \function_unit 11'00010000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00010 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 end sync init end @@ -1557,18 +1558,19 @@ module \dec30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -1783,39 +1785,39 @@ module \dec30 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 4'0100 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 4'0101 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 4'0000 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 4'0001 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 4'0010 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 4'0011 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 4'0110 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 4'0111 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 4'1000 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 4'1001 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 end sync init end @@ -2677,18 +2679,19 @@ module \dec_sub10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -2903,39 +2906,39 @@ module \dec_sub10 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01000 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11000 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10000 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00100 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10100 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00111 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10111 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00110 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10110 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 end sync init end @@ -3797,18 +3800,19 @@ module \dec_sub28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -4023,39 +4027,39 @@ module \dec_sub28 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00001 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00111 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01111 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01000 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01110 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00011 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01101 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01100 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01001 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 end sync init end @@ -4917,18 +4921,19 @@ module \dec_sub0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -5143,21 +5148,21 @@ module \dec_sub0 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00111 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00001 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00100 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 end sync init end @@ -5605,18 +5610,19 @@ module \dec_sub26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -5831,51 +5837,51 @@ module \dec_sub26 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00001 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10001 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10000 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11101 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11100 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11110 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00011 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01111 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01011 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00101 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00100 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11000 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11001 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 end sync init end @@ -7013,18 +7019,19 @@ module \dec_sub19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -7239,21 +7246,21 @@ module \dec_sub19 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00010 - assign \function_unit 10'0000000010 + assign \function_unit 11'00010000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01010 - assign \function_unit 10'0000000010 + assign \function_unit 11'10000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01110 - assign \function_unit 10'0000000010 + assign \function_unit 11'10000000000 end sync init end @@ -7701,18 +7708,19 @@ module \dec_sub22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -7927,54 +7935,54 @@ module \dec_sub22 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00010 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00001 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01000 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00111 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11110 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11000 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10000 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10101 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00110 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11100 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10110 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10100 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00100 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10010 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 end sync init end @@ -9181,18 +9189,19 @@ module \dec_sub9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -9407,57 +9416,57 @@ module \dec_sub9 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01100 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11100 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01101 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11101 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01110 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11110 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01111 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11111 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01000 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11000 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00010 - assign \function_unit 10'0100000000 + assign \function_unit 11'00100000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0100000000 + assign \function_unit 11'00100000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10010 - assign \function_unit 10'0100000000 + assign \function_unit 11'00100000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10000 - assign \function_unit 10'0100000000 + assign \function_unit 11'00100000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00111 - assign \function_unit 10'0100000000 + assign \function_unit 11'00100000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10111 - assign \function_unit 10'0100000000 + assign \function_unit 11'00100000000 end sync init end @@ -10733,18 +10742,19 @@ module \dec_sub11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -10959,57 +10969,57 @@ module \dec_sub11 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01100 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11100 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01101 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11101 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01110 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11110 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01111 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11111 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01000 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11000 - assign \function_unit 10'1000000000 + assign \function_unit 11'01000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00010 - assign \function_unit 10'0100000000 + assign \function_unit 11'00100000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0100000000 + assign \function_unit 11'00100000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10010 - assign \function_unit 10'0100000000 + assign \function_unit 11'00100000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10000 - assign \function_unit 10'0100000000 + assign \function_unit 11'00100000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00111 - assign \function_unit 10'0100000000 + assign \function_unit 11'00100000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10111 - assign \function_unit 10'0100000000 + assign \function_unit 11'00100000000 end sync init end @@ -12285,18 +12295,19 @@ module \dec_sub27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -12511,18 +12522,18 @@ module \dec_sub27 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11001 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10000 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 end sync init end @@ -12901,18 +12912,19 @@ module \dec_sub15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -13127,105 +13139,105 @@ module \dec_sub15 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00001 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00010 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00011 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00100 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00101 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00110 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00111 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01000 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01001 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01010 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01011 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01100 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01101 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01110 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01111 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10000 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10001 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10010 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10011 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10100 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10101 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10110 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10111 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11000 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11001 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11010 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11011 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11100 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11101 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11110 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11111 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 end sync init end @@ -15605,18 +15617,19 @@ module \dec_sub20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -15831,27 +15844,27 @@ module \dec_sub20 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00001 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00010 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10000 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00011 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10100 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 end sync init end @@ -16437,18 +16450,19 @@ module \dec_sub23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -16663,51 +16677,51 @@ module \dec_sub23 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00011 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00010 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01011 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01010 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01001 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01000 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00001 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00111 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00110 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01101 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01100 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00101 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00100 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 end sync init end @@ -17845,18 +17859,19 @@ module \dec_sub21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -18071,27 +18086,27 @@ module \dec_sub21 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00001 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01011 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'01010 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00101 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00100 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 end sync init end @@ -18677,18 +18692,19 @@ module \dec_sub16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -18903,12 +18919,12 @@ module \dec_sub16 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00100 - assign \function_unit 10'0001000000 + assign \function_unit 11'00001000000 end sync init end @@ -19149,18 +19165,19 @@ module \dec_sub18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -19373,12 +19390,12 @@ module \dec_sub18 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00101 - assign \function_unit 10'0000000010 + assign \function_unit 11'00010000000 end sync init end @@ -19609,18 +19626,19 @@ module \dec_sub8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -19835,45 +19853,45 @@ module \dec_sub8 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00011 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10011 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00001 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10001 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10000 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00100 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10100 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00111 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10111 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00110 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10110 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 end sync init end @@ -20873,18 +20891,19 @@ module \dec_sub24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -21099,21 +21118,21 @@ module \dec_sub24 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11000 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'11001 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'10000 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 end sync init end @@ -21561,18 +21580,19 @@ module \dec_sub4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -21787,15 +21807,15 @@ module \dec_sub4 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00010 - assign \function_unit 10'0010000000 + assign \function_unit 11'00010000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 5'00000 - assign \function_unit 10'0010000000 + assign \function_unit 11'00010000000 end sync init end @@ -22105,18 +22125,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -22326,18 +22347,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub10_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub10_function_unit + wire width 11 \dec_sub10_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -22574,18 +22596,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub28_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub28_function_unit + wire width 11 \dec_sub28_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -22822,18 +22845,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub0_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub0_function_unit + wire width 11 \dec_sub0_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -23070,18 +23094,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub26_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub26_function_unit + wire width 11 \dec_sub26_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -23318,18 +23343,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub19_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub19_function_unit + wire width 11 \dec_sub19_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -23566,18 +23592,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub22_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub22_function_unit + wire width 11 \dec_sub22_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -23814,18 +23841,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub9_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub9_function_unit + wire width 11 \dec_sub9_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -24062,18 +24090,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub11_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub11_function_unit + wire width 11 \dec_sub11_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -24310,18 +24339,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub27_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub27_function_unit + wire width 11 \dec_sub27_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -24558,18 +24588,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub15_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub15_function_unit + wire width 11 \dec_sub15_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -24806,18 +24837,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub20_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub20_function_unit + wire width 11 \dec_sub20_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -25054,18 +25086,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub23_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub23_function_unit + wire width 11 \dec_sub23_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -25302,18 +25335,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub21_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub21_function_unit + wire width 11 \dec_sub21_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -25550,18 +25584,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub16_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub16_function_unit + wire width 11 \dec_sub16_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -25798,18 +25833,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub18_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub18_function_unit + wire width 11 \dec_sub18_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -26043,18 +26079,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub8_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub8_function_unit + wire width 11 \dec_sub8_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -26291,18 +26328,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub24_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub24_function_unit + wire width 11 \dec_sub24_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -26539,18 +26577,19 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec_sub4_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec_sub4_function_unit + wire width 11 \dec_sub4_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -26889,7 +26928,7 @@ module \dec31 sync init end process $group_20 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264" switch \opc_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274" @@ -28362,18 +28401,19 @@ module \dec58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -28588,18 +28628,18 @@ module \dec58 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 2'00 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 2'01 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 2'10 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 end sync init end @@ -28978,18 +29018,19 @@ module \dec62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 input 0 \opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 1 \function_unit + wire width 11 output 1 \function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -29204,15 +29245,15 @@ module \dec62 sync init end process $group_1 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 2'00 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 2'01 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 end sync init end @@ -29588,18 +29629,19 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" wire width 3 output 9 \cr_out attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 10 \function_unit + wire width 11 output 10 \function_unit attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -29797,18 +29839,19 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec19_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec19_function_unit + wire width 11 \dec19_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -30045,18 +30088,19 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec30_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec30_function_unit + wire width 11 \dec30_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -30293,18 +30337,19 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec31_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec31_function_unit + wire width 11 \dec31_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -30541,18 +30586,19 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec58_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec58_function_unit + wire width 11 \dec58_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -30789,18 +30835,19 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" wire width 32 \dec62_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 \dec62_function_unit + wire width 11 \dec62_function_unit attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -31069,7 +31116,7 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257" wire width 32 \opcode_switch$1 process $group_6 - assign \function_unit 10'0000000000 + assign \function_unit 11'00000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299" @@ -31089,124 +31136,124 @@ module \dec assign \function_unit \dec62_function_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'001100 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'001101 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'001110 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'001111 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'010001 - assign \function_unit 10'0010000000 + assign \function_unit 11'00010000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'011100 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'011101 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'010010 - assign \function_unit 10'0000100000 + assign \function_unit 11'00000100000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'010000 - assign \function_unit 10'0000100000 + assign \function_unit 11'00000100000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'001011 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'001010 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'100010 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'100011 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'101010 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'101011 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'101000 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'101001 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'100000 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'100001 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'000111 - assign \function_unit 10'0100000000 + assign \function_unit 11'00100000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'011000 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'011001 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'010100 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'010101 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'010111 - assign \function_unit 10'0000001000 + assign \function_unit 11'00000001000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'100110 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'100111 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'101100 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'101101 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'100100 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'100101 - assign \function_unit 10'0000000100 + assign \function_unit 11'00000000100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'001000 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'000010 - assign \function_unit 10'0010000000 + assign \function_unit 11'00010000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'000011 - assign \function_unit 10'0010000000 + assign \function_unit 11'00010000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'011010 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 6'011011 - assign \function_unit 10'0000010000 + assign \function_unit 11'00000010000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279" switch \opcode_switch$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 32'000000---------------0100000000- - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 32'01100000000000000000000000000000 - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288" case 32'000001---------------0000000011- - assign \function_unit 10'0000000010 + assign \function_unit 11'00000000010 end sync init end @@ -36729,6 +36776,462 @@ module \dec end end attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_a.sprmap" +module \sprmap + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 input 0 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" + wire width 10 output 1 \spr_o + process $group_0 + assign \spr_o 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:64" + switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000000001 + assign \spr_o 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000000011 + assign \spr_o 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000001000 + assign \spr_o 10'0000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000001001 + assign \spr_o 10'0000000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000001101 + assign \spr_o 10'0000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000010001 + assign \spr_o 10'0000000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000010010 + assign \spr_o 10'0000000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000010011 + assign \spr_o 10'0000000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000010110 + assign \spr_o 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000011010 + assign \spr_o 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000011011 + assign \spr_o 10'0000001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000011100 + assign \spr_o 10'0000001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000011101 + assign \spr_o 10'0000001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000110000 + assign \spr_o 10'0000001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000111101 + assign \spr_o 10'0000001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010000000 + assign \spr_o 10'0000001111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010000001 + assign \spr_o 10'0000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010000010 + assign \spr_o 10'0000010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010000011 + assign \spr_o 10'0000010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010001000 + assign \spr_o 10'0000010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010010000 + assign \spr_o 10'0000010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010011000 + assign \spr_o 10'0000010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010011001 + assign \spr_o 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010011101 + assign \spr_o 10'0000010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010011110 + assign \spr_o 10'0000011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010011111 + assign \spr_o 10'0000011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010110000 + assign \spr_o 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010110100 + assign \spr_o 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010111010 + assign \spr_o 10'0000011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010111011 + assign \spr_o 10'0000011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010111100 + assign \spr_o 10'0000011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010111110 + assign \spr_o 10'0000011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100000000 + assign \spr_o 10'0000100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100000011 + assign \spr_o 10'0000100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100001100 + assign \spr_o 10'0000100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100001101 + assign \spr_o 10'0000100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100010000 + assign \spr_o 10'0000100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100010001 + assign \spr_o 10'0000100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100010010 + assign \spr_o 10'0000100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100010011 + assign \spr_o 10'0000100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100011011 + assign \spr_o 10'0000101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100011100 + assign \spr_o 10'0000101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100011101 + assign \spr_o 10'0000101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100011110 + assign \spr_o 10'0000101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100011111 + assign \spr_o 10'0000101100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110000 + assign \spr_o 10'0000101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110001 + assign \spr_o 10'0000101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110010 + assign \spr_o 10'0000101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110011 + assign \spr_o 10'0000110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110100 + assign \spr_o 10'0000110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110101 + assign \spr_o 10'0000110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110110 + assign \spr_o 10'0000110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100111001 + assign \spr_o 10'0000110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100111010 + assign \spr_o 10'0000110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100111011 + assign \spr_o 10'0000110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100111110 + assign \spr_o 10'0000110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100111111 + assign \spr_o 10'0000111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0101010000 + assign \spr_o 10'0000111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0101010001 + assign \spr_o 10'0000111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0101010010 + assign \spr_o 10'0000111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0101010011 + assign \spr_o 10'0000111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0101011101 + assign \spr_o 10'0000111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0110111110 + assign \spr_o 10'0000111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0111010000 + assign \spr_o 10'0000111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000000 + assign \spr_o 10'0001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000001 + assign \spr_o 10'0001000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000010 + assign \spr_o 10'0001000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000011 + assign \spr_o 10'0001000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000100 + assign \spr_o 10'0001000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000101 + assign \spr_o 10'0001000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000110 + assign \spr_o 10'0001000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000111 + assign \spr_o 10'0001000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100001000 + assign \spr_o 10'0001001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100001011 + assign \spr_o 10'0001001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100001100 + assign \spr_o 10'0001001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100001101 + assign \spr_o 10'0001001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100001110 + assign \spr_o 10'0001001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010000 + assign \spr_o 10'0001001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010001 + assign \spr_o 10'0001001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010010 + assign \spr_o 10'0001001111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010011 + assign \spr_o 10'0001010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010100 + assign \spr_o 10'0001010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010101 + assign \spr_o 10'0001010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010110 + assign \spr_o 10'0001010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010111 + assign \spr_o 10'0001010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100011000 + assign \spr_o 10'0001010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100011011 + assign \spr_o 10'0001010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100011100 + assign \spr_o 10'0001010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100011101 + assign \spr_o 10'0001011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100011110 + assign \spr_o 10'0001011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100000 + assign \spr_o 10'0001011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100001 + assign \spr_o 10'0001011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100010 + assign \spr_o 10'0001011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100011 + assign \spr_o 10'0001011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100100 + assign \spr_o 10'0001011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100101 + assign \spr_o 10'0001011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100110 + assign \spr_o 10'0001100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100101000 + assign \spr_o 10'0001100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100101001 + assign \spr_o 10'0001100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100101010 + assign \spr_o 10'0001100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100101011 + assign \spr_o 10'0001100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100101111 + assign \spr_o 10'0001100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100110000 + assign \spr_o 10'0001100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100110111 + assign \spr_o 10'0001100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1101010000 + assign \spr_o 10'0001101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1101010001 + assign \spr_o 10'0001101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1101010111 + assign \spr_o 10'0001101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1110000000 + assign \spr_o 10'0001101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1110000010 + assign \spr_o 10'0001101100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1111111111 + assign \spr_o 10'0001101101 + end + sync init + end +end +attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_a" module \dec_a attribute \enum_base_type "In1Sel" @@ -36737,7 +37240,7 @@ module \dec_a attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:80" wire width 3 input 0 \sel_in attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -36817,8 +37320,119 @@ module \dec_a wire width 5 output 2 \reg_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 3 \reg_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83" wire width 1 output 4 \immz_out + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 10 output 5 \spr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -36837,16 +37451,135 @@ module \dec_a wire width 10 input 12 \SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" wire width 10 input 13 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" + wire width 10 \sprmap_spr_o + cell \sprmap \sprmap + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93" wire width 5 \ra process $group_0 assign \ra 5'00000 assign \ra \RA sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" cell $eq $2 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -36857,9 +37590,9 @@ module \dec_a connect \B 3'001 connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:72" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:96" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:72" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:96" cell $eq $4 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -36870,9 +37603,9 @@ module \dec_a connect \B 3'010 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" cell $ne $6 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -36883,9 +37616,9 @@ module \dec_a connect \B 5'00000 connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" cell $and $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -36896,9 +37629,9 @@ module \dec_a connect \B $5 connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" cell $or $10 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -36909,9 +37642,9 @@ module \dec_a connect \B $7 connect \Y $9 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" cell $eq $12 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -36924,23 +37657,23 @@ module \dec_a end process $group_1 assign \reg_a 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" case 1'1 assign \reg_a \ra end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" switch { $11 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" case 1'1 assign \reg_a \RS end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95" cell $eq $14 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -36951,9 +37684,9 @@ module \dec_a connect \B 3'001 connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:72" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:96" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:72" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:96" cell $eq $16 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -36964,9 +37697,9 @@ module \dec_a connect \B 3'010 connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" cell $ne $18 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -36977,9 +37710,9 @@ module \dec_a connect \B 5'00000 connect \Y $17 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" cell $and $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -36990,9 +37723,9 @@ module \dec_a connect \B $17 connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" cell $or $22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -37003,9 +37736,9 @@ module \dec_a connect \B $19 connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" cell $eq $24 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -37018,23 +37751,23 @@ module \dec_a end process $group_2 assign \reg_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" switch { $21 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" case 1'1 assign \reg_a_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" switch { $23 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" case 1'1 assign \reg_a_ok 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:78" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:78" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" cell $eq $26 parameter \A_SIGNED 0 parameter \A_WIDTH 3 @@ -37045,9 +37778,9 @@ module \dec_a connect \B 3'010 connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" cell $eq $28 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -37058,9 +37791,9 @@ module \dec_a connect \B 5'00000 connect \Y $27 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" cell $and $30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -37073,17 +37806,17 @@ module \dec_a end process $group_3 assign \immz_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" switch { $29 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" case 1'1 assign \immz_out 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" cell $eq $32 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -37094,9 +37827,9 @@ module \dec_a connect \B 7'0000111 connect \Y $31 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" cell $eq $34 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -37107,9 +37840,9 @@ module \dec_a connect \B 7'0001000 connect \Y $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" cell $not $36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -37117,9 +37850,9 @@ module \dec_a connect \A \BO [2] connect \Y $35 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" cell $not $38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -37127,9 +37860,9 @@ module \dec_a connect \A \XL_XO [5] connect \Y $37 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" cell $and $40 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -37140,33 +37873,75 @@ module \dec_a connect \B $37 connect \Y $39 end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + wire width 1 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + cell $eq $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101110 + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" + wire width 10 \spr process $group_4 assign \fast_a 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" switch { $33 $31 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" switch { $35 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" case 1'1 assign \fast_a 3'010 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" case 2'1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" switch { $39 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" case 1'1 assign \fast_a 3'010 end end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + switch { $41 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" + case 10'0000001001 + assign \fast_a 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134" + case 10'0000001000 + assign \fast_a 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + case 10'1100101111 + assign \fast_a 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140" + case 10'0000011010 + assign \fast_a 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" + case 10'0000011011 + assign \fast_a 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150" + case + end + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" - cell $eq $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + cell $eq $44 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -37174,12 +37949,12 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0000111 - connect \Y $41 + connect \Y $43 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" - cell $eq $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" + cell $eq $46 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -37187,68 +37962,108 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $43 + connect \Y $45 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" - cell $not $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" + cell $not $48 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $45 + connect \Y $47 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" - cell $not $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + cell $not $50 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [5] - connect \Y $47 + connect \Y $49 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" - cell $and $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + cell $and $52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \B $47 - connect \Y $49 + connect \B $49 + connect \Y $51 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + cell $eq $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101110 + connect \Y $53 end process $group_5 assign \fast_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" - switch { $43 $41 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" + switch { $45 $43 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" - switch { $45 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" + switch { $47 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" case 1'1 assign \fast_a_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118" case 2'1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" - switch { $49 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + switch { $51 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" case 1'1 assign \fast_a_ok 1'1 end end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + switch { $53 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" + case 10'0000001001 + assign \fast_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134" + case 10'0000001000 + assign \fast_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + case 10'1100101111 + assign \fast_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140" + case 10'0000011010 + assign \fast_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" + case 10'0000011011 + assign \fast_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150" + case + end + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" - cell $eq $52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + cell $eq $56 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -37256,22 +38071,22 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101110 - connect \Y $51 + connect \Y $55 end process $group_6 - assign \spr_a 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" - switch { $51 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" + assign \spr 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + switch { $55 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" case 1'1 - assign \spr_a \SPR + assign \spr { \SPR [4:0] \SPR [9:5] } end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" - cell $eq $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + cell $eq $58 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -37279,15 +38094,112 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101110 - connect \Y $53 + connect \Y $57 end process $group_7 + assign \sprmap_spr_i 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + switch { $57 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150" + case + assign \sprmap_spr_i \spr + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + wire width 1 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + cell $eq $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101110 + connect \Y $59 + end + process $group_8 + assign \spr_a 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + switch { $59 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150" + case + assign \spr_a \sprmap_spr_o + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + wire width 1 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + cell $eq $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101110 + connect \Y $61 + end + process $group_9 assign \spr_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" - switch { $53 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" - case 1'1 - assign \spr_a_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + switch { $61 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150" + case + assign \spr_a_ok 1'1 + end end sync init end @@ -37310,7 +38222,7 @@ module \dec_b attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170" wire width 4 input 0 \sel_in attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -37420,44 +38332,44 @@ module \dec_b wire width 10 input 17 \XL_XO process $group_0 assign \reg_b 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" attribute \nmigen.decoding "RB/1" case 4'0001 assign \reg_b \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" attribute \nmigen.decoding "RS/13" case 4'1101 assign \reg_b \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:139" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" attribute \nmigen.decoding "CONST_UI/2" case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" attribute \nmigen.decoding "CONST_SI/3" case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195" attribute \nmigen.decoding "CONST_UI_HI/4" case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" attribute \nmigen.decoding "CONST_SI_HI/5" case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203" attribute \nmigen.decoding "CONST_LI/6" case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206" attribute \nmigen.decoding "CONST_BD/7" case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" attribute \nmigen.decoding "CONST_DS/8" case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" attribute \nmigen.decoding "CONST_M1/9" case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" attribute \nmigen.decoding "CONST_SH/10" case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" attribute \nmigen.decoding "CONST_SH32/11" case 4'1011 end @@ -37465,44 +38377,44 @@ module \dec_b end process $group_1 assign \reg_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" attribute \nmigen.decoding "RB/1" case 4'0001 assign \reg_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" attribute \nmigen.decoding "RS/13" case 4'1101 assign \reg_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:139" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" attribute \nmigen.decoding "CONST_UI/2" case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" attribute \nmigen.decoding "CONST_SI/3" case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195" attribute \nmigen.decoding "CONST_UI_HI/4" case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" attribute \nmigen.decoding "CONST_SI_HI/5" case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203" attribute \nmigen.decoding "CONST_LI/6" case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206" attribute \nmigen.decoding "CONST_BD/7" case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" attribute \nmigen.decoding "CONST_DS/8" case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" attribute \nmigen.decoding "CONST_M1/9" case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" attribute \nmigen.decoding "CONST_SH/10" case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" attribute \nmigen.decoding "CONST_SH32/11" case 4'1011 end @@ -37518,11 +38430,11 @@ module \dec_b connect \A \UI connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:196" wire width 64 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:196" wire width 47 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:196" cell $sshl $5 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37533,7 +38445,7 @@ module \dec_b connect \B 5'10000 connect \Y $4 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:196" cell $pos $6 parameter \A_SIGNED 0 parameter \A_WIDTH 47 @@ -37541,11 +38453,11 @@ module \dec_b connect \A $4 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" wire width 64 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" wire width 47 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" cell $sshl $9 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37556,7 +38468,7 @@ module \dec_b connect \B 5'10000 connect \Y $8 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" cell $pos $10 parameter \A_SIGNED 0 parameter \A_WIDTH 47 @@ -37564,11 +38476,11 @@ module \dec_b connect \A $8 connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $13 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37580,11 +38492,11 @@ module \dec_b connect \Y $12 end connect $11 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $16 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37596,11 +38508,11 @@ module \dec_b connect \Y $15 end connect $14 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $19 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37612,11 +38524,11 @@ module \dec_b connect \Y $18 end connect $17 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $22 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37628,11 +38540,11 @@ module \dec_b connect \Y $21 end connect $20 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $25 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37644,11 +38556,11 @@ module \dec_b connect \Y $24 end connect $23 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $28 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37660,11 +38572,11 @@ module \dec_b connect \Y $27 end connect $26 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $31 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37676,11 +38588,11 @@ module \dec_b connect \Y $30 end connect $29 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $34 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37692,11 +38604,11 @@ module \dec_b connect \Y $33 end connect $32 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $37 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37708,11 +38620,11 @@ module \dec_b connect \Y $36 end connect $35 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $40 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37724,11 +38636,11 @@ module \dec_b connect \Y $39 end connect $38 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $43 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37740,11 +38652,11 @@ module \dec_b connect \Y $42 end connect $41 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $46 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37756,11 +38668,11 @@ module \dec_b connect \Y $45 end connect $44 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $49 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37772,11 +38684,11 @@ module \dec_b connect \Y $48 end connect $47 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $52 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37788,11 +38700,11 @@ module \dec_b connect \Y $51 end connect $50 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $55 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37804,11 +38716,11 @@ module \dec_b connect \Y $54 end connect $53 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $58 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37820,11 +38732,11 @@ module \dec_b connect \Y $57 end connect $56 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $61 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37836,11 +38748,11 @@ module \dec_b connect \Y $60 end connect $59 $60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $64 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37852,11 +38764,11 @@ module \dec_b connect \Y $63 end connect $62 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $67 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37868,11 +38780,11 @@ module \dec_b connect \Y $66 end connect $65 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $70 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37884,11 +38796,11 @@ module \dec_b connect \Y $69 end connect $68 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $73 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37900,11 +38812,11 @@ module \dec_b connect \Y $72 end connect $71 $72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $76 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37916,11 +38828,11 @@ module \dec_b connect \Y $75 end connect $74 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $79 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37932,11 +38844,11 @@ module \dec_b connect \Y $78 end connect $77 $78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $82 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37948,11 +38860,11 @@ module \dec_b connect \Y $81 end connect $80 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $85 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37964,11 +38876,11 @@ module \dec_b connect \Y $84 end connect $83 $84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $88 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37980,11 +38892,11 @@ module \dec_b connect \Y $87 end connect $86 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $91 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -37996,11 +38908,11 @@ module \dec_b connect \Y $90 end connect $89 $90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $94 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -38012,11 +38924,11 @@ module \dec_b connect \Y $93 end connect $92 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $97 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -38028,11 +38940,11 @@ module \dec_b connect \Y $96 end connect $95 $96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $100 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -38044,11 +38956,11 @@ module \dec_b connect \Y $99 end connect $98 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $103 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -38060,11 +38972,11 @@ module \dec_b connect \Y $102 end connect $101 $102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $106 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -38076,11 +38988,11 @@ module \dec_b connect \Y $105 end connect $104 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" wire width 47 $108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" cell $sshl $109 parameter \A_SIGNED 0 parameter \A_WIDTH 16 @@ -38092,11 +39004,11 @@ module \dec_b connect \Y $108 end connect $107 $108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:155" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" wire width 64 $110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:155" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" wire width 27 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:155" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" cell $sshl $112 parameter \A_SIGNED 0 parameter \A_WIDTH 24 @@ -38107,7 +39019,7 @@ module \dec_b connect \B 2'10 connect \Y $111 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:155" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" cell $pos $113 parameter \A_SIGNED 0 parameter \A_WIDTH 27 @@ -38115,11 +39027,11 @@ module \dec_b connect \A $111 connect \Y $110 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" wire width 64 $114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" wire width 17 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" cell $sshl $116 parameter \A_SIGNED 0 parameter \A_WIDTH 14 @@ -38130,7 +39042,7 @@ module \dec_b connect \B 2'10 connect \Y $115 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" cell $pos $117 parameter \A_SIGNED 0 parameter \A_WIDTH 17 @@ -38138,11 +39050,11 @@ module \dec_b connect \A $115 connect \Y $114 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" wire width 64 $118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" wire width 17 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" cell $sshl $120 parameter \A_SIGNED 0 parameter \A_WIDTH 14 @@ -38153,7 +39065,7 @@ module \dec_b connect \B 2'10 connect \Y $119 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" cell $pos $121 parameter \A_SIGNED 0 parameter \A_WIDTH 17 @@ -38161,9 +39073,9 @@ module \dec_b connect \A $119 connect \Y $118 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" wire width 64 $122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213" cell $not $123 parameter \A_SIGNED 0 parameter \A_WIDTH 64 @@ -38193,52 +39105,52 @@ module \dec_b end process $group_2 assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" attribute \nmigen.decoding "RB/1" case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" attribute \nmigen.decoding "RS/13" case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:139" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" attribute \nmigen.decoding "CONST_UI/2" case 4'0010 assign \imm_b $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" attribute \nmigen.decoding "CONST_SI/3" case 4'0011 assign \imm_b { { \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] } \SI } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195" attribute \nmigen.decoding "CONST_UI_HI/4" case 4'0100 assign \imm_b $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" attribute \nmigen.decoding "CONST_SI_HI/5" case 4'0101 assign \imm_b $7 assign \imm_b { { $14 [31:0] [31] $17 [31:0] [31] $20 [31:0] [31] $23 [31:0] [31] $26 [31:0] [31] $29 [31:0] [31] $32 [31:0] [31] $35 [31:0] [31] $38 [31:0] [31] $41 [31:0] [31] $44 [31:0] [31] $47 [31:0] [31] $50 [31:0] [31] $53 [31:0] [31] $56 [31:0] [31] $59 [31:0] [31] $62 [31:0] [31] $65 [31:0] [31] $68 [31:0] [31] $71 [31:0] [31] $74 [31:0] [31] $77 [31:0] [31] $80 [31:0] [31] $83 [31:0] [31] $86 [31:0] [31] $89 [31:0] [31] $92 [31:0] [31] $95 [31:0] [31] $98 [31:0] [31] $101 [31:0] [31] $104 [31:0] [31] $107 [31:0] [31] } $11 [31:0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203" attribute \nmigen.decoding "CONST_LI/6" case 4'0110 assign \imm_b $110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206" attribute \nmigen.decoding "CONST_BD/7" case 4'0111 assign \imm_b $114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" attribute \nmigen.decoding "CONST_DS/8" case 4'1000 assign \imm_b $118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" attribute \nmigen.decoding "CONST_M1/9" case 4'1001 assign \imm_b $122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" attribute \nmigen.decoding "CONST_SH/10" case 4'1010 assign \imm_b $124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" attribute \nmigen.decoding "CONST_SH32/11" case 4'1011 assign \imm_b $126 @@ -38247,60 +39159,60 @@ module \dec_b end process $group_3 assign \imm_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182" attribute \nmigen.decoding "RB/1" case 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" attribute \nmigen.decoding "RS/13" case 4'1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:139" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" attribute \nmigen.decoding "CONST_UI/2" case 4'0010 assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:142" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" attribute \nmigen.decoding "CONST_SI/3" case 4'0011 assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195" attribute \nmigen.decoding "CONST_UI_HI/4" case 4'0100 assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" attribute \nmigen.decoding "CONST_SI_HI/5" case 4'0101 assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203" attribute \nmigen.decoding "CONST_LI/6" case 4'0110 assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206" attribute \nmigen.decoding "CONST_BD/7" case 4'0111 assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:160" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" attribute \nmigen.decoding "CONST_DS/8" case 4'1000 assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:163" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212" attribute \nmigen.decoding "CONST_M1/9" case 4'1001 assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" attribute \nmigen.decoding "CONST_SH/10" case 4'1010 assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" attribute \nmigen.decoding "CONST_SH32/11" case 4'1011 assign \imm_b_ok 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" wire width 1 $128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" cell $eq $129 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -38311,9 +39223,9 @@ module \dec_b connect \B 7'0001000 connect \Y $128 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" wire width 1 $130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" cell $not $131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -38323,25 +39235,25 @@ module \dec_b end process $group_4 assign \fast_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" switch { $128 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" switch { \XL_XO [5] $130 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" case 2'-1 assign \fast_b 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" case 2'1- assign \fast_b 3'100 end end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" wire width 1 $132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" cell $eq $133 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -38352,9 +39264,9 @@ module \dec_b connect \B 7'0001000 connect \Y $132 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" wire width 1 $134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" cell $not $135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -38364,16 +39276,16 @@ module \dec_b end process $group_5 assign \fast_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" switch { $132 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" switch { \XL_XO [5] $134 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" case 2'-1 assign \fast_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" case 2'1- assign \fast_b_ok 1'1 end @@ -38388,7 +39300,7 @@ module \dec_c attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" wire width 2 input 0 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 5 output 1 \reg_c @@ -38400,13 +39312,13 @@ module \dec_c wire width 5 input 4 \RB process $group_0 assign \reg_c 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" attribute \nmigen.decoding "RB/2" case 2'10 assign \reg_c \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" attribute \nmigen.decoding "RS/1" case 2'01 assign \reg_c \RS @@ -38415,13 +39327,13 @@ module \dec_c end process $group_1 assign \reg_c_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" attribute \nmigen.decoding "RB/2" case 2'10 assign \reg_c_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:211" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" attribute \nmigen.decoding "RS/1" case 2'01 assign \reg_c_ok 1'1 @@ -38430,6 +39342,462 @@ module \dec_c end end attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o.sprmap" +module \sprmap$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 input 0 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" + wire width 10 output 1 \spr_o + process $group_0 + assign \spr_o 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:64" + switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000000001 + assign \spr_o 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000000011 + assign \spr_o 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000001000 + assign \spr_o 10'0000000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000001001 + assign \spr_o 10'0000000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000001101 + assign \spr_o 10'0000000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000010001 + assign \spr_o 10'0000000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000010010 + assign \spr_o 10'0000000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000010011 + assign \spr_o 10'0000000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000010110 + assign \spr_o 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000011010 + assign \spr_o 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000011011 + assign \spr_o 10'0000001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000011100 + assign \spr_o 10'0000001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000011101 + assign \spr_o 10'0000001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000110000 + assign \spr_o 10'0000001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0000111101 + assign \spr_o 10'0000001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010000000 + assign \spr_o 10'0000001111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010000001 + assign \spr_o 10'0000010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010000010 + assign \spr_o 10'0000010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010000011 + assign \spr_o 10'0000010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010001000 + assign \spr_o 10'0000010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010010000 + assign \spr_o 10'0000010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010011000 + assign \spr_o 10'0000010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010011001 + assign \spr_o 10'0000010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010011101 + assign \spr_o 10'0000010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010011110 + assign \spr_o 10'0000011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010011111 + assign \spr_o 10'0000011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010110000 + assign \spr_o 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010110100 + assign \spr_o 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010111010 + assign \spr_o 10'0000011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010111011 + assign \spr_o 10'0000011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010111100 + assign \spr_o 10'0000011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0010111110 + assign \spr_o 10'0000011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100000000 + assign \spr_o 10'0000100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100000011 + assign \spr_o 10'0000100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100001100 + assign \spr_o 10'0000100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100001101 + assign \spr_o 10'0000100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100010000 + assign \spr_o 10'0000100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100010001 + assign \spr_o 10'0000100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100010010 + assign \spr_o 10'0000100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100010011 + assign \spr_o 10'0000100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100011011 + assign \spr_o 10'0000101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100011100 + assign \spr_o 10'0000101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100011101 + assign \spr_o 10'0000101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100011110 + assign \spr_o 10'0000101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100011111 + assign \spr_o 10'0000101100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110000 + assign \spr_o 10'0000101101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110001 + assign \spr_o 10'0000101110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110010 + assign \spr_o 10'0000101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110011 + assign \spr_o 10'0000110000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110100 + assign \spr_o 10'0000110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110101 + assign \spr_o 10'0000110010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100110110 + assign \spr_o 10'0000110011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100111001 + assign \spr_o 10'0000110100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100111010 + assign \spr_o 10'0000110101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100111011 + assign \spr_o 10'0000110110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100111110 + assign \spr_o 10'0000110111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0100111111 + assign \spr_o 10'0000111000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0101010000 + assign \spr_o 10'0000111001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0101010001 + assign \spr_o 10'0000111010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0101010010 + assign \spr_o 10'0000111011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0101010011 + assign \spr_o 10'0000111100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0101011101 + assign \spr_o 10'0000111101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0110111110 + assign \spr_o 10'0000111110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'0111010000 + assign \spr_o 10'0000111111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000000 + assign \spr_o 10'0001000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000001 + assign \spr_o 10'0001000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000010 + assign \spr_o 10'0001000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000011 + assign \spr_o 10'0001000011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000100 + assign \spr_o 10'0001000100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000101 + assign \spr_o 10'0001000101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000110 + assign \spr_o 10'0001000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100000111 + assign \spr_o 10'0001000111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100001000 + assign \spr_o 10'0001001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100001011 + assign \spr_o 10'0001001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100001100 + assign \spr_o 10'0001001010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100001101 + assign \spr_o 10'0001001011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100001110 + assign \spr_o 10'0001001100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010000 + assign \spr_o 10'0001001101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010001 + assign \spr_o 10'0001001110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010010 + assign \spr_o 10'0001001111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010011 + assign \spr_o 10'0001010000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010100 + assign \spr_o 10'0001010001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010101 + assign \spr_o 10'0001010010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010110 + assign \spr_o 10'0001010011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100010111 + assign \spr_o 10'0001010100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100011000 + assign \spr_o 10'0001010101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100011011 + assign \spr_o 10'0001010110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100011100 + assign \spr_o 10'0001010111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100011101 + assign \spr_o 10'0001011000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100011110 + assign \spr_o 10'0001011001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100000 + assign \spr_o 10'0001011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100001 + assign \spr_o 10'0001011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100010 + assign \spr_o 10'0001011100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100011 + assign \spr_o 10'0001011101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100100 + assign \spr_o 10'0001011110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100101 + assign \spr_o 10'0001011111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100100110 + assign \spr_o 10'0001100000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100101000 + assign \spr_o 10'0001100001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100101001 + assign \spr_o 10'0001100010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100101010 + assign \spr_o 10'0001100011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100101011 + assign \spr_o 10'0001100100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100101111 + assign \spr_o 10'0001100101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100110000 + assign \spr_o 10'0001100110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1100110111 + assign \spr_o 10'0001100111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1101010000 + assign \spr_o 10'0001101000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1101010001 + assign \spr_o 10'0001101001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1101010111 + assign \spr_o 10'0001101010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1110000000 + assign \spr_o 10'0001101011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1110000010 + assign \spr_o 10'0001101100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66" + case 10'1111111111 + assign \spr_o 10'0001101101 + end + sync init + end +end +attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o" module \dec_o attribute \enum_base_type "OutSel" @@ -38437,7 +39805,7 @@ module \dec_o attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 2 input 0 \sel_in attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -38517,6 +39885,117 @@ module \dec_o wire width 5 output 2 \reg_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 3 \reg_o_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 10 output 4 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -38533,19 +40012,138 @@ module \dec_o wire width 5 input 10 \BO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 10 input 11 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" + wire width 10 \sprmap_spr_o + cell \sprmap$1 \sprmap + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + end process $group_0 assign \reg_o 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" attribute \nmigen.decoding "RT/1" case 2'01 assign \reg_o \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292" attribute \nmigen.decoding "RA/2" case 2'10 assign \reg_o \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" attribute \nmigen.decoding "SPR/3" case 2'11 end @@ -38553,59 +40151,44 @@ module \dec_o end process $group_1 assign \reg_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" attribute \nmigen.decoding "RT/1" case 2'01 assign \reg_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292" attribute \nmigen.decoding "RA/2" case 2'10 assign \reg_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" attribute \nmigen.decoding "SPR/3" case 2'11 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296" + wire width 10 \spr process $group_2 - assign \spr_o 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" + assign \spr 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" attribute \nmigen.decoding "RT/1" case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292" attribute \nmigen.decoding "RA/2" case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" attribute \nmigen.decoding "SPR/3" case 2'11 - assign \spr_o \SPR + assign \spr { \SPR [4:0] \SPR [9:5] } end sync init end - process $group_3 - assign \spr_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - attribute \nmigen.decoding "SPR/3" - case 2'11 - assign \spr_o_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" cell $eq $2 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -38613,12 +40196,12 @@ module \dec_o parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \internal_op - connect \B 7'0000111 + connect \B 7'0110001 connect \Y $1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" cell $eq $4 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -38626,36 +40209,49 @@ module \dec_o parameter \B_WIDTH 7 parameter \Y_WIDTH 1 connect \A \internal_op - connect \B 7'0001000 + connect \B 7'0000111 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $or $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + cell $eq $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A $1 - connect \B $3 + connect \A \internal_op + connect \B 7'0001000 connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - cell $not $8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + cell $or $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \BO [2] + connect \A $3 + connect \B $5 connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276" - cell $eq $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $12 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -38663,33 +40259,85 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'1000110 - connect \Y $9 + connect \Y $11 end - process $group_4 + process $group_3 assign \fast_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" + attribute \nmigen.decoding "RT/1" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292" + attribute \nmigen.decoding "RA/2" + case 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \nmigen.decoding "SPR/3" + case 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + switch { $1 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302" + case 10'0000001001 + assign \fast_o 3'010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + case 10'0000001000 + assign \fast_o 3'011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + case 10'1100101111 + assign \fast_o 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" + case 10'0000011010 + assign \fast_o 3'101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:314" + case 10'0000011011 + assign \fast_o 3'110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + case + end + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + switch { $7 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" + switch { $9 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" case 1'1 assign \fast_o 3'010 end end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + switch { $11 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" case 1'1 assign \fast_o 3'101 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:269" - cell $eq $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + cell $eq $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $13 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" + cell $eq $16 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -38697,12 +40345,12 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0000111 - connect \Y $11 + connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $eq $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + cell $eq $18 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -38710,35 +40358,35 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $13 + connect \Y $17 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $or $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + wire width 1 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + cell $or $20 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $11 - connect \B $13 - connect \Y $15 + connect \A $15 + connect \B $17 + connect \Y $19 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - cell $not $18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" + cell $not $22 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $17 + connect \Y $21 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276" - cell $eq $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $24 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -38746,34 +40394,229 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'1000110 - connect \Y $19 + connect \Y $23 end - process $group_5 + process $group_4 assign \fast_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" + attribute \nmigen.decoding "RT/1" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292" + attribute \nmigen.decoding "RA/2" + case 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \nmigen.decoding "SPR/3" + case 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + switch { $13 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302" + case 10'0000001001 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + case 10'0000001000 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + case 10'1100101111 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" + case 10'0000011010 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:314" + case 10'0000011011 + assign \fast_o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + case + end + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + switch { $19 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" + switch { $21 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" case 1'1 assign \fast_o_ok 1'1 end end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + switch { $23 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" case 1'1 assign \fast_o_ok 1'1 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + wire width 1 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + cell $eq $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $25 + end + process $group_5 + assign \sprmap_spr_i 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" + attribute \nmigen.decoding "RT/1" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292" + attribute \nmigen.decoding "RA/2" + case 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \nmigen.decoding "SPR/3" + case 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + switch { $25 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:314" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + case + assign \sprmap_spr_i \spr + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + wire width 1 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + cell $eq $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $27 + end + process $group_6 + assign \spr_o 10'0000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" + attribute \nmigen.decoding "RT/1" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292" + attribute \nmigen.decoding "RA/2" + case 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \nmigen.decoding "SPR/3" + case 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + switch { $27 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:314" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + case + assign \spr_o \sprmap_spr_o + end + end + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + cell $eq $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $29 + end + process $group_7 + assign \spr_o_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" + switch \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289" + attribute \nmigen.decoding "RT/1" + case 2'01 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292" + attribute \nmigen.decoding "RA/2" + case 2'10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + attribute \nmigen.decoding "SPR/3" + case 2'11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + switch { $29 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" + case 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302" + case 10'0000001001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305" + case 10'0000001000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + case 10'1100101111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" + case 10'0000011010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:314" + case 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317" + case 10'0000000001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + case + assign \spr_o_ok 1'1 + end + end + end + sync init + end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o2" module \dec_o2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" wire width 1 input 0 \lk attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -38874,18 +40717,18 @@ module \dec_o2 process $group_0 assign \reg_o 5'00000 assign \reg_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:361" switch { \upd } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:361" case 1'1 assign { \reg_o_ok \reg_o } $1 assign \reg_o_ok 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367" wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367" cell $eq $4 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -38896,9 +40739,9 @@ module \dec_o2 connect \B 7'0000111 connect \Y $3 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368" wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368" cell $eq $6 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -38909,9 +40752,9 @@ module \dec_o2 connect \B 7'0001000 connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368" wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368" cell $or $8 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -38922,9 +40765,9 @@ module \dec_o2 connect \B $5 connect \Y $7 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" cell $eq $10 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -38937,28 +40780,28 @@ module \dec_o2 end process $group_2 assign \fast_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368" switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" switch { \lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" case 1'1 assign \fast_o 3'011 end end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" case 1'1 assign \fast_o 3'110 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367" wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367" cell $eq $12 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -38969,9 +40812,9 @@ module \dec_o2 connect \B 7'0000111 connect \Y $11 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368" wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368" cell $eq $14 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -38982,9 +40825,9 @@ module \dec_o2 connect \B 7'0001000 connect \Y $13 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368" cell $or $16 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -38995,9 +40838,9 @@ module \dec_o2 connect \B $13 connect \Y $15 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" cell $eq $18 parameter \A_SIGNED 0 parameter \A_WIDTH 7 @@ -39010,20 +40853,20 @@ module \dec_o2 end process $group_3 assign \fast_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368" switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368" case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" switch { \lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369" case 1'1 assign \fast_o_ok 1'1 end end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" case 1'1 assign \fast_o_ok 1'1 end @@ -39037,7 +40880,7 @@ module \dec_rc attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" wire width 2 input 0 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 1 \rc @@ -39047,17 +40890,17 @@ module \dec_rc wire width 1 input 3 \Rc process $group_0 assign \rc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:338" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:397" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" attribute \nmigen.decoding "RC/2" case 2'10 assign \rc \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:342" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:401" attribute \nmigen.decoding "ONE/1" case 2'01 assign \rc 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:345" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" attribute \nmigen.decoding "NONE/0" case 2'00 assign \rc 1'0 @@ -39066,17 +40909,17 @@ module \dec_rc end process $group_1 assign \rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:338" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:397" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:339" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" attribute \nmigen.decoding "RC/2" case 2'10 assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:342" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:401" attribute \nmigen.decoding "ONE/1" case 2'01 assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:345" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" attribute \nmigen.decoding "NONE/0" case 2'00 assign \rc_ok 1'1 @@ -39091,7 +40934,7 @@ module \dec_oe attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:424" wire width 2 input 0 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 1 \oe @@ -39101,9 +40944,9 @@ module \dec_oe wire width 1 input 3 \OE process $group_0 assign \oe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:433" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:375" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:434" attribute \nmigen.decoding "RC/2" case 2'10 assign \oe \OE @@ -39112,9 +40955,9 @@ module \dec_oe end process $group_1 assign \oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:433" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:375" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:434" attribute \nmigen.decoding "RC/2" case 2'10 assign \oe_ok 1'1 @@ -39133,7 +40976,7 @@ module \dec_cr_in attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" wire width 3 input 0 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 3 output 1 \cr_bitfield @@ -39147,7 +40990,7 @@ module \dec_cr_in wire width 3 output 5 \cr_bitfield_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 6 \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" wire width 1 output 7 \whole_reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" wire width 5 input 8 \BB @@ -39164,32 +41007,32 @@ module \dec_cr_in process $group_0 assign \cr_bitfield_ok 1'0 assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464" attribute \nmigen.decoding "NONE/0" case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466" attribute \nmigen.decoding "CR0/1" case 3'001 assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469" attribute \nmigen.decoding "BI/2" case 3'010 assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" attribute \nmigen.decoding "BFA/3" case 3'011 assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" attribute \nmigen.decoding "BA_BB/4" case 3'100 assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" attribute \nmigen.decoding "BC/5" case 3'101 assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" attribute \nmigen.decoding "WHOLE_REG/6" case 3'110 end @@ -39198,28 +41041,28 @@ module \dec_cr_in process $group_1 assign \cr_bitfield_b_ok 1'0 assign \cr_bitfield_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464" attribute \nmigen.decoding "NONE/0" case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466" attribute \nmigen.decoding "CR0/1" case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469" attribute \nmigen.decoding "BI/2" case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" attribute \nmigen.decoding "BFA/3" case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" attribute \nmigen.decoding "BA_BB/4" case 3'100 assign \cr_bitfield_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" attribute \nmigen.decoding "BC/5" case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" attribute \nmigen.decoding "WHOLE_REG/6" case 3'110 end @@ -39228,27 +41071,27 @@ module \dec_cr_in process $group_2 assign \whole_reg 1'0 assign \whole_reg 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464" attribute \nmigen.decoding "NONE/0" case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466" attribute \nmigen.decoding "CR0/1" case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469" attribute \nmigen.decoding "BI/2" case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" attribute \nmigen.decoding "BFA/3" case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" attribute \nmigen.decoding "BA_BB/4" case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" attribute \nmigen.decoding "BC/5" case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" attribute \nmigen.decoding "WHOLE_REG/6" case 3'110 assign \whole_reg 1'1 @@ -39257,32 +41100,32 @@ module \dec_cr_in end process $group_3 assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464" attribute \nmigen.decoding "NONE/0" case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466" attribute \nmigen.decoding "CR0/1" case 3'001 assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469" attribute \nmigen.decoding "BI/2" case 3'010 assign \cr_bitfield \BI [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" attribute \nmigen.decoding "BFA/3" case 3'011 assign \cr_bitfield \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" attribute \nmigen.decoding "BA_BB/4" case 3'100 assign \cr_bitfield \BA [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" attribute \nmigen.decoding "BC/5" case 3'101 assign \cr_bitfield \BC [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" attribute \nmigen.decoding "WHOLE_REG/6" case 3'110 end @@ -39290,28 +41133,28 @@ module \dec_cr_in end process $group_4 assign \cr_bitfield_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464" attribute \nmigen.decoding "NONE/0" case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466" attribute \nmigen.decoding "CR0/1" case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469" attribute \nmigen.decoding "BI/2" case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" attribute \nmigen.decoding "BFA/3" case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" attribute \nmigen.decoding "BA_BB/4" case 3'100 assign \cr_bitfield_b \BB [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" attribute \nmigen.decoding "BC/5" case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" attribute \nmigen.decoding "WHOLE_REG/6" case 3'110 end @@ -39319,28 +41162,28 @@ module \dec_cr_in end process $group_5 assign \cr_bitfield_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464" attribute \nmigen.decoding "NONE/0" case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466" attribute \nmigen.decoding "CR0/1" case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469" attribute \nmigen.decoding "BI/2" case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" attribute \nmigen.decoding "BFA/3" case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" attribute \nmigen.decoding "BA_BB/4" case 3'100 assign \cr_bitfield_o \BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" attribute \nmigen.decoding "BC/5" case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" attribute \nmigen.decoding "WHOLE_REG/6" case 3'110 end @@ -39348,28 +41191,28 @@ module \dec_cr_in end process $group_6 assign \cr_bitfield_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464" attribute \nmigen.decoding "NONE/0" case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466" attribute \nmigen.decoding "CR0/1" case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469" attribute \nmigen.decoding "BI/2" case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472" attribute \nmigen.decoding "BFA/3" case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475" attribute \nmigen.decoding "BA_BB/4" case 3'100 assign \cr_bitfield_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482" attribute \nmigen.decoding "BC/5" case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:426" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" attribute \nmigen.decoding "WHOLE_REG/6" case 3'110 end @@ -39385,15 +41228,15 @@ module \dec_cr_out attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:501" wire width 3 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 1 input 1 \rc_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 3 output 2 \cr_bitfield attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 3 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" wire width 1 output 4 \whole_reg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335" wire width 3 input 5 \X_BF @@ -39402,24 +41245,24 @@ module \dec_cr_out process $group_0 assign \cr_bitfield_ok 1'0 assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:513" attribute \nmigen.decoding "NONE/0" case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:456" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:515" attribute \nmigen.decoding "CR0/1" case 3'001 assign \cr_bitfield_ok \rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:518" attribute \nmigen.decoding "BF/2" case 3'010 assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" attribute \nmigen.decoding "BT/3" case 3'011 assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" attribute \nmigen.decoding "WHOLE_REG/4" case 3'100 end @@ -39428,21 +41271,21 @@ module \dec_cr_out process $group_1 assign \whole_reg 1'0 assign \whole_reg 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:513" attribute \nmigen.decoding "NONE/0" case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:456" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:515" attribute \nmigen.decoding "CR0/1" case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:518" attribute \nmigen.decoding "BF/2" case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" attribute \nmigen.decoding "BT/3" case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" attribute \nmigen.decoding "WHOLE_REG/4" case 3'100 assign \whole_reg 1'1 @@ -39451,24 +41294,24 @@ module \dec_cr_out end process $group_2 assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512" switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:513" attribute \nmigen.decoding "NONE/0" case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:456" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:515" attribute \nmigen.decoding "CR0/1" case 3'001 assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:518" attribute \nmigen.decoding "BF/2" case 3'010 assign \cr_bitfield \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" attribute \nmigen.decoding "BT/3" case 3'011 assign \cr_bitfield \XL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" attribute \nmigen.decoding "WHOLE_REG/4" case 3'100 end @@ -39483,18 +41326,19 @@ module \pdecode2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" wire width 32 input 1 \raw_opcode_in attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34" - wire width 10 output 2 \fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33" + wire width 11 output 2 \fn_unit attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -39567,13 +41411,13 @@ module \pdecode2 attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:32" wire width 7 output 3 \insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 output 4 \imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 5 \imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" wire width 1 output 6 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 7 \rc @@ -39583,11 +41427,11 @@ module \pdecode2 wire width 1 output 9 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 10 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" wire width 1 output 11 \invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" wire width 1 output 12 \zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63" wire width 1 output 13 \invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 3 output 14 \cr_out @@ -39597,33 +41441,33 @@ module \pdecode2 attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64" wire width 2 output 16 \input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65" wire width 1 output 17 \output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66" wire width 1 output 18 \input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67" wire width 1 output 19 \output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68" wire width 1 output 20 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69" wire width 1 output 21 \is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" - wire width 4 output 22 \data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71" + wire width 4 output 22 \data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70" wire width 32 output 23 \insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" wire width 1 output 24 \byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73" wire width 1 output 25 \sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 26 \reg1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 27 \reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" wire width 1 output 28 \read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" wire width 1 output 29 \write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 30 \cr_in1_ok @@ -39635,38 +41479,268 @@ module \pdecode2 wire width 1 output 33 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 34 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:77" - wire width 13 output 35 \trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 36 \reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:75" - wire width 1 output 37 \update - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 38 \reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 39 \reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 40 \reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 41 \cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 42 \cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 43 \cr_in2$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 44 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 45 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 46 \rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 47 \ea + wire width 5 output 35 \traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:76" + wire width 13 output 36 \trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 48 \fasto1 + wire width 1 output 37 \spr1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 49 \fasto2 + wire width 1 output 38 \reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74" + wire width 1 output 39 \update + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 5 output 40 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 5 output 41 \reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 5 output 42 \reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 43 \cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 44 \cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 45 \cr_in2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 46 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 47 \fast2 + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 10 output 48 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 5 output 49 \rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 5 output 50 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 51 \fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 52 \fasto2 + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 10 output 53 \spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" - wire width 32 output 50 \opcode_in + wire width 32 output 54 \opcode_in attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -39674,7 +41748,7 @@ module \pdecode2 attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 3 output 51 \in1_sel + wire width 3 output 55 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -39691,26 +41765,26 @@ module \pdecode2 attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 4 output 52 \in2_sel + wire width 4 output 56 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 2 output 53 \in3_sel + wire width 2 output 57 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 54 \out_sel + wire width 2 output 58 \out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 2 output 55 \rc_sel + wire width 2 output 59 \rc_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -39720,7 +41794,7 @@ module \pdecode2 attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 3 output 56 \cr_in + wire width 3 output 60 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -39728,22 +41802,23 @@ module \pdecode2 attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 57 \cr_out$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37" - wire width 64 output 58 \nia + wire width 3 output 61 \cr_out$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:36" + wire width 64 output 62 \nia attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 59 \function_unit + wire width 11 output 63 \function_unit attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -39817,23 +41892,17 @@ module \pdecode2 attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 7 output 60 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 61 \rego_ok + wire width 7 output 64 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 62 \ea_ok + wire width 1 output 65 \rego_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 10 output 63 \spr1 + wire width 1 output 66 \ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 64 \spr1_ok + wire width 1 output 67 \spro_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 10 output 65 \spro + wire width 1 output 68 \fasto1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 66 \spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 67 \fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 68 \fasto2_ok + wire width 1 output 69 \fasto2_ok attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -39841,25 +41910,27 @@ module \pdecode2 attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 4 output 69 \ldst_len + wire width 4 output 70 \ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 70 \inv_a + wire width 1 output 71 \inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 71 \inv_out + wire width 1 output 72 \inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 72 \cry_out + wire width 1 output 73 \cry_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 73 \is_32b + wire width 1 output 74 \is_32b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 74 \sgn + wire width 1 output 75 \sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 75 \lk$4 + wire width 1 output 76 \lk$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 76 \br + wire width 1 output 77 \br attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 77 \sgn_ext + wire width 1 output 78 \sgn_ext attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 78 \upd + wire width 1 output 79 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35" + wire width 8 output 80 \asmcode attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -39891,13 +41962,13 @@ module \pdecode2 attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 5 output 79 \form + wire width 5 output 81 \form attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 80 \rsrv + wire width 1 output 82 \rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 81 \sgl_pipe + wire width 1 output 83 \sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123" - wire width 8 output 82 \asmcode + wire width 8 output 84 \asmcode$5 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" @@ -39982,7 +42053,7 @@ module \pdecode2 connect \form \form connect \rsrv \rsrv connect \sgl_pipe \sgl_pipe - connect \asmcode \asmcode + connect \asmcode \asmcode$5 connect \RS \dec_RS connect \RT \dec_RT connect \RA \dec_RA @@ -40014,14 +42085,125 @@ module \pdecode2 attribute \enum_value_010 "RA_OR_ZERO" attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:80" wire width 3 \dec_a_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 5 \dec_a_reg_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \dec_a_reg_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83" wire width 1 \dec_a_immz_out + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 10 \dec_a_spr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -40061,7 +42243,7 @@ module \pdecode2 attribute \enum_value_1011 "CONST_SH32" attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170" wire width 4 \dec_b_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 5 \dec_b_reg_b @@ -40099,7 +42281,7 @@ module \pdecode2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" wire width 2 \dec_c_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 5 \dec_c_reg_c @@ -40117,12 +42299,123 @@ module \pdecode2 attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" wire width 2 \dec_o_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 5 \dec_o_reg_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \dec_o_reg_o_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 10 \dec_o_spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -40145,7 +42438,7 @@ module \pdecode2 connect \BO \dec_BO connect \SPR \dec_SPR end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" wire width 1 \dec_o2_lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 5 \dec_o2_reg_o @@ -40169,7 +42462,7 @@ module \pdecode2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" wire width 2 \dec_rc_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \dec_rc_rc @@ -40185,7 +42478,7 @@ module \pdecode2 attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:424" wire width 2 \dec_oe_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \dec_oe_oe @@ -40205,7 +42498,7 @@ module \pdecode2 attribute \enum_value_100 "BA_BB" attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449" wire width 3 \dec_cr_in_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 3 \dec_cr_in_cr_bitfield @@ -40219,7 +42512,7 @@ module \pdecode2 wire width 3 \dec_cr_in_cr_bitfield_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \dec_cr_in_cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" wire width 1 \dec_cr_in_whole_reg cell \dec_cr_in \dec_cr_in connect \sel_in \dec_cr_in_sel_in @@ -40243,15 +42536,15 @@ module \pdecode2 attribute \enum_value_010 "BF" attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:501" wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" wire width 1 \dec_cr_out_rc_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 3 \dec_cr_out_cr_bitfield attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504" wire width 1 \dec_cr_out_whole_reg cell \dec_cr_out \dec_cr_out connect \sel_in \dec_cr_out_sel_in @@ -40262,72 +42555,323 @@ module \pdecode2 connect \X_BF \dec_X_BF connect \XL_BT \dec_XL_BT end - process $group_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:590" + wire width 7 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:590" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:590" + cell $eq $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \B_SIGNED 0 + parameter \B_WIDTH 11 + parameter \Y_WIDTH 1 + connect \A \function_unit + connect \B 11'00000000000 + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:590" + cell $mux $9 + parameter \WIDTH 7 + connect \A \internal_op + connect \B 7'0000000 + connect \S $7 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:646" + wire width 1 $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:646" + cell $eq $11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0111111 + connect \Y $10 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:653" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:653" + cell $eq $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0000000 + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:664" + wire width 1 $14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:664" + cell $eq $15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'0111111 + connect \Y $14 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" + wire width 1 $16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" + cell $eq $17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1001001 + connect \Y $16 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" + wire width 1 $18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" + cell $or $19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $14 + connect \B $16 + connect \Y $18 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:674" + wire width 1 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:674" + cell $eq $21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1000110 + connect \Y $20 + end + process $group_22 assign \insn 32'00000000000000000000000000000000 + assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \insn_type 7'0000000 + assign \fn_unit 11'00000000000 + assign \reg1 5'00000 + assign \reg1_ok 1'0 + assign \reg2 5'00000 + assign \reg2_ok 1'0 + assign \reg3 5'00000 + assign \reg3_ok 1'0 + assign \rego 5'00000 + assign \rego_ok 1'0 + assign \ea 5'00000 + assign \ea_ok 1'0 + assign \imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \imm_ok 1'0 + assign \zero_a 1'0 + assign \rc 1'0 + assign \rc_ok 1'0 + assign \oe 1'0 + assign \oe_ok 1'0 + assign \spr1 10'0000000000 + assign \spr1_ok 1'0 + assign \spro 10'0000000000 + assign \spro_ok 1'0 + assign \fast1 3'000 + assign \fast1_ok 1'0 + assign \fast2 3'000 + assign \fast2_ok 1'0 + assign \fasto1 3'000 + assign \fasto1_ok 1'0 + assign \fasto2 3'000 + assign \fasto2_ok 1'0 + assign \cr_in1 3'000 + assign \cr_in1_ok 1'0 + assign \cr_in2 3'000 + assign \cr_in2_ok 1'0 + assign \cr_in2$2 3'000 + assign \cr_in2_ok$1 1'0 + assign \read_cr_whole 1'0 + assign \cr_out 3'000 + assign \cr_out_ok 1'0 + assign \write_cr_whole 1'0 + assign \data_len 4'0000 + assign \invert_a 1'0 + assign \invert_out 1'0 + assign \input_carry 2'00 + assign \output_carry 1'0 + assign \is_32bit 1'0 + assign \is_signed 1'0 + assign \lk 1'0 + assign \byte_reverse 1'0 + assign \sign_extend 1'0 + assign \update 1'0 + assign \input_cr 1'0 + assign \output_cr 1'0 + assign \trapaddr 13'0000000000000 + assign \asmcode 8'00000000 + assign \traptype 5'00000 assign \insn \opcode_in + assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \insn_type $6 + assign \fn_unit \function_unit + assign { \reg1_ok \reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } + assign { \reg2_ok \reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } + assign { \reg3_ok \reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } + assign { \rego_ok \rego } { \dec_o_reg_o_ok \dec_o_reg_o } + assign { \ea_ok \ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } + assign { \imm_ok \imm } { \dec_b_imm_b_ok \dec_b_imm_b } + assign \zero_a \dec_a_immz_out + assign { \rc_ok \rc } { \dec_rc_rc_ok \dec_rc_rc } + assign { \oe_ok \oe } { \dec_oe_oe_ok \dec_oe_oe } + assign { \spr1_ok \spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } + assign { \spro_ok \spro } { \dec_o_spr_o_ok \dec_o_spr_o } + assign { \fast1_ok \fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } + assign { \fast2_ok \fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } + assign { \fasto1_ok \fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } + assign { \fasto2_ok \fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } + assign { \cr_in1_ok \cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } + assign { \cr_in2_ok \cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } + assign { \cr_in2_ok$1 \cr_in2$2 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } + assign \read_cr_whole \dec_cr_in_whole_reg + assign { \cr_out_ok \cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } + assign \write_cr_whole \dec_cr_out_whole_reg + assign \data_len \ldst_len + assign \invert_a \inv_a + assign \invert_out \inv_out + assign \input_carry \dec_cry_in + assign \output_carry \cry_out + assign \is_32bit \is_32b + assign \is_signed \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:634" + switch { \lk$4 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:634" + case 1'1 + assign \lk \dec_LK + end + switch { } + case + assign \byte_reverse \br + end + switch { } + case + assign \sign_extend \sgn_ext + end + switch { } + case + assign \update \upd + end + switch { } + case + assign \input_cr \cr_in [0] + end + switch { } + case + assign \output_cr \cr_out$3 [0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:646" + switch { $10 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:646" + case 1'1 + assign \trapaddr 13'0000001110000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:653" + switch { $12 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:653" + case 1'1 + assign { \trapaddr \traptype \update \sign_extend \byte_reverse \data_len \insn \is_signed \is_32bit \output_cr \input_cr \output_carry \input_carry \invert_out \zero_a \invert_a { \oe_ok \oe } { \rc_ok \rc } \lk \write_cr_whole { \cr_out_ok \cr_out } \read_cr_whole { \cr_in2_ok$1 \cr_in2$2 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } { \spr1_ok \spr1 } { \spro_ok \spro } { \imm_ok \imm } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \nia \asmcode \fn_unit \insn_type } 313'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \insn \opcode_in + assign \insn_type 7'0111111 + assign \fn_unit 11'00010000000 + assign \trapaddr 13'0000001110000 + assign \traptype 5'10000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" + switch { $18 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" + case 1'1 + assign \fasto1 3'101 + assign \fasto1_ok 1'1 + assign \fasto2 3'110 + assign \fasto2_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:674" + switch { $20 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:674" + case 1'1 + assign \fast1 3'101 + assign \fast1_ok 1'1 + assign \fast2 3'110 + assign \fast2_ok 1'1 + end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:81" wire width 32 \insn_in process $group_1 assign \insn_in 32'00000000000000000000000000000000 assign \insn_in \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" - wire width 32 \insn_in$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171" + wire width 32 \insn_in$22 process $group_2 - assign \insn_in$5 32'00000000000000000000000000000000 - assign \insn_in$5 \opcode_in + assign \insn_in$22 32'00000000000000000000000000000000 + assign \insn_in$22 \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199" - wire width 32 \insn_in$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" + wire width 32 \insn_in$23 process $group_3 - assign \insn_in$6 32'00000000000000000000000000000000 - assign \insn_in$6 \opcode_in + assign \insn_in$23 32'00000000000000000000000000000000 + assign \insn_in$23 \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - wire width 32 \insn_in$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276" + wire width 32 \insn_in$24 process $group_4 - assign \insn_in$7 32'00000000000000000000000000000000 - assign \insn_in$7 \opcode_in + assign \insn_in$24 32'00000000000000000000000000000000 + assign \insn_in$24 \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293" - wire width 32 \insn_in$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352" + wire width 32 \insn_in$25 process $group_5 - assign \insn_in$8 32'00000000000000000000000000000000 - assign \insn_in$8 \opcode_in + assign \insn_in$25 32'00000000000000000000000000000000 + assign \insn_in$25 \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330" - wire width 32 \insn_in$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389" + wire width 32 \insn_in$26 process $group_6 - assign \insn_in$9 32'00000000000000000000000000000000 - assign \insn_in$9 \opcode_in + assign \insn_in$26 32'00000000000000000000000000000000 + assign \insn_in$26 \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" - wire width 32 \insn_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:425" + wire width 32 \insn_in$27 process $group_7 - assign \insn_in$10 32'00000000000000000000000000000000 - assign \insn_in$10 \opcode_in + assign \insn_in$27 32'00000000000000000000000000000000 + assign \insn_in$27 \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:391" - wire width 32 \insn_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + wire width 32 \insn_in$28 process $group_8 - assign \insn_in$11 32'00000000000000000000000000000000 - assign \insn_in$11 \opcode_in + assign \insn_in$28 32'00000000000000000000000000000000 + assign \insn_in$28 \opcode_in sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443" - wire width 32 \insn_in$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + wire width 32 \insn_in$29 process $group_9 - assign \insn_in$12 32'00000000000000000000000000000000 - assign \insn_in$12 \opcode_in + assign \insn_in$29 32'00000000000000000000000000000000 + assign \insn_in$29 \opcode_in sync init end process $group_10 @@ -40355,7 +42899,7 @@ module \pdecode2 attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" wire width 2 \sel_in process $group_14 assign \sel_in 2'00 @@ -40392,263 +42936,6 @@ module \pdecode2 assign \dec_cr_out_rc_in \dec_rc_rc sync init end - wire width 1 $verilog_initial_trigger - process $group_21 - assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire width 7 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - cell $eq $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \function_unit - connect \B 10'0000000000 - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - cell $mux $16 - parameter \WIDTH 7 - connect \A \internal_op - connect \B 7'0000000 - connect \S $14 - connect \Y $13 - end - process $group_22 - assign \insn_type 7'0000000 - assign \insn_type $13 - sync init - end - process $group_23 - assign \fn_unit 10'0000000000 - assign \fn_unit \function_unit - sync init - end - process $group_24 - assign \reg1 5'00000 - assign \reg1_ok 1'0 - assign { \reg1_ok \reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } - sync init - end - process $group_26 - assign \reg2 5'00000 - assign \reg2_ok 1'0 - assign { \reg2_ok \reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } - sync init - end - process $group_28 - assign \reg3 5'00000 - assign \reg3_ok 1'0 - assign { \reg3_ok \reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } - sync init - end - process $group_30 - assign \rego 5'00000 - assign \rego_ok 1'0 - assign { \rego_ok \rego } { \dec_o_reg_o_ok \dec_o_reg_o } - sync init - end - process $group_32 - assign \ea 5'00000 - assign \ea_ok 1'0 - assign { \ea_ok \ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } - sync init - end - process $group_34 - assign \imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \imm_ok 1'0 - assign { \imm_ok \imm } { \dec_b_imm_b_ok \dec_b_imm_b } - sync init - end - process $group_36 - assign \zero_a 1'0 - assign \zero_a \dec_a_immz_out - sync init - end - process $group_37 - assign \rc 1'0 - assign \rc_ok 1'0 - assign { \rc_ok \rc } { \dec_rc_rc_ok \dec_rc_rc } - sync init - end - process $group_39 - assign \oe 1'0 - assign \oe_ok 1'0 - assign { \oe_ok \oe } { \dec_oe_oe_ok \dec_oe_oe } - sync init - end - process $group_41 - assign \spr1 10'0000000000 - assign \spr1_ok 1'0 - assign { \spr1_ok \spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } - sync init - end - process $group_43 - assign \spro 10'0000000000 - assign \spro_ok 1'0 - assign { \spro_ok \spro } { \dec_o_spr_o_ok \dec_o_spr_o } - sync init - end - process $group_45 - assign \fast1 3'000 - assign \fast1_ok 1'0 - assign { \fast1_ok \fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } - sync init - end - process $group_47 - assign \fast2 3'000 - assign \fast2_ok 1'0 - assign { \fast2_ok \fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } - sync init - end - process $group_49 - assign \fasto1 3'000 - assign \fasto1_ok 1'0 - assign { \fasto1_ok \fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } - sync init - end - process $group_51 - assign \fasto2 3'000 - assign \fasto2_ok 1'0 - assign { \fasto2_ok \fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } - sync init - end - process $group_53 - assign \cr_in1 3'000 - assign \cr_in1_ok 1'0 - assign { \cr_in1_ok \cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } - sync init - end - process $group_55 - assign \cr_in2 3'000 - assign \cr_in2_ok 1'0 - assign { \cr_in2_ok \cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } - sync init - end - process $group_57 - assign \cr_in2$2 3'000 - assign \cr_in2_ok$1 1'0 - assign { \cr_in2_ok$1 \cr_in2$2 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } - sync init - end - process $group_59 - assign \read_cr_whole 1'0 - assign \read_cr_whole \dec_cr_in_whole_reg - sync init - end - process $group_60 - assign \cr_out 3'000 - assign \cr_out_ok 1'0 - assign { \cr_out_ok \cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } - sync init - end - process $group_62 - assign \write_cr_whole 1'0 - assign \write_cr_whole \dec_cr_out_whole_reg - sync init - end - process $group_63 - assign \data_len 4'0000 - assign \data_len \ldst_len - sync init - end - process $group_64 - assign \invert_a 1'0 - assign \invert_a \inv_a - sync init - end - process $group_65 - assign \invert_out 1'0 - assign \invert_out \inv_out - sync init - end - process $group_66 - assign \input_carry 2'00 - assign \input_carry \dec_cry_in - sync init - end - process $group_67 - assign \output_carry 1'0 - assign \output_carry \cry_out - sync init - end - process $group_68 - assign \is_32bit 1'0 - assign \is_32bit \is_32b - sync init - end - process $group_69 - assign \is_signed 1'0 - assign \is_signed \sgn - sync init - end - process $group_70 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:573" - switch { \lk$4 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:573" - case 1'1 - assign \lk \dec_LK - end - sync init - end - process $group_71 - assign \byte_reverse 1'0 - assign \byte_reverse \br - sync init - end - process $group_72 - assign \sign_extend 1'0 - assign \sign_extend \sgn_ext - sync init - end - process $group_73 - assign \update 1'0 - assign \update \upd - sync init - end - process $group_74 - assign \input_cr 1'0 - assign \input_cr \cr_in [0] - sync init - end - process $group_75 - assign \output_cr 1'0 - assign \output_cr \cr_out$3 [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:586" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:586" - cell $eq $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0111111 - connect \Y $17 - end - process $group_76 - assign \trapaddr 13'0000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:586" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:586" - case 1'1 - assign \trapaddr 13'0000001110000 - end - sync init - end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.p" @@ -40708,7 +42995,7 @@ module \n end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.p" -module \p$1 +module \p$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -40736,7 +43023,7 @@ module \p$1 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.n" -module \n$2 +module \n$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -40842,18 +43129,19 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 input 1 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 input 2 \op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 input 2 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 input 3 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -40987,18 +43275,19 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 output 30 \op__insn_type$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 output 31 \op__fn_unit$3 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 output 31 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 output 32 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -41121,7 +43410,7 @@ module \input end process $group_5 assign \op__insn_type$2 7'0000000 - assign \op__fn_unit$3 10'0000000000 + assign \op__fn_unit$3 11'00000000000 assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$5 1'0 assign \op__lk$6 1'0 @@ -41233,18 +43522,19 @@ module \main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 input 1 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 input 2 \op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 input 2 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 input 3 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -41378,18 +43668,19 @@ module \main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 output 30 \op__insn_type$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 output 31 \op__fn_unit$3 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 output 31 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 output 32 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -42228,7 +44519,7 @@ module \main end process $group_19 assign \op__insn_type$2 7'0000000 - assign \op__fn_unit$3 10'0000000000 + assign \op__fn_unit$3 11'00000000000 assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$5 1'0 assign \op__lk$6 1'0 @@ -42335,18 +44626,19 @@ module \output attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 input 1 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 input 2 \op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 input 2 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 input 3 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -42484,18 +44776,19 @@ module \output attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 output 32 \op__insn_type$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 output 33 \op__fn_unit$3 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 output 33 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 output 34 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -42825,7 +45118,7 @@ module \output end process $group_16 assign \op__insn_type$2 7'0000000 - assign \op__fn_unit$3 10'0000000000 + assign \op__fn_unit$3 11'00000000000 assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$5 1'0 assign \op__lk$6 1'0 @@ -43004,18 +45297,19 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 input 5 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 input 6 \op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 input 6 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 input 7 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -43157,20 +45451,21 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 \op__insn_type$2$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 output 37 \op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \op__fn_unit$3$next + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 output 37 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 output 38 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -43303,11 +45598,11 @@ module \pipe wire width 1 output 69 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \xer_so_ok$next - cell \p$1 \p + cell \p$2 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$2 \n + cell \n$3 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -43388,18 +45683,19 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 \input_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \input_op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \input_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 \input_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -43533,18 +45829,19 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 \input_op__insn_type$29 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \input_op__fn_unit$30 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \input_op__fn_unit$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 \input_op__imm_data__imm$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -43738,18 +46035,19 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 \main_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \main_op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \main_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 \main_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -43883,18 +46181,19 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 \main_op__insn_type$58 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \main_op__fn_unit$59 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \main_op__fn_unit$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 \main_op__imm_data__imm$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -44103,18 +46402,19 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 \output_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \output_op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \output_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 \output_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -44252,18 +46552,19 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 \output_op__insn_type$85 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \output_op__fn_unit$86 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \output_op__fn_unit$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 \output_op__imm_data__imm$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -44407,7 +46708,7 @@ module \pipe end process $group_1 assign \input_op__insn_type 7'0000000 - assign \input_op__fn_unit 10'0000000000 + assign \input_op__fn_unit 11'00000000000 assign \input_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \input_op__imm_data__imm_ok 1'0 assign \input_op__lk 1'0 @@ -44460,7 +46761,7 @@ module \pipe end process $group_30 assign \main_op__insn_type 7'0000000 - assign \main_op__fn_unit 10'0000000000 + assign \main_op__fn_unit 11'00000000000 assign \main_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \main_op__imm_data__imm_ok 1'0 assign \main_op__lk 1'0 @@ -44513,7 +46814,7 @@ module \pipe end process $group_59 assign \output_op__insn_type 7'0000000 - assign \output_op__fn_unit 10'0000000000 + assign \output_op__fn_unit 11'00000000000 assign \output_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \output_op__imm_data__imm_ok 1'0 assign \output_op__lk 1'0 @@ -44695,18 +46996,19 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 \op__insn_type$124 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \op__fn_unit$125 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \op__fn_unit$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 \op__imm_data__imm$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -44757,7 +47059,7 @@ module \pipe wire width 1 \op__sign_extend$147 process $group_97 assign \op__insn_type$124 7'0000000 - assign \op__fn_unit$125 10'0000000000 + assign \op__fn_unit$125 11'00000000000 assign \op__imm_data__imm$126 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$127 1'0 assign \op__lk$128 1'0 @@ -44923,7 +47225,7 @@ module \pipe end sync init update \op__insn_type$2 7'0000000 - update \op__fn_unit$3 10'0000000000 + update \op__fn_unit$3 11'00000000000 update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 update \op__imm_data__imm_ok$5 1'0 update \op__lk$6 1'0 @@ -45210,18 +47512,19 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 input 14 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 input 15 \op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 input 15 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 input 16 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -45371,18 +47674,19 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 \pipe_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \pipe_op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \pipe_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 \pipe_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -45520,18 +47824,19 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 \pipe_op__insn_type$4 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \pipe_op__fn_unit$5 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \pipe_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 \pipe_op__imm_data__imm$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -45691,7 +47996,7 @@ module \alu_alu0 end process $group_3 assign \pipe_op__insn_type 7'0000000 - assign \pipe_op__fn_unit 10'0000000000 + assign \pipe_op__fn_unit 11'00000000000 assign \pipe_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pipe_op__imm_data__imm_ok 1'0 assign \pipe_op__lk 1'0 @@ -45829,18 +48134,19 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 \op__insn_type$31 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \op__fn_unit$32 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \op__fn_unit$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 \op__imm_data__imm$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -45891,7 +48197,7 @@ module \alu_alu0 wire width 1 \op__sign_extend$54 process $group_34 assign \op__insn_type$31 7'0000000 - assign \op__fn_unit$32 10'0000000000 + assign \op__fn_unit$32 11'00000000000 assign \op__imm_data__imm$33 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$34 1'0 assign \op__lk$35 1'0 @@ -47046,18 +49352,19 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 input 2 \oper_i__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 input 3 \oper_i__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 input 3 \oper_i__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 input 4 \oper_i__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -47233,18 +49540,19 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 \alu_alu0_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \alu_alu0_op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \alu_alu0_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 \alu_alu0_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -48163,18 +50471,19 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 \oper_r__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \oper_r__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \oper_r__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 \oper_r__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -48228,9 +50537,9 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 7 \oper_l__insn_type$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 10 \oper_l__fn_unit + wire width 11 \oper_l__fn_unit attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 10 \oper_l__fn_unit$next + wire width 11 \oper_l__fn_unit$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \oper_l__imm_data__imm attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" @@ -48320,10 +50629,10 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \oper_l__sign_extend$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 139 $69 + wire width 140 $69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" cell $mux $70 - parameter \WIDTH 139 + parameter \WIDTH 140 connect \A { \oper_l__sign_extend \oper_l__byte_reverse \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } \oper_l__invert_out \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } connect \B { \oper_i__sign_extend \oper_i__byte_reverse \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } connect \S \issue_i @@ -48331,7 +50640,7 @@ module \alu0 end process $group_25 assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 10'0000000000 + assign \oper_r__fn_unit 11'00000000000 assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \oper_r__imm_data__imm_ok 1'0 assign \oper_r__lk 1'0 @@ -48403,7 +50712,7 @@ module \alu0 end sync init update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 10'0000000000 + update \oper_l__fn_unit 11'00000000000 update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 update \oper_l__imm_data__imm_ok 1'0 update \oper_l__lk 1'0 @@ -48804,7 +51113,7 @@ module \alu0 end process $group_94 assign \alu_alu0_op__insn_type 7'0000000 - assign \alu_alu0_op__fn_unit 10'0000000000 + assign \alu_alu0_op__fn_unit 11'00000000000 assign \alu_alu0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \alu_alu0_op__imm_data__imm_ok 1'0 assign \alu_alu0_op__lk 1'0 @@ -49334,7 +51643,7 @@ module \alu0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.p" -module \p$3 +module \p$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -49362,7 +51671,7 @@ module \p$3 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.n" -module \n$4 +module \n$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -49390,7 +51699,7 @@ module \n$4 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.p" -module \p$6 +module \p$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -49418,7 +51727,7 @@ module \p$6 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.n" -module \n$7 +module \n$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -49446,7 +51755,7 @@ module \n$7 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.main" -module \main$8 +module \main$9 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -49524,18 +51833,19 @@ module \main$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 input 1 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 input 2 \op__fn_unit + wire width 11 input 2 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 input 3 \op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -49631,18 +51941,19 @@ module \main$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 output 13 \op__insn_type$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 output 14 \op__fn_unit$3 + wire width 11 output 14 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 output 15 \op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -50300,7 +52611,7 @@ module \main$8 end process $group_17 assign \op__insn_type$2 7'0000000 - assign \op__fn_unit$3 10'0000000000 + assign \op__fn_unit$3 11'00000000000 assign \op__insn$4 32'00000000000000000000000000000000 assign \op__read_cr_whole$5 1'0 assign \op__write_cr_whole$6 1'0 @@ -50310,7 +52621,7 @@ module \main$8 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe" -module \pipe$5 +module \pipe$6 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -50396,18 +52707,19 @@ module \pipe$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 input 5 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 input 6 \op__fn_unit + wire width 11 input 6 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 input 7 \op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -50511,20 +52823,21 @@ module \pipe$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 \op__insn_type$2$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 output 20 \op__fn_unit$3 + wire width 11 output 20 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 \op__fn_unit$3$next + wire width 11 \op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 output 21 \op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -50561,11 +52874,11 @@ module \pipe$5 wire width 1 output 29 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \cr_a_ok$next - cell \p$6 \p + cell \p$7 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$7 \n + cell \n$8 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -50646,18 +52959,19 @@ module \pipe$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 \main_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 \main_op__fn_unit + wire width 11 \main_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 \main_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -50753,18 +53067,19 @@ module \pipe$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 \main_op__insn_type$10 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 \main_op__fn_unit$11 + wire width 11 \main_op__fn_unit$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 \main_op__insn$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -50783,7 +53098,7 @@ module \pipe$5 wire width 4 \main_cr_a$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \main_cr_a_ok - cell \main$8 \main + cell \main$9 \main connect \muxid \main_muxid connect \op__insn_type \main_op__insn_type connect \op__fn_unit \main_op__fn_unit @@ -50816,7 +53131,7 @@ module \pipe$5 end process $group_1 assign \main_op__insn_type 7'0000000 - assign \main_op__fn_unit 10'0000000000 + assign \main_op__fn_unit 11'00000000000 assign \main_op__insn 32'00000000000000000000000000000000 assign \main_op__read_cr_whole 1'0 assign \main_op__write_cr_whole 1'0 @@ -50969,18 +53284,19 @@ module \pipe$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 \op__insn_type$21 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 \op__fn_unit$22 + wire width 11 \op__fn_unit$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 \op__insn$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -50989,7 +53305,7 @@ module \pipe$5 wire width 1 \op__write_cr_whole$25 process $group_16 assign \op__insn_type$21 7'0000000 - assign \op__fn_unit$22 10'0000000000 + assign \op__fn_unit$22 11'00000000000 assign \op__insn$23 32'00000000000000000000000000000000 assign \op__read_cr_whole$24 1'0 assign \op__write_cr_whole$25 1'0 @@ -51084,7 +53400,7 @@ module \pipe$5 end sync init update \op__insn_type$2 7'0000000 - update \op__fn_unit$3 10'0000000000 + update \op__fn_unit$3 11'00000000000 update \op__insn$4 32'00000000000000000000000000000000 update \op__read_cr_whole$5 1'0 update \op__write_cr_whole$6 1'0 @@ -51276,18 +53592,19 @@ module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 input 10 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 input 11 \op__fn_unit + wire width 11 input 11 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 input 12 \op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -51310,11 +53627,11 @@ module \alu_cr0 wire width 1 input 21 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 output 22 \p_ready_o - cell \p$3 \p + cell \p$4 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$4 \n + cell \n$5 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -51399,18 +53716,19 @@ module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 \pipe_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 \pipe_op__fn_unit + wire width 11 \pipe_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 \pipe_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -51510,18 +53828,19 @@ module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 \pipe_op__insn_type$4 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 \pipe_op__fn_unit$5 + wire width 11 \pipe_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 \pipe_op__insn$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -51540,7 +53859,7 @@ module \alu_cr0 wire width 4 \pipe_cr_a$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \pipe_cr_a_ok - cell \pipe$5 \pipe + cell \pipe$6 \pipe connect \rst \rst connect \clk \clk connect \p_valid_i \pipe_p_valid_i @@ -51591,7 +53910,7 @@ module \alu_cr0 end process $group_3 assign \pipe_op__insn_type 7'0000000 - assign \pipe_op__fn_unit 10'0000000000 + assign \pipe_op__fn_unit 11'00000000000 assign \pipe_op__insn 32'00000000000000000000000000000000 assign \pipe_op__read_cr_whole 1'0 assign \pipe_op__write_cr_whole 1'0 @@ -51720,18 +54039,19 @@ module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 \op__insn_type$12 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 \op__fn_unit$13 + wire width 11 \op__fn_unit$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 \op__insn$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -51740,7 +54060,7 @@ module \alu_cr0 wire width 1 \op__write_cr_whole$16 process $group_17 assign \op__insn_type$12 7'0000000 - assign \op__fn_unit$13 10'0000000000 + assign \op__fn_unit$13 11'00000000000 assign \op__insn$14 32'00000000000000000000000000000000 assign \op__read_cr_whole$15 1'0 assign \op__write_cr_whole$16 1'0 @@ -51769,7 +54089,7 @@ module \alu_cr0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.src_l" -module \src_l$9 +module \src_l$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -51914,7 +54234,7 @@ module \src_l$9 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.opc_l" -module \opc_l$10 +module \opc_l$11 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -52059,7 +54379,7 @@ module \opc_l$10 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.req_l" -module \req_l$11 +module \req_l$12 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -52204,7 +54524,7 @@ module \req_l$11 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rst_l" -module \rst_l$12 +module \rst_l$13 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -52349,7 +54669,7 @@ module \rst_l$12 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rok_l" -module \rok_l$13 +module \rok_l$14 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -52494,7 +54814,7 @@ module \rok_l$13 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alui_l" -module \alui_l$14 +module \alui_l$15 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -52639,7 +54959,7 @@ module \alui_l$14 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_l" -module \alu_l$15 +module \alu_l$16 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -52864,18 +55184,19 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 input 2 \oper_i__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 input 3 \oper_i__fn_unit + wire width 11 input 3 \oper_i__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 input 4 \oper_i__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -53005,18 +55326,19 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 \alu_cr0_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 \alu_cr0_op__fn_unit + wire width 11 \alu_cr0_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 \alu_cr0_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -53074,7 +55396,7 @@ module \cr0 wire width 6 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 6 \src_l_q_src - cell \src_l$9 \src_l + cell \src_l$10 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src @@ -53091,7 +55413,7 @@ module \cr0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$10 \opc_l + cell \opc_l$11 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc @@ -53104,7 +55426,7 @@ module \cr0 wire width 3 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 \req_l_r_req - cell \req_l$11 \req_l + cell \req_l$12 \req_l connect \rst \rst connect \clk \clk connect \q_req \req_l_q_req @@ -53115,7 +55437,7 @@ module \cr0 wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst - cell \rst_l$12 \rst_l + cell \rst_l$13 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst @@ -53129,7 +55451,7 @@ module \cr0 wire width 1 \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$13 \rok_l + cell \rok_l$14 \rok_l connect \rst \rst connect \clk \clk connect \q_rdok \rok_l_q_rdok @@ -53144,7 +55466,7 @@ module \cr0 wire width 1 \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$14 \alui_l + cell \alui_l$15 \alui_l connect \rst \rst connect \clk \clk connect \q_alui \alui_l_q_alui @@ -53159,7 +55481,7 @@ module \cr0 wire width 1 \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$15 \alu_l + cell \alu_l$16 \alu_l connect \rst \rst connect \clk \clk connect \q_alu \alu_l_q_alu @@ -53876,18 +56198,19 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 7 \oper_r__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 \oper_r__fn_unit + wire width 11 \oper_r__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 \oper_r__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -53899,9 +56222,9 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 7 \oper_l__insn_type$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 10 \oper_l__fn_unit + wire width 11 \oper_l__fn_unit attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 10 \oper_l__fn_unit$next + wire width 11 \oper_l__fn_unit$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 32 \oper_l__insn attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" @@ -53915,10 +56238,10 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \oper_l__write_cr_whole$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 51 $69 + wire width 52 $69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" cell $mux $70 - parameter \WIDTH 51 + parameter \WIDTH 52 connect \A { \oper_l__write_cr_whole \oper_l__read_cr_whole \oper_l__insn \oper_l__fn_unit \oper_l__insn_type } connect \B { \oper_i__write_cr_whole \oper_i__read_cr_whole \oper_i__insn \oper_i__fn_unit \oper_i__insn_type } connect \S \issue_i @@ -53926,7 +56249,7 @@ module \cr0 end process $group_25 assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 10'0000000000 + assign \oper_r__fn_unit 11'00000000000 assign \oper_r__insn 32'00000000000000000000000000000000 assign \oper_r__read_cr_whole 1'0 assign \oper_r__write_cr_whole 1'0 @@ -53947,7 +56270,7 @@ module \cr0 end sync init update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 10'0000000000 + update \oper_l__fn_unit 11'00000000000 update \oper_l__insn 32'00000000000000000000000000000000 update \oper_l__read_cr_whole 1'0 update \oper_l__write_cr_whole 1'0 @@ -54172,7 +56495,7 @@ module \cr0 end process $group_48 assign \alu_cr0_op__insn_type 7'0000000 - assign \alu_cr0_op__fn_unit 10'0000000000 + assign \alu_cr0_op__fn_unit 11'00000000000 assign \alu_cr0_op__insn 32'00000000000000000000000000000000 assign \alu_cr0_op__read_cr_whole 1'0 assign \alu_cr0_op__write_cr_whole 1'0 @@ -54609,7 +56932,7 @@ module \cr0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.p" -module \p$16 +module \p$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -54637,7 +56960,7 @@ module \p$16 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.n" -module \n$17 +module \n$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -54665,7 +56988,7 @@ module \n$17 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.p" -module \p$19 +module \p$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -54693,7 +57016,7 @@ module \p$19 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.n" -module \n$20 +module \n$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -54721,7 +57044,7 @@ module \n$20 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.main" -module \main$21 +module \main$22 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -54799,18 +57122,19 @@ module \main$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 input 1 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 input 2 \op__fn_unit + wire width 11 input 2 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 input 3 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -54822,9 +57146,9 @@ module \main$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 32 input 7 \op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 input 8 \spr1 + wire width 64 input 8 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 input 9 \spr2 + wire width 64 input 9 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 4 input 10 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -54906,18 +57230,19 @@ module \main$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 output 13 \op__insn_type$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 output 14 \op__fn_unit$3 + wire width 11 output 14 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 output 15 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -54929,13 +57254,13 @@ module \main$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 32 output 19 \op__insn$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 20 \spr1$9 + wire width 64 output 20 \fast1$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 21 \spr1_ok + wire width 1 output 21 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 22 \spr2$10 + wire width 64 output 22 \fast2$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 23 \spr2_ok + wire width 1 output 23 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 output 24 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -55180,7 +57505,7 @@ module \main$21 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 65 - connect \A \spr1 + connect \A \fast1 connect \B 1'1 connect \Y $35 end @@ -55198,14 +57523,14 @@ module \main$21 sync init end process $group_6 - assign \spr1$9 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast1$9 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97" switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97" case 1'1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:99" case - assign \spr1$9 \ctr_n + assign \fast1$9 \ctr_n end sync init end @@ -55218,7 +57543,7 @@ module \main$21 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 - connect \A \spr1 [31:0] + connect \A \fast1 [31:0] connect \Y $37 end process $group_7 @@ -55236,7 +57561,7 @@ module \main$21 assign \ctr_m $37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:109" case - assign \ctr_m \spr1 + assign \ctr_m \fast1 end end sync init @@ -55318,10 +57643,10 @@ module \main$21 switch { $45 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" case 1'1 - assign \br_imm_addr { \spr1 [63:2] 2'00 } + assign \br_imm_addr { \fast1 [63:2] 2'00 } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" case - assign \br_imm_addr { \spr2 [63:2] 2'00 } + assign \br_imm_addr { \fast2 [63:2] 2'00 } end end sync init @@ -55348,7 +57673,7 @@ module \main$21 sync init end process $group_11 - assign \spr1_ok 1'0 + assign \fast1_ok 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" switch \op__insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" @@ -55357,11 +57682,11 @@ module \main$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" attribute \nmigen.decoding "OP_BC/7" case 7'0000111 - assign \spr1_ok \ctr_write + assign \fast1_ok \ctr_write attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" attribute \nmigen.decoding "OP_BCREG/8" case 7'0001000 - assign \spr1_ok \ctr_write + assign \fast1_ok \ctr_write end sync init end @@ -55392,22 +57717,22 @@ module \main$21 end connect $47 $48 process $group_14 - assign \spr2$10 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast2$10 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:149" switch { \op__lk } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:149" case 1'1 - assign \spr2$10 $47 [63:0] + assign \fast2$10 $47 [63:0] end sync init end process $group_15 - assign \spr2_ok 1'0 + assign \fast2_ok 1'0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:149" switch { \op__lk } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:149" case 1'1 - assign \spr2_ok 1'1 + assign \fast2_ok 1'1 end sync init end @@ -55418,7 +57743,7 @@ module \main$21 end process $group_17 assign \op__insn_type$2 7'0000000 - assign \op__fn_unit$3 10'0000000000 + assign \op__fn_unit$3 11'00000000000 assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$5 1'0 assign \op__lk$6 1'0 @@ -55430,7 +57755,7 @@ module \main$21 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe" -module \pipe$18 +module \pipe$19 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -55516,18 +57841,19 @@ module \pipe$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 input 5 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 input 6 \op__fn_unit + wire width 11 input 6 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 input 7 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -55539,9 +57865,9 @@ module \pipe$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 32 input 11 \op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 input 12 \spr1 + wire width 64 input 12 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 input 13 \spr2 + wire width 64 input 13 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 4 input 14 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -55631,20 +57957,21 @@ module \pipe$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 \op__insn_type$2$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 output 20 \op__fn_unit$3 + wire width 11 output 20 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 \op__fn_unit$3$next + wire width 11 \op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 output 21 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -55666,21 +57993,21 @@ module \pipe$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 32 \op__insn$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 26 \spr1$9 + wire width 64 output 26 \fast1$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \spr1$9$next + wire width 64 \fast1$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 27 \spr1_ok + wire width 1 output 27 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \spr1_ok$next + wire width 1 \fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 28 \spr2$10 + wire width 64 output 28 \fast2$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \spr2$10$next + wire width 64 \fast2$10$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 29 \spr2_ok + wire width 1 output 29 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \spr2_ok$next + wire width 1 \fast2_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 output 30 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -55689,11 +58016,11 @@ module \pipe$18 wire width 1 output 31 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \nia_ok$next - cell \p$19 \p + cell \p$20 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$20 \n + cell \n$21 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -55774,18 +58101,19 @@ module \pipe$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 \main_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 \main_op__fn_unit + wire width 11 \main_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 \main_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -55797,9 +58125,9 @@ module \pipe$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 32 \main_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \main_spr1 + wire width 64 \main_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \main_spr2 + wire width 64 \main_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 4 \main_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -55881,18 +58209,19 @@ module \pipe$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 \main_op__insn_type$12 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 \main_op__fn_unit$13 + wire width 11 \main_op__fn_unit$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 \main_op__imm_data__imm$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -55904,18 +58233,18 @@ module \pipe$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 32 \main_op__insn$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \main_spr1$19 + wire width 64 \main_fast1$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \main_spr1_ok + wire width 1 \main_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \main_spr2$20 + wire width 64 \main_fast2$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \main_spr2_ok + wire width 1 \main_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 \main_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \main_nia_ok - cell \main$21 \main + cell \main$22 \main connect \muxid \main_muxid connect \op__insn_type \main_op__insn_type connect \op__fn_unit \main_op__fn_unit @@ -55924,8 +58253,8 @@ module \pipe$18 connect \op__lk \main_op__lk connect \op__is_32bit \main_op__is_32bit connect \op__insn \main_op__insn - connect \spr1 \main_spr1 - connect \spr2 \main_spr2 + connect \fast1 \main_fast1 + connect \fast2 \main_fast2 connect \cr_a \main_cr_a connect \cia \main_cia connect \muxid$1 \main_muxid$11 @@ -55936,10 +58265,10 @@ module \pipe$18 connect \op__lk$6 \main_op__lk$16 connect \op__is_32bit$7 \main_op__is_32bit$17 connect \op__insn$8 \main_op__insn$18 - connect \spr1$9 \main_spr1$19 - connect \spr1_ok \main_spr1_ok - connect \spr2$10 \main_spr2$20 - connect \spr2_ok \main_spr2_ok + connect \fast1$9 \main_fast1$19 + connect \fast1_ok \main_fast1_ok + connect \fast2$10 \main_fast2$20 + connect \fast2_ok \main_fast2_ok connect \nia \main_nia connect \nia_ok \main_nia_ok end @@ -55950,7 +58279,7 @@ module \pipe$18 end process $group_1 assign \main_op__insn_type 7'0000000 - assign \main_op__fn_unit 10'0000000000 + assign \main_op__fn_unit 11'00000000000 assign \main_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \main_op__imm_data__imm_ok 1'0 assign \main_op__lk 1'0 @@ -55960,13 +58289,13 @@ module \pipe$18 sync init end process $group_8 - assign \main_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_spr1 \spr1 + assign \main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_fast1 \fast1 sync init end process $group_9 - assign \main_spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_spr2 \spr2 + assign \main_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_fast2 \fast2 sync init end process $group_10 @@ -56095,18 +58424,19 @@ module \pipe$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 \op__insn_type$25 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 \op__fn_unit$26 + wire width 11 \op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 \op__imm_data__imm$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -56119,7 +58449,7 @@ module \pipe$18 wire width 32 \op__insn$31 process $group_16 assign \op__insn_type$25 7'0000000 - assign \op__fn_unit$26 10'0000000000 + assign \op__fn_unit$26 11'00000000000 assign \op__imm_data__imm$27 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$28 1'0 assign \op__lk$29 1'0 @@ -56129,23 +58459,23 @@ module \pipe$18 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \spr1$32 + wire width 64 \fast1$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \spr1_ok$33 + wire width 1 \fast1_ok$33 process $group_23 - assign \spr1$32 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr1_ok$33 1'0 - assign { \spr1_ok$33 \spr1$32 } { \main_spr1_ok \main_spr1$19 } + assign \fast1$32 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast1_ok$33 1'0 + assign { \fast1_ok$33 \fast1$32 } { \main_fast1_ok \main_fast1$19 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \spr2$34 + wire width 64 \fast2$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \spr2_ok$35 + wire width 1 \fast2_ok$35 process $group_25 - assign \spr2$34 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr2_ok$35 1'0 - assign { \spr2_ok$35 \spr2$34 } { \main_spr2_ok \main_spr2$20 } + assign \fast2$34 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast2_ok$35 1'0 + assign { \fast2_ok$35 \fast2$34 } { \main_fast2_ok \main_fast2$20 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -56224,7 +58554,7 @@ module \pipe$18 end sync init update \op__insn_type$2 7'0000000 - update \op__fn_unit$3 10'0000000000 + update \op__fn_unit$3 11'00000000000 update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 update \op__imm_data__imm_ok$5 1'0 update \op__lk$6 1'0 @@ -56240,52 +58570,52 @@ module \pipe$18 update \op__insn$8 \op__insn$8$next end process $group_38 - assign \spr1$9$next \spr1$9 - assign \spr1_ok$next \spr1_ok + assign \fast1$9$next \fast1$9 + assign \fast1_ok$next \fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \spr1_ok$next \spr1$9$next } { \spr1_ok$33 \spr1$32 } + assign { \fast1_ok$next \fast1$9$next } { \fast1_ok$33 \fast1$32 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \spr1_ok$next \spr1$9$next } { \spr1_ok$33 \spr1$32 } + assign { \fast1_ok$next \fast1$9$next } { \fast1_ok$33 \fast1$32 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \spr1_ok$next 1'0 + assign \fast1_ok$next 1'0 end sync init - update \spr1$9 64'0000000000000000000000000000000000000000000000000000000000000000 - update \spr1_ok 1'0 + update \fast1$9 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast1_ok 1'0 sync posedge \clk - update \spr1$9 \spr1$9$next - update \spr1_ok \spr1_ok$next + update \fast1$9 \fast1$9$next + update \fast1_ok \fast1_ok$next end process $group_40 - assign \spr2$10$next \spr2$10 - assign \spr2_ok$next \spr2_ok + assign \fast2$10$next \fast2$10 + assign \fast2_ok$next \fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \spr2_ok$next \spr2$10$next } { \spr2_ok$35 \spr2$34 } + assign { \fast2_ok$next \fast2$10$next } { \fast2_ok$35 \fast2$34 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \spr2_ok$next \spr2$10$next } { \spr2_ok$35 \spr2$34 } + assign { \fast2_ok$next \fast2$10$next } { \fast2_ok$35 \fast2$34 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \spr2_ok$next 1'0 + assign \fast2_ok$next 1'0 end sync init - update \spr2$10 64'0000000000000000000000000000000000000000000000000000000000000000 - update \spr2_ok 1'0 + update \fast2$10 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast2_ok 1'0 sync posedge \clk - update \spr2$10 \spr2$10$next - update \spr2_ok \spr2_ok$next + update \fast2$10 \fast2$10$next + update \fast2_ok \fast2_ok$next end process $group_42 assign \nia$next \nia @@ -56330,13 +58660,13 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 2 \spr1_ok + wire width 1 output 2 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 3 \spr1 + wire width 64 output 3 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 4 \spr2_ok + wire width 1 output 4 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 5 \spr2 + wire width 64 output 5 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 6 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -56420,18 +58750,19 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 input 10 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 input 11 \op__fn_unit + wire width 11 input 11 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 input 12 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -56443,9 +58774,9 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 32 input 16 \op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 input 17 \spr1$1 + wire width 64 input 17 \fast1$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 input 18 \spr2$2 + wire width 64 input 18 \fast2$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 4 input 19 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -56454,11 +58785,11 @@ module \alu_branch0 wire width 1 input 21 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 output 22 \p_ready_o - cell \p$16 \p + cell \p$17 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$17 \n + cell \n$18 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -56543,18 +58874,19 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 \pipe_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 \pipe_op__fn_unit + wire width 11 \pipe_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 \pipe_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -56566,9 +58898,9 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 32 \pipe_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \pipe_spr1 + wire width 64 \pipe_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \pipe_spr2 + wire width 64 \pipe_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 4 \pipe_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -56654,18 +58986,19 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 \pipe_op__insn_type$4 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 \pipe_op__fn_unit$5 + wire width 11 \pipe_op__fn_unit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 \pipe_op__imm_data__imm$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -56677,18 +59010,18 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 32 \pipe_op__insn$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \pipe_spr1$11 + wire width 64 \pipe_fast1$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \pipe_spr1_ok + wire width 1 \pipe_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \pipe_spr2$12 + wire width 64 \pipe_fast2$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \pipe_spr2_ok + wire width 1 \pipe_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 \pipe_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \pipe_nia_ok - cell \pipe$18 \pipe + cell \pipe$19 \pipe connect \rst \rst connect \clk \clk connect \p_valid_i \pipe_p_valid_i @@ -56701,8 +59034,8 @@ module \alu_branch0 connect \op__lk \pipe_op__lk connect \op__is_32bit \pipe_op__is_32bit connect \op__insn \pipe_op__insn - connect \spr1 \pipe_spr1 - connect \spr2 \pipe_spr2 + connect \fast1 \pipe_fast1 + connect \fast2 \pipe_fast2 connect \cr_a \pipe_cr_a connect \cia \pipe_cia connect \n_valid_o \pipe_n_valid_o @@ -56715,10 +59048,10 @@ module \alu_branch0 connect \op__lk$6 \pipe_op__lk$8 connect \op__is_32bit$7 \pipe_op__is_32bit$9 connect \op__insn$8 \pipe_op__insn$10 - connect \spr1$9 \pipe_spr1$11 - connect \spr1_ok \pipe_spr1_ok - connect \spr2$10 \pipe_spr2$12 - connect \spr2_ok \pipe_spr2_ok + connect \fast1$9 \pipe_fast1$11 + connect \fast1_ok \pipe_fast1_ok + connect \fast2$10 \pipe_fast2$12 + connect \fast2_ok \pipe_fast2_ok connect \nia \pipe_nia connect \nia_ok \pipe_nia_ok end @@ -56741,7 +59074,7 @@ module \alu_branch0 end process $group_3 assign \pipe_op__insn_type 7'0000000 - assign \pipe_op__fn_unit 10'0000000000 + assign \pipe_op__fn_unit 11'00000000000 assign \pipe_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pipe_op__imm_data__imm_ok 1'0 assign \pipe_op__lk 1'0 @@ -56751,13 +59084,13 @@ module \alu_branch0 sync init end process $group_10 - assign \pipe_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_spr1 \spr1$1 + assign \pipe_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_fast1 \fast1$1 sync init end process $group_11 - assign \pipe_spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_spr2 \spr2$2 + assign \pipe_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_fast2 \fast2$2 sync init end process $group_12 @@ -56862,18 +59195,19 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 \op__insn_type$14 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 \op__fn_unit$15 + wire width 11 \op__fn_unit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 \op__imm_data__imm$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -56886,7 +59220,7 @@ module \alu_branch0 wire width 32 \op__insn$20 process $group_17 assign \op__insn_type$14 7'0000000 - assign \op__fn_unit$15 10'0000000000 + assign \op__fn_unit$15 11'00000000000 assign \op__imm_data__imm$16 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$17 1'0 assign \op__lk$18 1'0 @@ -56896,15 +59230,15 @@ module \alu_branch0 sync init end process $group_24 - assign \spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr1_ok 1'0 - assign { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } + assign \fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast1_ok 1'0 + assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$11 } sync init end process $group_26 - assign \spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr2_ok 1'0 - assign { \spr2_ok \spr2 } { \pipe_spr2_ok \pipe_spr2$12 } + assign \fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast2_ok 1'0 + assign { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$12 } sync init end process $group_28 @@ -56917,7 +59251,7 @@ module \alu_branch0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.src_l" -module \src_l$22 +module \src_l$23 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -57062,7 +59396,7 @@ module \src_l$22 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.opc_l" -module \opc_l$23 +module \opc_l$24 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -57207,7 +59541,7 @@ module \opc_l$23 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.req_l" -module \req_l$24 +module \req_l$25 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -57352,7 +59686,7 @@ module \req_l$24 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rst_l" -module \rst_l$25 +module \rst_l$26 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -57497,7 +59831,7 @@ module \rst_l$25 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rok_l" -module \rok_l$26 +module \rok_l$27 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -57642,7 +59976,7 @@ module \rok_l$26 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alui_l" -module \alui_l$27 +module \alui_l$28 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -57787,7 +60121,7 @@ module \alui_l$27 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_l" -module \alu_l$28 +module \alu_l$29 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -58012,18 +60346,19 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 input 2 \oper_i__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 input 3 \oper_i__fn_unit + wire width 11 input 3 \oper_i__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 input 4 \oper_i__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -58053,17 +60388,17 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" wire width 64 input 17 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 18 \spr1_ok + wire width 1 output 18 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" wire width 3 output 19 \wr__rel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" wire width 3 input 20 \wr__go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 21 \spr1 + wire width 64 output 21 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 22 \spr2_ok + wire width 1 output 22 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 23 \spr2 + wire width 64 output 23 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 24 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -58153,18 +60488,19 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 \alu_branch0_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 \alu_branch0_op__fn_unit + wire width 11 \alu_branch0_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 \alu_branch0_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -58176,9 +60512,9 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 32 \alu_branch0_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_branch0_spr1 + wire width 64 \alu_branch0_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_branch0_spr2 + wire width 64 \alu_branch0_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 4 \alu_branch0_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -58190,10 +60526,10 @@ module \branch0 cell \alu_branch0 \alu_branch0 connect \rst \rst connect \clk \clk - connect \spr1_ok \spr1_ok - connect \spr1 \spr1 - connect \spr2_ok \spr2_ok - connect \spr2 \spr2 + connect \fast1_ok \fast1_ok + connect \fast1 \fast1 + connect \fast2_ok \fast2_ok + connect \fast2 \fast2 connect \nia_ok \nia_ok connect \nia \nia connect \n_valid_o \alu_branch0_n_valid_o @@ -58205,8 +60541,8 @@ module \branch0 connect \op__lk \alu_branch0_op__lk connect \op__is_32bit \alu_branch0_op__is_32bit connect \op__insn \alu_branch0_op__insn - connect \spr1$1 \alu_branch0_spr1 - connect \spr2$2 \alu_branch0_spr2 + connect \fast1$1 \alu_branch0_fast1 + connect \fast2$2 \alu_branch0_fast2 connect \cr_a \alu_branch0_cr_a connect \cia \alu_branch0_cia connect \p_valid_i \alu_branch0_p_valid_i @@ -58222,7 +60558,7 @@ module \branch0 wire width 4 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 4 \src_l_q_src - cell \src_l$22 \src_l + cell \src_l$23 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src @@ -58239,7 +60575,7 @@ module \branch0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$23 \opc_l + cell \opc_l$24 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc @@ -58252,7 +60588,7 @@ module \branch0 wire width 3 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 \req_l_r_req - cell \req_l$24 \req_l + cell \req_l$25 \req_l connect \rst \rst connect \clk \clk connect \q_req \req_l_q_req @@ -58263,7 +60599,7 @@ module \branch0 wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst - cell \rst_l$25 \rst_l + cell \rst_l$26 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst @@ -58277,7 +60613,7 @@ module \branch0 wire width 1 \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$26 \rok_l + cell \rok_l$27 \rok_l connect \rst \rst connect \clk \clk connect \q_rdok \rok_l_q_rdok @@ -58292,7 +60628,7 @@ module \branch0 wire width 1 \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$27 \alui_l + cell \alui_l$28 \alui_l connect \rst \rst connect \clk \clk connect \q_alui \alui_l_q_alui @@ -58307,7 +60643,7 @@ module \branch0 wire width 1 \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$28 \alu_l + cell \alu_l$29 \alu_l connect \rst \rst connect \clk \clk connect \q_alu \alu_l_q_alu @@ -59024,18 +61360,19 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 \oper_r__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 \oper_r__fn_unit + wire width 11 \oper_r__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 64 \oper_r__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -59051,9 +61388,9 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 7 \oper_l__insn_type$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 10 \oper_l__fn_unit + wire width 11 \oper_l__fn_unit attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 10 \oper_l__fn_unit$next + wire width 11 \oper_l__fn_unit$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \oper_l__imm_data__imm attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" @@ -59075,10 +61412,10 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 32 \oper_l__insn$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 116 $69 + wire width 117 $69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" cell $mux $70 - parameter \WIDTH 116 + parameter \WIDTH 117 connect \A { \oper_l__insn \oper_l__is_32bit \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } connect \B { \oper_i__insn \oper_i__is_32bit \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } connect \S \issue_i @@ -59086,7 +61423,7 @@ module \branch0 end process $group_25 assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 10'0000000000 + assign \oper_r__fn_unit 11'00000000000 assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \oper_r__imm_data__imm_ok 1'0 assign \oper_r__lk 1'0 @@ -59117,7 +61454,7 @@ module \branch0 end sync init update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 10'0000000000 + update \oper_l__fn_unit 11'00000000000 update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 update \oper_l__imm_data__imm_ok 1'0 update \oper_l__lk 1'0 @@ -59133,17 +61470,17 @@ module \branch0 update \oper_l__insn \oper_l__insn$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" - wire width 64 \data_r0__spr1 + wire width 64 \data_r0__fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" - wire width 1 \data_r0__spr1_ok + wire width 1 \data_r0__fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__spr1 + wire width 64 \data_r0_l__fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r0_l__spr1$next + wire width 64 \data_r0_l__fast1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__spr1_ok + wire width 1 \data_r0_l__fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r0_l__spr1_ok$next + wire width 1 \data_r0_l__fast1_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" wire width 65 $71 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" @@ -59159,15 +61496,15 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" cell $mux $74 parameter \WIDTH 65 - connect \A { \data_r0_l__spr1_ok \data_r0_l__spr1 } - connect \B { \spr1_ok \spr1 } + connect \A { \data_r0_l__fast1_ok \data_r0_l__fast1 } + connect \B { \fast1_ok \fast1 } connect \S $72 connect \Y $71 end process $group_39 - assign \data_r0__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r0__spr1_ok 1'0 - assign { \data_r0__spr1_ok \data_r0__spr1 } $71 + assign \data_r0__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r0__fast1_ok 1'0 + assign { \data_r0__fast1_ok \data_r0__fast1 } $71 sync init end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" @@ -59181,38 +61518,38 @@ module \branch0 connect \Y $75 end process $group_41 - assign \data_r0_l__spr1$next \data_r0_l__spr1 - assign \data_r0_l__spr1_ok$next \data_r0_l__spr1_ok + assign \data_r0_l__fast1$next \data_r0_l__fast1 + assign \data_r0_l__fast1_ok$next \data_r0_l__fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { $75 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \data_r0_l__spr1_ok$next \data_r0_l__spr1$next } { \spr1_ok \spr1 } + assign { \data_r0_l__fast1_ok$next \data_r0_l__fast1$next } { \fast1_ok \fast1 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \data_r0_l__spr1_ok$next 1'0 + assign \data_r0_l__fast1_ok$next 1'0 end sync init - update \data_r0_l__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0_l__spr1_ok 1'0 + update \data_r0_l__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r0_l__fast1_ok 1'0 sync posedge \clk - update \data_r0_l__spr1 \data_r0_l__spr1$next - update \data_r0_l__spr1_ok \data_r0_l__spr1_ok$next + update \data_r0_l__fast1 \data_r0_l__fast1$next + update \data_r0_l__fast1_ok \data_r0_l__fast1_ok$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" - wire width 64 \data_r1__spr2 + wire width 64 \data_r1__fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" - wire width 1 \data_r1__spr2_ok + wire width 1 \data_r1__fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r1_l__spr2 + wire width 64 \data_r1_l__fast2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r1_l__spr2$next + wire width 64 \data_r1_l__fast2$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__spr2_ok + wire width 1 \data_r1_l__fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__spr2_ok$next + wire width 1 \data_r1_l__fast2_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" wire width 65 $77 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" @@ -59228,15 +61565,15 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" cell $mux $80 parameter \WIDTH 65 - connect \A { \data_r1_l__spr2_ok \data_r1_l__spr2 } - connect \B { \spr2_ok \spr2 } + connect \A { \data_r1_l__fast2_ok \data_r1_l__fast2 } + connect \B { \fast2_ok \fast2 } connect \S $78 connect \Y $77 end process $group_43 - assign \data_r1__spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r1__spr2_ok 1'0 - assign { \data_r1__spr2_ok \data_r1__spr2 } $77 + assign \data_r1__fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r1__fast2_ok 1'0 + assign { \data_r1__fast2_ok \data_r1__fast2 } $77 sync init end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" @@ -59250,25 +61587,25 @@ module \branch0 connect \Y $81 end process $group_45 - assign \data_r1_l__spr2$next \data_r1_l__spr2 - assign \data_r1_l__spr2_ok$next \data_r1_l__spr2_ok + assign \data_r1_l__fast2$next \data_r1_l__fast2 + assign \data_r1_l__fast2_ok$next \data_r1_l__fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { $81 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \data_r1_l__spr2_ok$next \data_r1_l__spr2$next } { \spr2_ok \spr2 } + assign { \data_r1_l__fast2_ok$next \data_r1_l__fast2$next } { \fast2_ok \fast2 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \data_r1_l__spr2_ok$next 1'0 + assign \data_r1_l__fast2_ok$next 1'0 end sync init - update \data_r1_l__spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r1_l__spr2_ok 1'0 + update \data_r1_l__fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r1_l__fast2_ok 1'0 sync posedge \clk - update \data_r1_l__spr2 \data_r1_l__spr2$next - update \data_r1_l__spr2_ok \data_r1_l__spr2_ok$next + update \data_r1_l__fast2 \data_r1_l__fast2$next + update \data_r1_l__fast2_ok \data_r1_l__fast2_ok$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" wire width 64 \data_r2__nia @@ -59341,12 +61678,12 @@ module \branch0 end process $group_51 assign \wrmask 3'000 - assign \wrmask { \data_r2__nia_ok \data_r1__spr2_ok \data_r0__spr1_ok } + assign \wrmask { \data_r2__nia_ok \data_r1__fast2_ok \data_r0__fast1_ok } sync init end process $group_52 assign \alu_branch0_op__insn_type 7'0000000 - assign \alu_branch0_op__fn_unit 10'0000000000 + assign \alu_branch0_op__fn_unit 11'00000000000 assign \alu_branch0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \alu_branch0_op__imm_data__imm_ok 1'0 assign \alu_branch0_op__lk 1'0 @@ -59404,8 +61741,8 @@ module \branch0 connect \Y $93 end process $group_61 - assign \alu_branch0_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_branch0_spr1 $93 + assign \alu_branch0_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_branch0_fast1 $93 sync init end process $group_62 @@ -59436,8 +61773,8 @@ module \branch0 connect \Y $95 end process $group_63 - assign \alu_branch0_spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_branch0_spr2 $95 + assign \alu_branch0_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_branch0_fast2 $95 sync init end process $group_64 @@ -59734,7 +62071,7 @@ module \branch0 switch { \wr__go [0] } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 - assign \dest1_o { \data_r0__spr1_ok \data_r0__spr1 } [63:0] + assign \dest1_o { \data_r0__fast1_ok \data_r0__fast1 } [63:0] end sync init end @@ -59746,7 +62083,7 @@ module \branch0 switch { \wr__go [1] } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 - assign \dest2_o { \data_r1__spr2_ok \data_r1__spr2 } [63:0] + assign \dest2_o { \data_r1__fast2_ok \data_r1__fast2 } [63:0] end sync init end @@ -59765,7 +62102,7 @@ module \branch0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.p" -module \p$29 +module \p$30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -59793,7 +62130,7 @@ module \p$29 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.n" -module \n$30 +module \n$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -59821,7 +62158,7 @@ module \n$30 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.p" -module \p$32 +module \p$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -59849,7 +62186,7 @@ module \p$32 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.n" -module \n$33 +module \n$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -59877,7 +62214,7 @@ module \n$33 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.main" -module \main$34 +module \main$35 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -59955,24 +62292,25 @@ module \main$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 input 1 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 input 2 \op__fn_unit + wire width 11 input 2 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 input 3 \op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 input 4 \op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 input 5 \op__traptype + wire width 5 input 5 \op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 input 6 \op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -59980,9 +62318,9 @@ module \main$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 input 8 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 input 9 \spr1 + wire width 64 input 9 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 input 10 \spr2 + wire width 64 input 10 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 input 11 \cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -60064,24 +62402,25 @@ module \main$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 output 14 \op__insn_type$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 output 15 \op__fn_unit$3 + wire width 11 output 15 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 output 16 \op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 output 17 \op__is_32bit$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 output 18 \op__traptype$6 + wire width 5 output 18 \op__traptype$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 output 19 \op__trapaddr$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -60089,13 +62428,13 @@ module \main$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 21 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 22 \spr1$8 + wire width 64 output 22 \fast1$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 23 \spr1_ok + wire width 1 output 23 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 24 \spr2$9 + wire width 64 output 24 \fast2$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 25 \spr2_ok + wire width 1 output 25 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 output 26 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -60104,44 +62443,44 @@ module \main$34 wire width 64 output 28 \msr$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 29 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:125" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:101" wire width 5 \to process $group_0 assign \to 5'00000 assign \to { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:129" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:105" wire width 64 \a_s process $group_1 assign \a_s 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112" switch { \op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112" case 1'1 assign \a_s { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:117" case assign \a_s \ra end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:130" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:106" wire width 64 \b_s process $group_2 assign \b_s 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112" switch { \op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112" case 1'1 assign \b_s { { \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] } \rb [31:0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:117" case assign \b_s \rb end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:108" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251" wire width 64 $11 @@ -60155,18 +62494,18 @@ module \main$34 end process $group_3 assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112" switch { \op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112" case 1'1 assign \a $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:117" case assign \a \ra end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:133" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:109" wire width 64 \b attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251" wire width 64 $13 @@ -60180,22 +62519,22 @@ module \main$34 end process $group_4 assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112" switch { \op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:136" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112" case 1'1 assign \b $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:117" case assign \b \rb end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:148" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:124" wire width 1 \lt_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:130" wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:130" cell $lt $16 parameter \A_SIGNED 1 parameter \A_WIDTH 64 @@ -60211,11 +62550,11 @@ module \main$34 assign \lt_s $15 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:125" wire width 1 \gt_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:155" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:131" wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:155" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:131" cell $gt $18 parameter \A_SIGNED 1 parameter \A_WIDTH 64 @@ -60231,11 +62570,11 @@ module \main$34 assign \gt_s $17 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:126" wire width 1 \lt_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132" wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:156" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132" cell $lt $20 parameter \A_SIGNED 0 parameter \A_WIDTH 64 @@ -60251,11 +62590,11 @@ module \main$34 assign \lt_u $19 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:127" wire width 1 \gt_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:133" wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:133" cell $gt $22 parameter \A_SIGNED 0 parameter \A_WIDTH 64 @@ -60271,11 +62610,11 @@ module \main$34 assign \gt_u $21 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:128" wire width 1 \equal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:134" wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:134" cell $eq $24 parameter \A_SIGNED 0 parameter \A_WIDTH 64 @@ -60291,20 +62630,20 @@ module \main$34 assign \equal $23 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138" wire width 5 \trap_bits process $group_10 assign \trap_bits 5'00000 assign \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:143" wire width 1 \should_trap - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" wire width 5 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" cell $and $27 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -60315,7 +62654,7 @@ module \main$34 connect \B \to connect \Y $26 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" cell $reduce_or $28 parameter \A_SIGNED 0 parameter \A_WIDTH 5 @@ -60323,19 +62662,19 @@ module \main$34 connect \A $26 connect \Y $25 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" cell $reduce_or $30 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \op__traptype connect \Y $29 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:168" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" cell $or $32 parameter \A_SIGNED 0 parameter \A_WIDTH 1 @@ -60351,11 +62690,11 @@ module \main$34 assign \should_trap $31 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" wire width 64 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" wire width 20 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" cell $sshl $35 parameter \A_SIGNED 0 parameter \A_WIDTH 13 @@ -60366,7 +62705,7 @@ module \main$34 connect \B 3'100 connect \Y $34 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153" cell $pos $36 parameter \A_SIGNED 0 parameter \A_WIDTH 20 @@ -60376,383 +62715,467 @@ module \main$34 end process $group_12 assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147" switch \op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" attribute \nmigen.decoding "OP_TRAP/63" case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151" switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151" case 1'1 assign \nia $33 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" attribute \nmigen.decoding "OP_MTMSRD/72" case 7'1001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 - assign \nia { { { } \spr1 [63:2] } 2'00 } + assign \nia { { { } \fast1 [63:2] } 2'00 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 + assign \nia 64'0000000000000000000000000000000000000000000000000000110000000000 end sync init end process $group_13 assign \nia_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147" switch \op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" attribute \nmigen.decoding "OP_TRAP/63" case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151" switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151" case 1'1 assign \nia_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" attribute \nmigen.decoding "OP_MTMSRD/72" case 7'1001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 assign \nia_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 + assign \nia_ok 1'1 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205" + wire width 65 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205" + wire width 65 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205" + cell $add $39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \cia + connect \B 3'100 + connect \Y $38 + end + connect $37 $38 process $group_14 - assign \spr1$8 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" + assign \fast1$8 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147" switch \op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" attribute \nmigen.decoding "OP_TRAP/63" case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151" switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151" case 1'1 - assign \spr1$8 \cia + assign \fast1$8 \cia end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" attribute \nmigen.decoding "OP_MTMSRD/72" case 7'1001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 + assign \fast1$8 $37 [63:0] end sync init end process $group_15 - assign \spr1_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" + assign \fast1_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147" switch \op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" attribute \nmigen.decoding "OP_TRAP/63" case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151" switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151" case 1'1 - assign \spr1_ok 1'1 + assign \fast1_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" attribute \nmigen.decoding "OP_MTMSRD/72" case 7'1001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 + assign \fast1_ok 1'1 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:178" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:178" - cell $eq $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154" + wire width 1 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154" + cell $eq $41 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \op__traptype connect \B 1'0 - connect \Y $37 + connect \Y $40 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181" - wire width 4 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181" - cell $and $41 + wire width 1 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" + wire width 5 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" + cell $and $44 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 2 - parameter \Y_WIDTH 4 + parameter \Y_WIDTH 5 connect \A \op__traptype connect \B 2'10 - connect \Y $40 + connect \Y $43 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $42 + cell $reduce_bool $45 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \Y_WIDTH 1 - connect \A $40 - connect \Y $39 + connect \A $43 + connect \Y $42 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183" - wire width 4 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183" - cell $and $45 + wire width 1 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" + wire width 5 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" + cell $and $48 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 + parameter \Y_WIDTH 5 connect \A \op__traptype connect \B 1'1 - connect \Y $44 + connect \Y $47 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $46 + cell $reduce_bool $49 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \Y_WIDTH 1 - connect \A $44 - connect \Y $43 + connect \A $47 + connect \Y $46 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" - wire width 4 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" - cell $and $49 + wire width 1 $50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161" + wire width 5 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161" + cell $and $52 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 + parameter \Y_WIDTH 5 connect \A \op__traptype connect \B 4'1000 - connect \Y $48 + connect \Y $51 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $50 + cell $reduce_bool $53 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \Y_WIDTH 1 - connect \A $48 - connect \Y $47 + connect \A $51 + connect \Y $50 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" + wire width 5 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" + cell $and $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \op__traptype + connect \B 5'10000 + connect \Y $55 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A $55 + connect \Y $54 end process $group_16 - assign \spr2$9 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" + assign \fast2$9 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147" switch \op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" attribute \nmigen.decoding "OP_TRAP/63" case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151" switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" - case 1'1 - assign \spr2$9 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr2$9 [15:0] \msr [15:0] - assign \spr2$9 [26:22] \msr [26:22] - assign \spr2$9 [63:31] \msr [63:31] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:178" - switch { $37 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:178" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151" + case 1'1 + assign \fast2$9 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast2$9 [15:0] \msr [15:0] + assign \fast2$9 [26:22] \msr [26:22] + assign \fast2$9 [63:31] \msr [63:31] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154" + switch { $40 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154" + case 1'1 + assign \fast2$9 [17] 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" + switch { $42 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" case 1'1 - assign \spr2$9 [17] 1'1 + assign \fast2$9 [18] 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181" - switch { $39 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" + switch { $46 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" case 1'1 - assign \spr2$9 [18] 1'1 + assign \fast2$9 [20] 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183" - switch { $43 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161" + switch { $50 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161" case 1'1 - assign \spr2$9 [20] 1'1 + assign \fast2$9 [16] 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" - switch { $47 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:185" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" + switch { $54 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" case 1'1 - assign \spr2$9 [16] 1'1 + assign \fast2$9 [19] 1'1 end end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" attribute \nmigen.decoding "OP_MTMSRD/72" case 7'1001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 + assign \fast2$9 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast2$9 [15:0] \msr [15:0] + assign \fast2$9 [26:22] \msr [26:22] + assign \fast2$9 [63:31] \msr [63:31] end sync init end process $group_17 - assign \spr2_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" + assign \fast2_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147" switch \op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" attribute \nmigen.decoding "OP_TRAP/63" case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151" switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151" case 1'1 - assign \spr2_ok 1'1 + assign \fast2_ok 1'1 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" attribute \nmigen.decoding "OP_MTMSRD/72" case 7'1001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 + assign \fast2_ok 1'1 end sync init end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $51 + wire width 1 $58 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $52 + cell $reduce_bool $59 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \op__insn [22] \op__insn [21] } - connect \Y $51 + connect \Y $58 end process $group_18 assign \msr$10 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147" switch \op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" attribute \nmigen.decoding "OP_TRAP/63" case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" attribute \nmigen.decoding "OP_MTMSRD/72" case 7'1001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191" - switch { $51 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169" + switch { $58 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169" case 1'1 assign \msr$10 [15] \ra [15] assign \msr$10 [1] \ra [1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" case assign \msr$10 [11:1] \ra [11:1] assign \msr$10 [59:13] \ra [59:13] assign \msr$10 [63:61] \ra [63:61] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:75" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:50" switch { \msr$10 [14] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:75" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:50" case 1'1 assign \msr$10 [15] 1'1 assign \msr$10 [5] 1'1 assign \msr$10 [4] 1'1 end end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 - assign \msr$10 [15:0] \spr2 [15:0] - assign \msr$10 [26:22] \spr2 [26:22] - assign \msr$10 [63:31] \spr2 [63:31] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:75" + assign \msr$10 [15:0] \fast2 [15:0] + assign \msr$10 [26:22] \fast2 [26:22] + assign \msr$10 [63:31] \fast2 [63:31] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:50" switch { \msr$10 [14] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:75" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:50" case 1'1 assign \msr$10 [15] 1'1 assign \msr$10 [5] 1'1 assign \msr$10 [4] 1'1 end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 end sync init end process $group_19 assign \msr_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147" switch \op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" attribute \nmigen.decoding "OP_TRAP/63" case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" attribute \nmigen.decoding "OP_MTMSRD/72" case 7'1001000 assign \msr_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 assign \msr_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 end sync init end process $group_20 assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147" switch \op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" attribute \nmigen.decoding "OP_TRAP/63" case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" attribute \nmigen.decoding "OP_MTMSRD/72" case 7'1001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 assign \o \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 end sync init end process $group_21 assign \o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147" switch \op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" attribute \nmigen.decoding "OP_TRAP/63" case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" attribute \nmigen.decoding "OP_MTMSRD/72" case 7'1001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182" attribute \nmigen.decoding "OP_MFMSR/71" case 7'1000111 assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:209" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" attribute \nmigen.decoding "OP_RFID/70" case 7'1000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200" + attribute \nmigen.decoding "OP_SC/73" + case 7'1001001 end sync init end @@ -60763,10 +63186,10 @@ module \main$34 end process $group_23 assign \op__insn_type$2 7'0000000 - assign \op__fn_unit$3 10'0000000000 + assign \op__fn_unit$3 11'00000000000 assign \op__insn$4 32'00000000000000000000000000000000 assign \op__is_32bit$5 1'0 - assign \op__traptype$6 4'0000 + assign \op__traptype$6 5'00000 assign \op__trapaddr$7 13'0000000000000 assign { \op__trapaddr$7 \op__traptype$6 \op__is_32bit$5 \op__insn$4 \op__fn_unit$3 \op__insn_type$2 } { \op__trapaddr \op__traptype \op__is_32bit \op__insn \op__fn_unit \op__insn_type } sync init @@ -60774,7 +63197,7 @@ module \main$34 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe" -module \pipe$31 +module \pipe$32 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -60860,24 +63283,25 @@ module \pipe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 input 5 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 input 6 \op__fn_unit + wire width 11 input 6 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 input 7 \op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 input 8 \op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 input 9 \op__traptype + wire width 5 input 9 \op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 input 10 \op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -60885,9 +63309,9 @@ module \pipe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 input 12 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 input 13 \spr1 + wire width 64 input 13 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 input 14 \spr2 + wire width 64 input 14 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 input 15 \cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -60977,20 +63401,21 @@ module \pipe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 \op__insn_type$2$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 output 21 \op__fn_unit$3 + wire width 11 output 21 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 \op__fn_unit$3$next + wire width 11 \op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 output 22 \op__insn$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" @@ -61000,9 +63425,9 @@ module \pipe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 \op__is_32bit$5$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 output 24 \op__traptype$6 + wire width 5 output 24 \op__traptype$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 \op__traptype$6$next + wire width 5 \op__traptype$6$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 output 25 \op__trapaddr$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" @@ -61016,21 +63441,21 @@ module \pipe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \o_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 28 \spr1$8 + wire width 64 output 28 \fast1$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \spr1$8$next + wire width 64 \fast1$8$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 29 \spr1_ok + wire width 1 output 29 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \spr1_ok$next + wire width 1 \fast1_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 30 \spr2$9 + wire width 64 output 30 \fast2$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \spr2$9$next + wire width 64 \fast2$9$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 31 \spr2_ok + wire width 1 output 31 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \spr2_ok$next + wire width 1 \fast2_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 output 32 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -61047,11 +63472,11 @@ module \pipe$31 wire width 1 output 35 \msr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \msr_ok$next - cell \p$32 \p + cell \p$33 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$33 \n + cell \n$34 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -61132,24 +63557,25 @@ module \pipe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 \main_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 \main_op__fn_unit + wire width 11 \main_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 \main_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 \main_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 \main_op__traptype + wire width 5 \main_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 \main_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -61157,9 +63583,9 @@ module \pipe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 \main_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \main_spr1 + wire width 64 \main_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \main_spr2 + wire width 64 \main_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 \main_cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -61241,24 +63667,25 @@ module \pipe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 \main_op__insn_type$12 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 \main_op__fn_unit$13 + wire width 11 \main_op__fn_unit$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 \main_op__insn$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 \main_op__is_32bit$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 \main_op__traptype$16 + wire width 5 \main_op__traptype$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 \main_op__trapaddr$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -61266,13 +63693,13 @@ module \pipe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \main_spr1$18 + wire width 64 \main_fast1$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \main_spr1_ok + wire width 1 \main_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \main_spr2$19 + wire width 64 \main_fast2$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \main_spr2_ok + wire width 1 \main_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 \main_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -61281,7 +63708,7 @@ module \pipe$31 wire width 64 \main_msr$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \main_msr_ok - cell \main$34 \main + cell \main$35 \main connect \muxid \main_muxid connect \op__insn_type \main_op__insn_type connect \op__fn_unit \main_op__fn_unit @@ -61291,8 +63718,8 @@ module \pipe$31 connect \op__trapaddr \main_op__trapaddr connect \ra \main_ra connect \rb \main_rb - connect \spr1 \main_spr1 - connect \spr2 \main_spr2 + connect \fast1 \main_fast1 + connect \fast2 \main_fast2 connect \cia \main_cia connect \msr \main_msr connect \muxid$1 \main_muxid$11 @@ -61304,10 +63731,10 @@ module \pipe$31 connect \op__trapaddr$7 \main_op__trapaddr$17 connect \o \main_o connect \o_ok \main_o_ok - connect \spr1$8 \main_spr1$18 - connect \spr1_ok \main_spr1_ok - connect \spr2$9 \main_spr2$19 - connect \spr2_ok \main_spr2_ok + connect \fast1$8 \main_fast1$18 + connect \fast1_ok \main_fast1_ok + connect \fast2$9 \main_fast2$19 + connect \fast2_ok \main_fast2_ok connect \nia \main_nia connect \nia_ok \main_nia_ok connect \msr$10 \main_msr$20 @@ -61320,10 +63747,10 @@ module \pipe$31 end process $group_1 assign \main_op__insn_type 7'0000000 - assign \main_op__fn_unit 10'0000000000 + assign \main_op__fn_unit 11'00000000000 assign \main_op__insn 32'00000000000000000000000000000000 assign \main_op__is_32bit 1'0 - assign \main_op__traptype 4'0000 + assign \main_op__traptype 5'00000 assign \main_op__trapaddr 13'0000000000000 assign { \main_op__trapaddr \main_op__traptype \main_op__is_32bit \main_op__insn \main_op__fn_unit \main_op__insn_type } { \op__trapaddr \op__traptype \op__is_32bit \op__insn \op__fn_unit \op__insn_type } sync init @@ -61339,13 +63766,13 @@ module \pipe$31 sync init end process $group_9 - assign \main_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_spr1 \spr1 + assign \main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_fast1 \fast1 sync init end process $group_10 - assign \main_spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_spr2 \spr2 + assign \main_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \main_fast2 \fast2 sync init end process $group_11 @@ -61474,32 +63901,33 @@ module \pipe$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 \op__insn_type$25 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 \op__fn_unit$26 + wire width 11 \op__fn_unit$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 \op__insn$27 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 \op__is_32bit$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 \op__traptype$29 + wire width 5 \op__traptype$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 \op__trapaddr$30 process $group_17 assign \op__insn_type$25 7'0000000 - assign \op__fn_unit$26 10'0000000000 + assign \op__fn_unit$26 11'00000000000 assign \op__insn$27 32'00000000000000000000000000000000 assign \op__is_32bit$28 1'0 - assign \op__traptype$29 4'0000 + assign \op__traptype$29 5'00000 assign \op__trapaddr$30 13'0000000000000 assign { \op__trapaddr$30 \op__traptype$29 \op__is_32bit$28 \op__insn$27 \op__fn_unit$26 \op__insn_type$25 } { \main_op__trapaddr$17 \main_op__traptype$16 \main_op__is_32bit$15 \main_op__insn$14 \main_op__fn_unit$13 \main_op__insn_type$12 } sync init @@ -61515,23 +63943,23 @@ module \pipe$31 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \spr1$33 + wire width 64 \fast1$33 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \spr1_ok$34 + wire width 1 \fast1_ok$34 process $group_25 - assign \spr1$33 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr1_ok$34 1'0 - assign { \spr1_ok$34 \spr1$33 } { \main_spr1_ok \main_spr1$18 } + assign \fast1$33 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast1_ok$34 1'0 + assign { \fast1_ok$34 \fast1$33 } { \main_fast1_ok \main_fast1$18 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \spr2$35 + wire width 64 \fast2$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \spr2_ok$36 + wire width 1 \fast2_ok$36 process $group_27 - assign \spr2$35 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr2_ok$36 1'0 - assign { \spr2_ok$36 \spr2$35 } { \main_spr2_ok \main_spr2$19 } + assign \fast2$35 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast2_ok$36 1'0 + assign { \fast2_ok$36 \fast2$35 } { \main_fast2_ok \main_fast2$19 } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -61613,10 +64041,10 @@ module \pipe$31 end sync init update \op__insn_type$2 7'0000000 - update \op__fn_unit$3 10'0000000000 + update \op__fn_unit$3 11'00000000000 update \op__insn$4 32'00000000000000000000000000000000 update \op__is_32bit$5 1'0 - update \op__traptype$6 4'0000 + update \op__traptype$6 5'00000 update \op__trapaddr$7 13'0000000000000 sync posedge \clk update \op__insn_type$2 \op__insn_type$2$next @@ -61651,52 +64079,52 @@ module \pipe$31 update \o_ok \o_ok$next end process $group_43 - assign \spr1$8$next \spr1$8 - assign \spr1_ok$next \spr1_ok + assign \fast1$8$next \fast1$8 + assign \fast1_ok$next \fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \spr1_ok$next \spr1$8$next } { \spr1_ok$34 \spr1$33 } + assign { \fast1_ok$next \fast1$8$next } { \fast1_ok$34 \fast1$33 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \spr1_ok$next \spr1$8$next } { \spr1_ok$34 \spr1$33 } + assign { \fast1_ok$next \fast1$8$next } { \fast1_ok$34 \fast1$33 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \spr1_ok$next 1'0 + assign \fast1_ok$next 1'0 end sync init - update \spr1$8 64'0000000000000000000000000000000000000000000000000000000000000000 - update \spr1_ok 1'0 + update \fast1$8 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast1_ok 1'0 sync posedge \clk - update \spr1$8 \spr1$8$next - update \spr1_ok \spr1_ok$next + update \fast1$8 \fast1$8$next + update \fast1_ok \fast1_ok$next end process $group_45 - assign \spr2$9$next \spr2$9 - assign \spr2_ok$next \spr2_ok + assign \fast2$9$next \fast2$9 + assign \fast2_ok$next \fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" switch { \n_i_rdy_data \p_valid_i_p_ready_o } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" case 2'-1 - assign { \spr2_ok$next \spr2$9$next } { \spr2_ok$36 \spr2$35 } + assign { \fast2_ok$next \fast2$9$next } { \fast2_ok$36 \fast2$35 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" case 2'1- - assign { \spr2_ok$next \spr2$9$next } { \spr2_ok$36 \spr2$35 } + assign { \fast2_ok$next \fast2$9$next } { \fast2_ok$36 \fast2$35 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \spr2_ok$next 1'0 + assign \fast2_ok$next 1'0 end sync init - update \spr2$9 64'0000000000000000000000000000000000000000000000000000000000000000 - update \spr2_ok 1'0 + update \fast2$9 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast2_ok 1'0 sync posedge \clk - update \spr2$9 \spr2$9$next - update \spr2_ok \spr2_ok$next + update \fast2$9 \fast2$9$next + update \fast2_ok \fast2_ok$next end process $group_47 assign \nia$next \nia @@ -61769,13 +64197,13 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 output 3 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 4 \spr1_ok + wire width 1 output 4 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 5 \spr1 + wire width 64 output 5 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 6 \spr2_ok + wire width 1 output 6 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 7 \spr2 + wire width 64 output 7 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 8 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -61863,24 +64291,25 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 input 14 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 input 15 \op__fn_unit + wire width 11 input 15 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 input 16 \op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 input 17 \op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 input 18 \op__traptype + wire width 5 input 18 \op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 input 19 \op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -61888,9 +64317,9 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 input 21 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 input 22 \spr1$1 + wire width 64 input 22 \fast1$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 input 23 \spr2$2 + wire width 64 input 23 \fast2$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 input 24 \cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -61899,11 +64328,11 @@ module \alu_trap0 wire width 1 input 26 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 output 27 \p_ready_o - cell \p$29 \p + cell \p$30 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$30 \n + cell \n$31 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -61988,24 +64417,25 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 \pipe_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 \pipe_op__fn_unit + wire width 11 \pipe_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 \pipe_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 \pipe_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 \pipe_op__traptype + wire width 5 \pipe_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 \pipe_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -62013,9 +64443,9 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 \pipe_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \pipe_spr1 + wire width 64 \pipe_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \pipe_spr2 + wire width 64 \pipe_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 \pipe_cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -62101,24 +64531,25 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 \pipe_op__insn_type$5 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 \pipe_op__fn_unit$6 + wire width 11 \pipe_op__fn_unit$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 \pipe_op__insn$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 \pipe_op__is_32bit$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 \pipe_op__traptype$9 + wire width 5 \pipe_op__traptype$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 \pipe_op__trapaddr$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -62126,13 +64557,13 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \pipe_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \pipe_spr1$11 + wire width 64 \pipe_fast1$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \pipe_spr1_ok + wire width 1 \pipe_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \pipe_spr2$12 + wire width 64 \pipe_fast2$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \pipe_spr2_ok + wire width 1 \pipe_fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 \pipe_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -62141,7 +64572,7 @@ module \alu_trap0 wire width 64 \pipe_msr$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \pipe_msr_ok - cell \pipe$31 \pipe + cell \pipe$32 \pipe connect \rst \rst connect \clk \clk connect \p_valid_i \pipe_p_valid_i @@ -62155,8 +64586,8 @@ module \alu_trap0 connect \op__trapaddr \pipe_op__trapaddr connect \ra \pipe_ra connect \rb \pipe_rb - connect \spr1 \pipe_spr1 - connect \spr2 \pipe_spr2 + connect \fast1 \pipe_fast1 + connect \fast2 \pipe_fast2 connect \cia \pipe_cia connect \msr \pipe_msr connect \n_valid_o \pipe_n_valid_o @@ -62170,10 +64601,10 @@ module \alu_trap0 connect \op__trapaddr$7 \pipe_op__trapaddr$10 connect \o \pipe_o connect \o_ok \pipe_o_ok - connect \spr1$8 \pipe_spr1$11 - connect \spr1_ok \pipe_spr1_ok - connect \spr2$9 \pipe_spr2$12 - connect \spr2_ok \pipe_spr2_ok + connect \fast1$8 \pipe_fast1$11 + connect \fast1_ok \pipe_fast1_ok + connect \fast2$9 \pipe_fast2$12 + connect \fast2_ok \pipe_fast2_ok connect \nia \pipe_nia connect \nia_ok \pipe_nia_ok connect \msr$10 \pipe_msr$13 @@ -62198,10 +64629,10 @@ module \alu_trap0 end process $group_3 assign \pipe_op__insn_type 7'0000000 - assign \pipe_op__fn_unit 10'0000000000 + assign \pipe_op__fn_unit 11'00000000000 assign \pipe_op__insn 32'00000000000000000000000000000000 assign \pipe_op__is_32bit 1'0 - assign \pipe_op__traptype 4'0000 + assign \pipe_op__traptype 5'00000 assign \pipe_op__trapaddr 13'0000000000000 assign { \pipe_op__trapaddr \pipe_op__traptype \pipe_op__is_32bit \pipe_op__insn \pipe_op__fn_unit \pipe_op__insn_type } { \op__trapaddr \op__traptype \op__is_32bit \op__insn \op__fn_unit \op__insn_type } sync init @@ -62217,13 +64648,13 @@ module \alu_trap0 sync init end process $group_11 - assign \pipe_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_spr1 \spr1$1 + assign \pipe_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_fast1 \fast1$1 sync init end process $group_12 - assign \pipe_spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_spr2 \spr2$2 + assign \pipe_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_fast2 \fast2$2 sync init end process $group_13 @@ -62328,32 +64759,33 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 \op__insn_type$15 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 \op__fn_unit$16 + wire width 11 \op__fn_unit$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 \op__insn$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 \op__is_32bit$18 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 \op__traptype$19 + wire width 5 \op__traptype$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 \op__trapaddr$20 process $group_18 assign \op__insn_type$15 7'0000000 - assign \op__fn_unit$16 10'0000000000 + assign \op__fn_unit$16 11'00000000000 assign \op__insn$17 32'00000000000000000000000000000000 assign \op__is_32bit$18 1'0 - assign \op__traptype$19 4'0000 + assign \op__traptype$19 5'00000 assign \op__trapaddr$20 13'0000000000000 assign { \op__trapaddr$20 \op__traptype$19 \op__is_32bit$18 \op__insn$17 \op__fn_unit$16 \op__insn_type$15 } { \pipe_op__trapaddr$10 \pipe_op__traptype$9 \pipe_op__is_32bit$8 \pipe_op__insn$7 \pipe_op__fn_unit$6 \pipe_op__insn_type$5 } sync init @@ -62365,15 +64797,15 @@ module \alu_trap0 sync init end process $group_26 - assign \spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr1_ok 1'0 - assign { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } + assign \fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast1_ok 1'0 + assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$11 } sync init end process $group_28 - assign \spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr2_ok 1'0 - assign { \spr2_ok \spr2 } { \pipe_spr2_ok \pipe_spr2$12 } + assign \fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast2_ok 1'0 + assign { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$12 } sync init end process $group_30 @@ -62392,7 +64824,7 @@ module \alu_trap0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.src_l" -module \src_l$35 +module \src_l$36 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -62537,7 +64969,7 @@ module \src_l$35 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.opc_l" -module \opc_l$36 +module \opc_l$37 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -62682,7 +65114,7 @@ module \opc_l$36 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.req_l" -module \req_l$37 +module \req_l$38 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -62827,7 +65259,7 @@ module \req_l$37 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rst_l" -module \rst_l$38 +module \rst_l$39 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -62972,7 +65404,7 @@ module \rst_l$38 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rok_l" -module \rok_l$39 +module \rok_l$40 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -63117,7 +65549,7 @@ module \rok_l$39 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alui_l" -module \alui_l$40 +module \alui_l$41 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -63262,7 +65694,7 @@ module \alui_l$40 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_l" -module \alu_l$41 +module \alu_l$42 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -63487,24 +65919,25 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 input 2 \oper_i__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 input 3 \oper_i__fn_unit + wire width 11 input 3 \oper_i__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 input 4 \oper_i__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 input 5 \oper_i__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 input 6 \oper_i__traptype + wire width 5 input 6 \oper_i__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 input 7 \oper_i__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" @@ -63538,13 +65971,13 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 output 22 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 23 \spr1_ok + wire width 1 output 23 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 24 \spr1 + wire width 64 output 24 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 25 \spr2_ok + wire width 1 output 25 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 26 \spr2 + wire width 64 output 26 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 27 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -63638,24 +66071,25 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 \alu_trap0_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 \alu_trap0_op__fn_unit + wire width 11 \alu_trap0_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 \alu_trap0_op__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 \alu_trap0_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 \alu_trap0_op__traptype + wire width 5 \alu_trap0_op__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 \alu_trap0_op__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -63663,9 +66097,9 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 \alu_trap0_rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_trap0_spr1 + wire width 64 \alu_trap0_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_trap0_spr2 + wire width 64 \alu_trap0_fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 \alu_trap0_cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" @@ -63679,10 +66113,10 @@ module \trap0 connect \clk \clk connect \o_ok \o_ok connect \o \o - connect \spr1_ok \spr1_ok - connect \spr1 \spr1 - connect \spr2_ok \spr2_ok - connect \spr2 \spr2 + connect \fast1_ok \fast1_ok + connect \fast1 \fast1 + connect \fast2_ok \fast2_ok + connect \fast2 \fast2 connect \nia_ok \nia_ok connect \nia \nia connect \msr_ok \msr_ok @@ -63697,8 +66131,8 @@ module \trap0 connect \op__trapaddr \alu_trap0_op__trapaddr connect \ra \alu_trap0_ra connect \rb \alu_trap0_rb - connect \spr1$1 \alu_trap0_spr1 - connect \spr2$2 \alu_trap0_spr2 + connect \fast1$1 \alu_trap0_fast1 + connect \fast2$2 \alu_trap0_fast2 connect \cia \alu_trap0_cia connect \msr$3 \alu_trap0_msr connect \p_valid_i \alu_trap0_p_valid_i @@ -63714,7 +66148,7 @@ module \trap0 wire width 6 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 6 \src_l_q_src - cell \src_l$35 \src_l + cell \src_l$36 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src @@ -63731,7 +66165,7 @@ module \trap0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$36 \opc_l + cell \opc_l$37 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc @@ -63744,7 +66178,7 @@ module \trap0 wire width 5 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 5 \req_l_r_req - cell \req_l$37 \req_l + cell \req_l$38 \req_l connect \rst \rst connect \clk \clk connect \q_req \req_l_q_req @@ -63755,7 +66189,7 @@ module \trap0 wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst - cell \rst_l$38 \rst_l + cell \rst_l$39 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst @@ -63769,7 +66203,7 @@ module \trap0 wire width 1 \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$39 \rok_l + cell \rok_l$40 \rok_l connect \rst \rst connect \clk \clk connect \q_rdok \rok_l_q_rdok @@ -63784,7 +66218,7 @@ module \trap0 wire width 1 \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$40 \alui_l + cell \alui_l$41 \alui_l connect \rst \rst connect \clk \clk connect \q_alui \alui_l_q_alui @@ -63799,7 +66233,7 @@ module \trap0 wire width 1 \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$41 \alu_l + cell \alu_l$42 \alu_l connect \rst \rst connect \clk \clk connect \q_alu \alu_l_q_alu @@ -64516,24 +66950,25 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 7 \oper_r__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 \oper_r__fn_unit + wire width 11 \oper_r__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 \oper_r__insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 \oper_r__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 \oper_r__traptype + wire width 5 \oper_r__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 \oper_r__trapaddr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" @@ -64541,9 +66976,9 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 7 \oper_l__insn_type$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 10 \oper_l__fn_unit + wire width 11 \oper_l__fn_unit attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 10 \oper_l__fn_unit$next + wire width 11 \oper_l__fn_unit$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 32 \oper_l__insn attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" @@ -64553,18 +66988,18 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \oper_l__is_32bit$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \oper_l__traptype + wire width 5 \oper_l__traptype attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \oper_l__traptype$next + wire width 5 \oper_l__traptype$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 13 \oper_l__trapaddr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 13 \oper_l__trapaddr$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 67 $69 + wire width 69 $69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" cell $mux $70 - parameter \WIDTH 67 + parameter \WIDTH 69 connect \A { \oper_l__trapaddr \oper_l__traptype \oper_l__is_32bit \oper_l__insn \oper_l__fn_unit \oper_l__insn_type } connect \B { \oper_i__trapaddr \oper_i__traptype \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type } connect \S \issue_i @@ -64572,10 +67007,10 @@ module \trap0 end process $group_25 assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 10'0000000000 + assign \oper_r__fn_unit 11'00000000000 assign \oper_r__insn 32'00000000000000000000000000000000 assign \oper_r__is_32bit 1'0 - assign \oper_r__traptype 4'0000 + assign \oper_r__traptype 5'00000 assign \oper_r__trapaddr 13'0000000000000 assign { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } $69 sync init @@ -64595,10 +67030,10 @@ module \trap0 end sync init update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 10'0000000000 + update \oper_l__fn_unit 11'00000000000 update \oper_l__insn 32'00000000000000000000000000000000 update \oper_l__is_32bit 1'0 - update \oper_l__traptype 4'0000 + update \oper_l__traptype 5'00000 update \oper_l__trapaddr 13'0000000000000 sync posedge \clk update \oper_l__insn_type \oper_l__insn_type$next @@ -64678,17 +67113,17 @@ module \trap0 update \data_r0_l__o_ok \data_r0_l__o_ok$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" - wire width 64 \data_r1__spr1 + wire width 64 \data_r1__fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" - wire width 1 \data_r1__spr1_ok + wire width 1 \data_r1__fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r1_l__spr1 + wire width 64 \data_r1_l__fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r1_l__spr1$next + wire width 64 \data_r1_l__fast1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__spr1_ok + wire width 1 \data_r1_l__fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__spr1_ok$next + wire width 1 \data_r1_l__fast1_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" wire width 65 $77 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" @@ -64704,15 +67139,15 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" cell $mux $80 parameter \WIDTH 65 - connect \A { \data_r1_l__spr1_ok \data_r1_l__spr1 } - connect \B { \spr1_ok \spr1 } + connect \A { \data_r1_l__fast1_ok \data_r1_l__fast1 } + connect \B { \fast1_ok \fast1 } connect \S $78 connect \Y $77 end process $group_41 - assign \data_r1__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r1__spr1_ok 1'0 - assign { \data_r1__spr1_ok \data_r1__spr1 } $77 + assign \data_r1__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r1__fast1_ok 1'0 + assign { \data_r1__fast1_ok \data_r1__fast1 } $77 sync init end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" @@ -64726,38 +67161,38 @@ module \trap0 connect \Y $81 end process $group_43 - assign \data_r1_l__spr1$next \data_r1_l__spr1 - assign \data_r1_l__spr1_ok$next \data_r1_l__spr1_ok + assign \data_r1_l__fast1$next \data_r1_l__fast1 + assign \data_r1_l__fast1_ok$next \data_r1_l__fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { $81 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \data_r1_l__spr1_ok$next \data_r1_l__spr1$next } { \spr1_ok \spr1 } + assign { \data_r1_l__fast1_ok$next \data_r1_l__fast1$next } { \fast1_ok \fast1 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \data_r1_l__spr1_ok$next 1'0 + assign \data_r1_l__fast1_ok$next 1'0 end sync init - update \data_r1_l__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r1_l__spr1_ok 1'0 + update \data_r1_l__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r1_l__fast1_ok 1'0 sync posedge \clk - update \data_r1_l__spr1 \data_r1_l__spr1$next - update \data_r1_l__spr1_ok \data_r1_l__spr1_ok$next + update \data_r1_l__fast1 \data_r1_l__fast1$next + update \data_r1_l__fast1_ok \data_r1_l__fast1_ok$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" - wire width 64 \data_r2__spr2 + wire width 64 \data_r2__fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" - wire width 1 \data_r2__spr2_ok + wire width 1 \data_r2__fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r2_l__spr2 + wire width 64 \data_r2_l__fast2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \data_r2_l__spr2$next + wire width 64 \data_r2_l__fast2$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__spr2_ok + wire width 1 \data_r2_l__fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__spr2_ok$next + wire width 1 \data_r2_l__fast2_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" wire width 65 $83 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" @@ -64773,15 +67208,15 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" cell $mux $86 parameter \WIDTH 65 - connect \A { \data_r2_l__spr2_ok \data_r2_l__spr2 } - connect \B { \spr2_ok \spr2 } + connect \A { \data_r2_l__fast2_ok \data_r2_l__fast2 } + connect \B { \fast2_ok \fast2 } connect \S $84 connect \Y $83 end process $group_45 - assign \data_r2__spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \data_r2__spr2_ok 1'0 - assign { \data_r2__spr2_ok \data_r2__spr2 } $83 + assign \data_r2__fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r2__fast2_ok 1'0 + assign { \data_r2__fast2_ok \data_r2__fast2 } $83 sync init end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" @@ -64795,25 +67230,25 @@ module \trap0 connect \Y $87 end process $group_47 - assign \data_r2_l__spr2$next \data_r2_l__spr2 - assign \data_r2_l__spr2_ok$next \data_r2_l__spr2_ok + assign \data_r2_l__fast2$next \data_r2_l__fast2 + assign \data_r2_l__fast2_ok$next \data_r2_l__fast2_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { $87 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \data_r2_l__spr2_ok$next \data_r2_l__spr2$next } { \spr2_ok \spr2 } + assign { \data_r2_l__fast2_ok$next \data_r2_l__fast2$next } { \fast2_ok \fast2 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \data_r2_l__spr2_ok$next 1'0 + assign \data_r2_l__fast2_ok$next 1'0 end sync init - update \data_r2_l__spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r2_l__spr2_ok 1'0 + update \data_r2_l__fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r2_l__fast2_ok 1'0 sync posedge \clk - update \data_r2_l__spr2 \data_r2_l__spr2$next - update \data_r2_l__spr2_ok \data_r2_l__spr2_ok$next + update \data_r2_l__fast2 \data_r2_l__fast2$next + update \data_r2_l__fast2_ok \data_r2_l__fast2_ok$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" wire width 64 \data_r3__nia @@ -64955,15 +67390,15 @@ module \trap0 end process $group_57 assign \wrmask 5'00000 - assign \wrmask { \data_r4__msr_ok \data_r3__nia_ok \data_r2__spr2_ok \data_r1__spr1_ok \data_r0__o_ok } + assign \wrmask { \data_r4__msr_ok \data_r3__nia_ok \data_r2__fast2_ok \data_r1__fast1_ok \data_r0__o_ok } sync init end process $group_58 assign \alu_trap0_op__insn_type 7'0000000 - assign \alu_trap0_op__fn_unit 10'0000000000 + assign \alu_trap0_op__fn_unit 11'00000000000 assign \alu_trap0_op__insn 32'00000000000000000000000000000000 assign \alu_trap0_op__is_32bit 1'0 - assign \alu_trap0_op__traptype 4'0000 + assign \alu_trap0_op__traptype 5'00000 assign \alu_trap0_op__trapaddr 13'0000000000000 assign { \alu_trap0_op__trapaddr \alu_trap0_op__traptype \alu_trap0_op__is_32bit \alu_trap0_op__insn \alu_trap0_op__fn_unit \alu_trap0_op__insn_type } { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } sync init @@ -65047,8 +67482,8 @@ module \trap0 connect \Y $105 end process $group_68 - assign \alu_trap0_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_trap0_spr1 $105 + assign \alu_trap0_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_trap0_fast1 $105 sync init end process $group_69 @@ -65079,8 +67514,8 @@ module \trap0 connect \Y $107 end process $group_70 - assign \alu_trap0_spr2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_trap0_spr2 $107 + assign \alu_trap0_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_trap0_fast2 $107 sync init end process $group_71 @@ -65405,7 +67840,7 @@ module \trap0 switch { \wr__go [1] } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 - assign \dest2_o { \data_r1__spr1_ok \data_r1__spr1 } [63:0] + assign \dest2_o { \data_r1__fast1_ok \data_r1__fast1 } [63:0] end sync init end @@ -65417,7 +67852,7 @@ module \trap0 switch { \wr__go [2] } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 - assign \dest3_o { \data_r2__spr2_ok \data_r2__spr2 } [63:0] + assign \dest3_o { \data_r2__fast2_ok \data_r2__fast2 } [63:0] end sync init end @@ -65448,7 +67883,7 @@ module \trap0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.p" -module \p$42 +module \p$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -65476,7 +67911,7 @@ module \p$42 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.n" -module \n$43 +module \n$44 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -65504,7 +67939,7 @@ module \n$43 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.p" -module \p$45 +module \p$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -65532,7 +67967,7 @@ module \p$45 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.n" -module \n$46 +module \n$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -65560,7 +67995,7 @@ module \n$46 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.input" -module \input$47 +module \input$48 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -65638,18 +68073,19 @@ module \input$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 input 1 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 input 2 \op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 input 2 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 input 3 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -65771,18 +68207,19 @@ module \input$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 output 24 \op__insn_type$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 output 25 \op__fn_unit$3 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 output 25 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 output 26 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -65864,7 +68301,7 @@ module \input$47 end process $group_3 assign \op__insn_type$2 7'0000000 - assign \op__fn_unit$3 10'0000000000 + assign \op__fn_unit$3 11'00000000000 assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$5 1'0 assign \op__lk$6 1'0 @@ -71872,7 +74309,7 @@ module \clz end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.main" -module \main$48 +module \main$49 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -71950,18 +74387,19 @@ module \main$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 input 1 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 input 2 \op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 input 2 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 input 3 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -72083,18 +74521,19 @@ module \main$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 output 24 \op__insn_type$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 output 25 \op__fn_unit$3 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 output 25 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 output 26 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -73645,7 +76084,7 @@ module \main$48 end process $group_14 assign \op__insn_type$2 7'0000000 - assign \op__fn_unit$3 10'0000000000 + assign \op__fn_unit$3 11'00000000000 assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$5 1'0 assign \op__lk$6 1'0 @@ -73670,7 +76109,7 @@ module \main$48 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.output" -module \output$49 +module \output$50 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -73748,18 +76187,19 @@ module \output$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 input 1 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 input 2 \op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 input 2 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 input 3 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -73885,18 +76325,19 @@ module \output$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 output 26 \op__insn_type$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 output 27 \op__fn_unit$3 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 output 27 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 output 28 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -74210,7 +76651,7 @@ module \output$49 end process $group_16 assign \op__insn_type$2 7'0000000 - assign \op__fn_unit$3 10'0000000000 + assign \op__fn_unit$3 11'00000000000 assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$5 1'0 assign \op__lk$6 1'0 @@ -74236,7 +76677,7 @@ module \output$49 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe" -module \pipe$44 +module \pipe$45 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -74322,18 +76763,19 @@ module \pipe$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 input 5 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 input 6 \op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 input 6 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 input 7 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -74463,20 +76905,21 @@ module \pipe$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 \op__insn_type$2$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 output 31 \op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \op__fn_unit$3$next + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 output 31 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 \op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 output 32 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -74577,11 +77020,11 @@ module \pipe$44 wire width 1 output 55 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \xer_ca_ok$next - cell \p$45 \p + cell \p$46 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$46 \n + cell \n$47 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -74662,18 +77105,19 @@ module \pipe$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 \input_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \input_op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 \input_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 \input_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -74795,18 +77239,19 @@ module \pipe$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 \input_op__insn_type$23 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \input_op__fn_unit$24 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 \input_op__fn_unit$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 \input_op__imm_data__imm$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -74851,7 +77296,7 @@ module \pipe$44 wire width 64 \input_ra$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 64 \input_rb$44 - cell \input$47 \input + cell \input$48 \input connect \muxid \input_muxid connect \op__insn_type \input_op__insn_type connect \op__fn_unit \input_op__fn_unit @@ -74976,18 +77421,19 @@ module \pipe$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 \main_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \main_op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 \main_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 \main_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -75109,18 +77555,19 @@ module \pipe$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 \main_op__insn_type$46 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \main_op__fn_unit$47 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 \main_op__fn_unit$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 \main_op__imm_data__imm$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -75165,7 +77612,7 @@ module \pipe$44 wire width 64 \main_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \main_o_ok - cell \main$48 \main + cell \main$49 \main connect \muxid \main_muxid connect \op__insn_type \main_op__insn_type connect \op__fn_unit \main_op__fn_unit @@ -75290,18 +77737,19 @@ module \pipe$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 \output_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \output_op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 \output_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 \output_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -75427,18 +77875,19 @@ module \pipe$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 \output_op__insn_type$67 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \output_op__fn_unit$68 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 \output_op__fn_unit$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 \output_op__imm_data__imm$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -75491,7 +77940,7 @@ module \pipe$44 wire width 2 \output_xer_ca$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \output_xer_ca_ok - cell \output$49 \output + cell \output$50 \output connect \muxid \output_muxid connect \op__insn_type \output_op__insn_type connect \op__fn_unit \output_op__fn_unit @@ -75552,7 +78001,7 @@ module \pipe$44 end process $group_1 assign \input_op__insn_type 7'0000000 - assign \input_op__fn_unit 10'0000000000 + assign \input_op__fn_unit 11'00000000000 assign \input_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \input_op__imm_data__imm_ok 1'0 assign \input_op__lk 1'0 @@ -75591,7 +78040,7 @@ module \pipe$44 end process $group_24 assign \main_op__insn_type 7'0000000 - assign \main_op__fn_unit 10'0000000000 + assign \main_op__fn_unit 11'00000000000 assign \main_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \main_op__imm_data__imm_ok 1'0 assign \main_op__lk 1'0 @@ -75630,7 +78079,7 @@ module \pipe$44 end process $group_47 assign \output_op__insn_type 7'0000000 - assign \output_op__fn_unit 10'0000000000 + assign \output_op__fn_unit 11'00000000000 assign \output_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \output_op__imm_data__imm_ok 1'0 assign \output_op__lk 1'0 @@ -75798,18 +78247,19 @@ module \pipe$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 \op__insn_type$101 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \op__fn_unit$102 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 \op__fn_unit$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 \op__imm_data__imm$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -75852,7 +78302,7 @@ module \pipe$44 wire width 32 \op__insn$120 process $group_77 assign \op__insn_type$101 7'0000000 - assign \op__fn_unit$102 10'0000000000 + assign \op__fn_unit$102 11'00000000000 assign \op__imm_data__imm$103 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$104 1'0 assign \op__lk$105 1'0 @@ -75990,7 +78440,7 @@ module \pipe$44 end sync init update \op__insn_type$2 7'0000000 - update \op__fn_unit$3 10'0000000000 + update \op__fn_unit$3 11'00000000000 update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 update \op__imm_data__imm_ok$5 1'0 update \op__lk$6 1'0 @@ -76216,18 +78666,19 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 input 10 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 input 11 \op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 input 11 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 input 12 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -76276,11 +78727,11 @@ module \alu_logical0 wire width 1 input 32 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 output 33 \p_ready_o - cell \p$42 \p + cell \p$43 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$43 \n + cell \n$44 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -76365,18 +78816,19 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 \pipe_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \pipe_op__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 \pipe_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 \pipe_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -76502,18 +78954,19 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 \pipe_op__insn_type$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \pipe_op__fn_unit$3 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 \pipe_op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 \pipe_op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -76566,7 +79019,7 @@ module \alu_logical0 wire width 2 \pipe_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \pipe_xer_ca_ok - cell \pipe$44 \pipe + cell \pipe$45 \pipe connect \rst \rst connect \clk \clk connect \p_valid_i \pipe_p_valid_i @@ -76643,7 +79096,7 @@ module \alu_logical0 end process $group_3 assign \pipe_op__insn_type 7'0000000 - assign \pipe_op__fn_unit 10'0000000000 + assign \pipe_op__fn_unit 11'00000000000 assign \pipe_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pipe_op__imm_data__imm_ok 1'0 assign \pipe_op__lk 1'0 @@ -76767,18 +79220,19 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 \op__insn_type$23 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \op__fn_unit$24 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 \op__fn_unit$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 64 \op__imm_data__imm$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -76821,7 +79275,7 @@ module \alu_logical0 wire width 32 \op__insn$42 process $group_28 assign \op__insn_type$23 7'0000000 - assign \op__fn_unit$24 10'0000000000 + assign \op__fn_unit$24 11'00000000000 assign \op__imm_data__imm$25 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$26 1'0 assign \op__lk$27 1'0 @@ -76865,7 +79319,7 @@ module \alu_logical0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l" -module \src_l$50 +module \src_l$51 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -77010,7 +79464,5235 @@ module \src_l$50 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l" -module \opc_l$51 +module \opc_l$52 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_opc + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_opc + connect \Y $11 + end + process $group_1 + assign \q_opc 1'0 + assign \q_opc $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $13 + end + process $group_2 + assign \qn_opc 1'0 + assign \qn_opc $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_opc 1'0 + assign \qlq_opc $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l" +module \req_l$53 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $3 + connect \B \s_req + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 3'000 + end + sync init + update \q_int 3'000 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $9 + connect \B \s_req + connect \Y $11 + end + process $group_1 + assign \q_req 3'000 + assign \q_req $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $13 + end + process $group_2 + assign \qn_req 3'000 + assign \qn_req $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_req 3'000 + assign \qlq_req $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l" +module \rst_l$54 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rst + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rst + connect \Y $11 + end + process $group_1 + assign \q_rst 1'0 + assign \q_rst $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $13 + end + process $group_2 + assign \qn_rst 1'0 + assign \qn_rst $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rst 1'0 + assign \qlq_rst $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l" +module \rok_l$55 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_rdok + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_rdok + connect \Y $11 + end + process $group_1 + assign \q_rdok 1'0 + assign \q_rdok $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $13 + end + process $group_2 + assign \qn_rdok 1'0 + assign \qn_rdok $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rdok 1'0 + assign \qlq_rdok $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l" +module \alui_l$56 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alui + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alui + connect \Y $11 + end + process $group_1 + assign \q_alui 1'0 + assign \q_alui $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $13 + end + process $group_2 + assign \qn_alui 1'0 + assign \qn_alui $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alui 1'0 + assign \qlq_alui $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l" +module \alu_l$57 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 1 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $3 + connect \B \s_alu + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 1'0 + end + sync init + update \q_int 1'0 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $9 + connect \B \s_alu + connect \Y $11 + end + process $group_1 + assign \q_alu 1'0 + assign \q_alu $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 1 \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $13 + end + process $group_2 + assign \qn_alu 1'0 + assign \qn_alu $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 1 \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_alu 1'0 + assign \qlq_alu $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0" +module \logical0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 2 \oper_i__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 input 3 \oper_i__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 4 \oper_i__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 5 \oper_i__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 6 \oper_i__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 7 \oper_i__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 8 \oper_i__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 9 \oper_i__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 10 \oper_i__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 11 \oper_i__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 12 \oper_i__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 13 \oper_i__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 14 \oper_i__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 15 \oper_i__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 16 \oper_i__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 17 \oper_i__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 18 \oper_i__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 19 \oper_i__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 20 \oper_i__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 21 \oper_i__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" + wire width 1 input 22 \issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" + wire width 1 output 23 \busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" + wire width 2 input 24 \rdmaskn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 2 output 25 \rd__rel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 2 input 26 \rd__go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 input 27 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 input 28 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 29 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 output 30 \wr__rel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 input 31 \wr__go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 32 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 33 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 4 output 34 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 35 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 36 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 1 input 37 \go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" + wire width 1 input 38 \shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 64 output 39 \dest1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \alu_logical0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \alu_logical0_n_ready_i + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \alu_logical0_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 \alu_logical0_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \alu_logical0_op__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_logical0_op__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_logical0_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_logical0_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_logical0_op__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_logical0_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_logical0_op__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_logical0_op__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_logical0_op__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \alu_logical0_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_logical0_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \alu_logical0_op__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_logical0_op__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_logical0_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_logical0_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \alu_logical0_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \alu_logical0_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \alu_logical0_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \alu_logical0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \alu_logical0_rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \alu_logical0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \alu_logical0_p_ready_o + cell \alu_logical0 \alu_logical0 + connect \rst \rst + connect \clk \clk + connect \o_ok \o_ok + connect \o \o + connect \cr_a_ok \cr_a_ok + connect \cr_a \cr_a + connect \xer_ca_ok \xer_ca_ok + connect \xer_ca \xer_ca + connect \n_valid_o \alu_logical0_n_valid_o + connect \n_ready_i \alu_logical0_n_ready_i + connect \op__insn_type \alu_logical0_op__insn_type + connect \op__fn_unit \alu_logical0_op__fn_unit + connect \op__imm_data__imm \alu_logical0_op__imm_data__imm + connect \op__imm_data__imm_ok \alu_logical0_op__imm_data__imm_ok + connect \op__lk \alu_logical0_op__lk + connect \op__rc__rc \alu_logical0_op__rc__rc + connect \op__rc__rc_ok \alu_logical0_op__rc__rc_ok + connect \op__oe__oe \alu_logical0_op__oe__oe + connect \op__oe__oe_ok \alu_logical0_op__oe__oe_ok + connect \op__invert_a \alu_logical0_op__invert_a + connect \op__zero_a \alu_logical0_op__zero_a + connect \op__input_carry \alu_logical0_op__input_carry + connect \op__invert_out \alu_logical0_op__invert_out + connect \op__write_cr__data \alu_logical0_op__write_cr__data + connect \op__write_cr__ok \alu_logical0_op__write_cr__ok + connect \op__output_carry \alu_logical0_op__output_carry + connect \op__is_32bit \alu_logical0_op__is_32bit + connect \op__is_signed \alu_logical0_op__is_signed + connect \op__data_len \alu_logical0_op__data_len + connect \op__insn \alu_logical0_op__insn + connect \ra \alu_logical0_ra + connect \rb \alu_logical0_rb + connect \p_valid_i \alu_logical0_p_valid_i + connect \p_ready_o \alu_logical0_p_ready_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 2 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 2 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 2 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 2 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 2 \src_l_q_src + cell \src_l$51 \src_l + connect \rst \rst + connect \clk \clk + connect \s_src \src_l_s_src + connect \r_src \src_l_r_src + connect \q_src \src_l_q_src + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \opc_l_q_opc + cell \opc_l$52 \opc_l + connect \rst \rst + connect \clk \clk + connect \s_opc \opc_l_s_opc + connect \r_opc \opc_l_r_opc + connect \q_opc \opc_l_q_opc + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 \req_l_r_req + cell \req_l$53 \req_l + connect \rst \rst + connect \clk \clk + connect \q_req \req_l_q_req + connect \s_req \req_l_s_req + connect \r_req \req_l_r_req + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rst_l_r_rst + cell \rst_l$54 \rst_l + connect \rst \rst + connect \clk \clk + connect \s_rst \rst_l_s_rst + connect \r_rst \rst_l_r_rst + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \rok_l_r_rdok$next + cell \rok_l$55 \rok_l + connect \rst \rst + connect \clk \clk + connect \q_rdok \rok_l_q_rdok + connect \s_rdok \rok_l_s_rdok + connect \r_rdok \rok_l_r_rdok + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alui_l_s_alui + cell \alui_l$56 \alui_l + connect \rst \rst + connect \clk \clk + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 1 \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 1 \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 1 \alu_l_s_alu + cell \alu_l$57 \alu_l + connect \rst \rst + connect \clk \clk + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178" + wire width 1 \all_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B \rok_l_q_rdok + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" + wire width 2 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" + cell $not $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \rd__rel + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" + wire width 2 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" + cell $or $7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $4 + connect \B \rd__go + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" + cell $reduce_and $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A $6 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" + wire width 1 $9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $1 + connect \B $3 + connect \Y $9 + end + process $group_0 + assign \all_rd 1'0 + assign \all_rd $9 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" + wire width 1 \all_rd_dly + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183" + wire width 1 \all_rd_dly$next + process $group_1 + assign \all_rd_dly$next \all_rd_dly + assign \all_rd_dly$next \all_rd + sync init + update \all_rd_dly 1'0 + sync posedge \clk + update \all_rd_dly \all_rd_dly$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184" + wire width 1 \all_rd_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" + cell $not $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" + wire width 1 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186" + cell $and $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B $11 + connect \Y $13 + end + process $group_2 + assign \all_rd_pulse 1'0 + assign \all_rd_pulse $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + wire width 1 \alu_done + process $group_3 + assign \alu_done 1'0 + assign \alu_done \alu_logical0_n_valid_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" + wire width 1 \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" + wire width 1 \alu_done_dly$next + process $group_4 + assign \alu_done_dly$next \alu_done_dly + assign \alu_done_dly$next \alu_done + sync init + update \alu_done_dly 1'0 + sync posedge \clk + update \alu_done_dly \alu_done_dly$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191" + wire width 1 \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" + wire width 1 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" + cell $not $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $15 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" + wire width 1 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195" + cell $and $18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B $15 + connect \Y $17 + end + process $group_5 + assign \alu_pulse 1'0 + assign \alu_pulse $17 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" + wire width 3 \alu_pulsem + process $group_6 + assign \alu_pulsem 3'000 + assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" + wire width 3 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" + wire width 3 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" + wire width 3 $19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" + cell $and $20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \wr__go + connect \B { \busy_o \busy_o \busy_o } + connect \Y $19 + end + process $group_7 + assign \prev_wr_go$next \prev_wr_go + assign \prev_wr_go$next $19 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \prev_wr_go$next 3'000 + end + sync init + update \prev_wr_go 3'000 + sync posedge \clk + update \prev_wr_go \prev_wr_go$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire width 1 \done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + wire width 1 $21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + wire width 3 $23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93" + wire width 3 \wrmask + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + cell $not $24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \wrmask + connect \Y $23 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + wire width 3 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + cell $and $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \wr__rel + connect \B $23 + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + cell $reduce_bool $27 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A $25 + connect \Y $22 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + cell $not $28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $22 + connect \Y $21 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + wire width 1 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" + cell $and $30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B $21 + connect \Y $29 + end + process $group_8 + assign \done_o 1'0 + assign \done_o $29 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" + wire width 1 \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + wire width 1 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + cell $reduce_bool $32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \wr__go + connect \Y $31 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + wire width 1 $33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + cell $reduce_bool $34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $33 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + wire width 1 $35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" + cell $or $36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $31 + connect \B $33 + connect \Y $35 + end + process $group_9 + assign \wr_any 1'0 + assign \wr_any $35 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207" + wire width 1 \req_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire width 1 $37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + cell $not $38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_n_ready_i + connect \Y $37 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire width 1 $39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + cell $and $40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B $37 + connect \Y $39 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire width 3 $41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + cell $and $42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B \wrmask + connect \Y $41 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire width 1 $43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + cell $eq $44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $41 + connect \B 1'0 + connect \Y $43 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire width 1 $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + cell $and $46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $39 + connect \B $43 + connect \Y $45 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrmask + connect \B 1'0 + connect \Y $47 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $47 + connect \B \alu_logical0_n_ready_i + connect \Y $49 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $49 + connect \B \alu_logical0_n_valid_o + connect \Y $51 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + wire width 1 $53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $51 + connect \B \busy_o + connect \Y $53 + end + process $group_10 + assign \req_done 1'0 + assign \req_done $45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + switch { $53 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + case 1'1 + assign \req_done 1'1 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221" + wire width 1 \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + wire width 1 $55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225" + cell $or $56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \go_die_i + connect \Y $55 + end + process $group_11 + assign \reset 1'0 + assign \reset $55 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + wire width 1 \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire width 1 $57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + cell $or $58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \issue_i + connect \B \go_die_i + connect \Y $57 + end + process $group_12 + assign \rst_r 1'0 + assign \rst_r $57 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" + wire width 3 \reset_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire width 3 $59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + cell $or $60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \wr__go + connect \B { \go_die_i \go_die_i \go_die_i } + connect \Y $59 + end + process $group_13 + assign \reset_w 3'000 + assign \reset_w $59 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" + wire width 2 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 2 $61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + cell $or $62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \rd__go + connect \B { \go_die_i \go_die_i } + connect \Y $61 + end + process $group_14 + assign \reset_r 2'00 + assign \reset_r $61 + sync init + end + process $group_15 + assign \rok_l_s_rdok 1'0 + assign \rok_l_s_rdok \issue_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + wire width 1 $63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $and $64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_n_valid_o + connect \B \busy_o + connect \Y $63 + end + process $group_16 + assign \rok_l_r_rdok$next \rok_l_r_rdok + assign \rok_l_r_rdok$next $63 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \rok_l_r_rdok$next 1'1 + end + sync init + update \rok_l_r_rdok 1'1 + sync posedge \clk + update \rok_l_r_rdok \rok_l_r_rdok$next + end + process $group_17 + assign \rst_l_s_rst 1'0 + assign \rst_l_s_rst \all_rd + sync init + end + process $group_18 + assign \rst_l_r_rst 1'1 + assign \rst_l_r_rst \rst_r + sync init + end + process $group_19 + assign \opc_l_s_opc$next \opc_l_s_opc + assign \opc_l_s_opc$next \issue_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \opc_l_s_opc$next 1'0 + end + sync init + update \opc_l_s_opc 1'0 + sync posedge \clk + update \opc_l_s_opc \opc_l_s_opc$next + end + process $group_20 + assign \opc_l_r_opc$next \opc_l_r_opc + assign \opc_l_r_opc$next \req_done + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \opc_l_r_opc$next 1'1 + end + sync init + update \opc_l_r_opc 1'1 + sync posedge \clk + update \opc_l_r_opc \opc_l_r_opc$next + end + process $group_21 + assign \src_l_s_src$next \src_l_s_src + assign \src_l_s_src$next { \issue_i \issue_i } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \src_l_s_src$next 2'00 + end + sync init + update \src_l_s_src 2'00 + sync posedge \clk + update \src_l_s_src \src_l_s_src$next + end + process $group_22 + assign \src_l_r_src$next \src_l_r_src + assign \src_l_r_src$next \reset_r + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \src_l_r_src$next 2'11 + end + sync init + update \src_l_r_src 2'11 + sync posedge \clk + update \src_l_r_src \src_l_r_src$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + wire width 3 $65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" + cell $and $66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \alu_pulsem + connect \B \wrmask + connect \Y $65 + end + process $group_23 + assign \req_l_s_req 3'000 + assign \req_l_s_req $65 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" + wire width 3 $67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" + cell $or $68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $67 + end + process $group_24 + assign \req_l_r_req 3'111 + assign \req_l_r_req $67 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 \oper_r__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 \oper_r__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 \oper_r__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__invert_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__zero_a + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 \oper_r__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 \oper_r__write_cr__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 \oper_r__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 \oper_r__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 \oper_r__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 7 \oper_l__insn_type$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 11 \oper_l__fn_unit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 11 \oper_l__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \oper_l__imm_data__imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \oper_l__imm_data__imm$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__imm_data__imm_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__imm_data__imm_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__lk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__lk$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__rc__rc_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__oe__oe_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__invert_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__invert_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__zero_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \oper_l__input_carry + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \oper_l__input_carry$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__invert_out + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__invert_out$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 3 \oper_l__write_cr__data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 3 \oper_l__write_cr__data$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__write_cr__ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__write_cr__ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__output_carry + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__output_carry$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_signed + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \oper_l__is_signed$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \oper_l__data_len + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \oper_l__data_len$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 32 \oper_l__insn$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 136 $69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $70 + parameter \WIDTH 136 + connect \A { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } \oper_l__invert_out \oper_l__input_carry \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } + connect \B { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } + connect \S \issue_i + connect \Y $69 + end + process $group_25 + assign \oper_r__insn_type 7'0000000 + assign \oper_r__fn_unit 11'00000000000 + assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oper_r__imm_data__imm_ok 1'0 + assign \oper_r__lk 1'0 + assign \oper_r__rc__rc 1'0 + assign \oper_r__rc__rc_ok 1'0 + assign \oper_r__oe__oe 1'0 + assign \oper_r__oe__oe_ok 1'0 + assign \oper_r__invert_a 1'0 + assign \oper_r__zero_a 1'0 + assign \oper_r__input_carry 2'00 + assign \oper_r__invert_out 1'0 + assign \oper_r__write_cr__data 3'000 + assign \oper_r__write_cr__ok 1'0 + assign \oper_r__output_carry 1'0 + assign \oper_r__is_32bit 1'0 + assign \oper_r__is_signed 1'0 + assign \oper_r__data_len 4'0000 + assign \oper_r__insn 32'00000000000000000000000000000000 + assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $69 + sync init + end + process $group_45 + assign \oper_l__insn_type$next \oper_l__insn_type + assign \oper_l__fn_unit$next \oper_l__fn_unit + assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm + assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok + assign \oper_l__lk$next \oper_l__lk + assign \oper_l__rc__rc$next \oper_l__rc__rc + assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok + assign \oper_l__oe__oe$next \oper_l__oe__oe + assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok + assign \oper_l__invert_a$next \oper_l__invert_a + assign \oper_l__zero_a$next \oper_l__zero_a + assign \oper_l__input_carry$next \oper_l__input_carry + assign \oper_l__invert_out$next \oper_l__invert_out + assign \oper_l__write_cr__data$next \oper_l__write_cr__data + assign \oper_l__write_cr__ok$next \oper_l__write_cr__ok + assign \oper_l__output_carry$next \oper_l__output_carry + assign \oper_l__is_32bit$next \oper_l__is_32bit + assign \oper_l__is_signed$next \oper_l__is_signed + assign \oper_l__data_len$next \oper_l__data_len + assign \oper_l__insn$next \oper_l__insn + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \issue_i } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oper_l__imm_data__imm_ok$next 1'0 + assign \oper_l__rc__rc$next 1'0 + assign \oper_l__rc__rc_ok$next 1'0 + assign \oper_l__oe__oe$next 1'0 + assign \oper_l__oe__oe_ok$next 1'0 + assign \oper_l__write_cr__data$next 3'000 + assign \oper_l__write_cr__ok$next 1'0 + assign \oper_l__insn$next 32'00000000000000000000000000000000 + end + sync init + update \oper_l__insn_type 7'0000000 + update \oper_l__fn_unit 11'00000000000 + update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + update \oper_l__imm_data__imm_ok 1'0 + update \oper_l__lk 1'0 + update \oper_l__rc__rc 1'0 + update \oper_l__rc__rc_ok 1'0 + update \oper_l__oe__oe 1'0 + update \oper_l__oe__oe_ok 1'0 + update \oper_l__invert_a 1'0 + update \oper_l__zero_a 1'0 + update \oper_l__input_carry 2'00 + update \oper_l__invert_out 1'0 + update \oper_l__write_cr__data 3'000 + update \oper_l__write_cr__ok 1'0 + update \oper_l__output_carry 1'0 + update \oper_l__is_32bit 1'0 + update \oper_l__is_signed 1'0 + update \oper_l__data_len 4'0000 + update \oper_l__insn 32'00000000000000000000000000000000 + sync posedge \clk + update \oper_l__insn_type \oper_l__insn_type$next + update \oper_l__fn_unit \oper_l__fn_unit$next + update \oper_l__imm_data__imm \oper_l__imm_data__imm$next + update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next + update \oper_l__lk \oper_l__lk$next + update \oper_l__rc__rc \oper_l__rc__rc$next + update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next + update \oper_l__oe__oe \oper_l__oe__oe$next + update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next + update \oper_l__invert_a \oper_l__invert_a$next + update \oper_l__zero_a \oper_l__zero_a$next + update \oper_l__input_carry \oper_l__input_carry$next + update \oper_l__invert_out \oper_l__invert_out$next + update \oper_l__write_cr__data \oper_l__write_cr__data$next + update \oper_l__write_cr__ok \oper_l__write_cr__ok$next + update \oper_l__output_carry \oper_l__output_carry$next + update \oper_l__is_32bit \oper_l__is_32bit$next + update \oper_l__is_signed \oper_l__is_signed$next + update \oper_l__data_len \oper_l__data_len$next + update \oper_l__insn \oper_l__insn$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r0_l__o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 64 \data_r0_l__o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r0_l__o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r0_l__o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 65 $71 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $72 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $72 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $74 + parameter \WIDTH 65 + connect \A { \data_r0_l__o_ok \data_r0_l__o } + connect \B { \o_ok \o } + connect \S $72 + connect \Y $71 + end + process $group_65 + assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r0__o_ok 1'0 + assign { \data_r0__o_ok \data_r0__o } $71 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $75 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $75 + end + process $group_67 + assign \data_r0_l__o$next \data_r0_l__o + assign \data_r0_l__o_ok$next \data_r0_l__o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $75 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \data_r0_l__o_ok$next 1'0 + end + sync init + update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r0_l__o_ok 1'0 + sync posedge \clk + update \data_r0_l__o \data_r0_l__o$next + update \data_r0_l__o_ok \data_r0_l__o_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \data_r1_l__cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 4 \data_r1_l__cr_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r1_l__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 5 $77 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $78 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $79 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $78 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $80 + parameter \WIDTH 5 + connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a } + connect \B { \cr_a_ok \cr_a } + connect \S $78 + connect \Y $77 + end + process $group_69 + assign \data_r1__cr_a 4'0000 + assign \data_r1__cr_a_ok 1'0 + assign { \data_r1__cr_a_ok \data_r1__cr_a } $77 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $81 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $81 + end + process $group_71 + assign \data_r1_l__cr_a$next \data_r1_l__cr_a + assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $81 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \cr_a } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \data_r1_l__cr_a_ok$next 1'0 + end + sync init + update \data_r1_l__cr_a 4'0000 + update \data_r1_l__cr_a_ok 1'0 + sync posedge \clk + update \data_r1_l__cr_a \data_r1_l__cr_a$next + update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r2_l__xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r2_l__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r2_l__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 3 $83 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $84 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $85 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $84 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $86 + parameter \WIDTH 3 + connect \A { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca } + connect \B { \xer_ca_ok \xer_ca } + connect \S $84 + connect \Y $83 + end + process $group_73 + assign \data_r2__xer_ca 2'00 + assign \data_r2__xer_ca_ok 1'0 + assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $83 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $87 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $87 + end + process $group_75 + assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca + assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $87 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \xer_ca } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \data_r2_l__xer_ca_ok$next 1'0 + end + sync init + update \data_r2_l__xer_ca 2'00 + update \data_r2_l__xer_ca_ok 1'0 + sync posedge \clk + update \data_r2_l__xer_ca \data_r2_l__xer_ca$next + update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next + end + process $group_77 + assign \wrmask 3'000 + assign \wrmask { \data_r2__xer_ca_ok \data_r1__cr_a_ok \data_r0__o_ok } + sync init + end + process $group_78 + assign \alu_logical0_op__insn_type 7'0000000 + assign \alu_logical0_op__fn_unit 11'00000000000 + assign \alu_logical0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_logical0_op__imm_data__imm_ok 1'0 + assign \alu_logical0_op__lk 1'0 + assign \alu_logical0_op__rc__rc 1'0 + assign \alu_logical0_op__rc__rc_ok 1'0 + assign \alu_logical0_op__oe__oe 1'0 + assign \alu_logical0_op__oe__oe_ok 1'0 + assign \alu_logical0_op__invert_a 1'0 + assign \alu_logical0_op__zero_a 1'0 + assign \alu_logical0_op__input_carry 2'00 + assign \alu_logical0_op__invert_out 1'0 + assign \alu_logical0_op__write_cr__data 3'000 + assign \alu_logical0_op__write_cr__ok 1'0 + assign \alu_logical0_op__output_carry 1'0 + assign \alu_logical0_op__is_32bit 1'0 + assign \alu_logical0_op__is_signed 1'0 + assign \alu_logical0_op__data_len 4'0000 + assign \alu_logical0_op__insn 32'00000000000000000000000000000000 + assign { \alu_logical0_op__insn \alu_logical0_op__data_len \alu_logical0_op__is_signed \alu_logical0_op__is_32bit \alu_logical0_op__output_carry { \alu_logical0_op__write_cr__ok \alu_logical0_op__write_cr__data } \alu_logical0_op__invert_out \alu_logical0_op__input_carry \alu_logical0_op__zero_a \alu_logical0_op__invert_a { \alu_logical0_op__oe__oe_ok \alu_logical0_op__oe__oe } { \alu_logical0_op__rc__rc_ok \alu_logical0_op__rc__rc } \alu_logical0_op__lk { \alu_logical0_op__imm_data__imm_ok \alu_logical0_op__imm_data__imm } \alu_logical0_op__fn_unit \alu_logical0_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" + wire width 1 \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + wire width 1 $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + cell $mux $90 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \oper_r__zero_a + connect \Y $89 + end + process $group_98 + assign \src_sel 1'0 + assign \src_sel $89 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + wire width 64 $91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + cell $mux $92 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \oper_r__zero_a + connect \Y $91 + end + process $group_99 + assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm $91 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" + wire width 1 \src_sel$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + wire width 1 $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" + cell $mux $95 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \oper_r__imm_data__imm_ok + connect \Y $94 + end + process $group_100 + assign \src_sel$93 1'0 + assign \src_sel$93 $94 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" + wire width 64 \src_or_imm$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + wire width 64 $97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" + cell $mux $98 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \oper_r__imm_data__imm + connect \S \oper_r__imm_data__imm_ok + connect \Y $97 + end + process $group_101 + assign \src_or_imm$96 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src_or_imm$96 $97 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $99 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $100 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $99 + end + process $group_102 + assign \alu_logical0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_logical0_ra $99 + sync init + end + process $group_103 + assign \src_r0$next \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_sel } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r0$next \src_or_imm + end + sync init + update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \src_r0 \src_r0$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $102 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$96 + connect \S \src_sel$93 + connect \Y $101 + end + process $group_104 + assign \alu_logical0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_logical0_rb $101 + sync init + end + process $group_105 + assign \src_r1$next \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_sel$93 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r1$next \src_or_imm$96 + end + sync init + update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \src_r1 \src_r1$next + end + process $group_106 + assign \alu_logical0_p_valid_i 1'0 + assign \alu_logical0_p_valid_i \alui_l_q_alui + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + wire width 1 $103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" + cell $and $104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $103 + end + process $group_107 + assign \alui_l_r_alui$next \alui_l_r_alui + assign \alui_l_r_alui$next $103 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \alui_l_r_alui$next 1'1 + end + sync init + update \alui_l_r_alui 1'1 + sync posedge \clk + update \alui_l_r_alui \alui_l_r_alui$next + end + process $group_108 + assign \alui_l_s_alui 1'0 + assign \alui_l_s_alui \all_rd_pulse + sync init + end + process $group_109 + assign \alu_logical0_n_ready_i 1'0 + assign \alu_logical0_n_ready_i \alu_l_q_alu + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" + cell $and $106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $105 + end + process $group_110 + assign \alu_l_r_alu$next \alu_l_r_alu + assign \alu_l_r_alu$next $105 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \alu_l_r_alu$next 1'1 + end + sync init + update \alu_l_r_alu 1'1 + sync posedge \clk + update \alu_l_r_alu \alu_l_r_alu$next + end + process $group_111 + assign \alu_l_s_alu 1'0 + assign \alu_l_s_alu \all_rd_pulse + sync init + end + process $group_112 + assign \busy_o 1'0 + assign \busy_o \opc_l_q_opc + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 2 $107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \src_l_q_src + connect \B { \busy_o \busy_o } + connect \Y $107 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + wire width 1 $109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + cell $not $110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oper_r__zero_a + connect \Y $109 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + wire width 1 $111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" + cell $not $112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oper_r__imm_data__imm_ok + connect \Y $111 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 2 $113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $107 + connect \B { $111 $109 } + connect \Y $113 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 2 $115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $not $116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \rdmaskn + connect \Y $115 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + wire width 2 $117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" + cell $and $118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $113 + connect \B $115 + connect \Y $117 + end + process $group_113 + assign \rd__rel 2'00 + assign \rd__rel $117 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B \shadown_i + connect \Y $119 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B \shadown_i + connect \Y $121 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B \shadown_i + connect \Y $123 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 3 $125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B { $119 $121 $123 } + connect \Y $125 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + wire width 3 $127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" + cell $and $128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A $125 + connect \B \wrmask + connect \Y $127 + end + process $group_114 + assign \wr__rel 3'000 + assign \wr__rel $127 + sync init + end + process $group_115 + assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" + switch { \wr__go [0] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" + case 1'1 + assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 4 \dest2_o + process $group_116 + assign \dest2_o 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" + switch { \wr__go [1] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" + case 1'1 + assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 2 \dest3_o + process $group_117 + assign \dest3_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" + switch { \wr__go [2] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" + case 1'1 + assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] + end + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.p" +module \p$58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.n" +module \n$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.p" +module \p$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.n" +module \n$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295" + cell $and $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.spr_main" +module \spr_main + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 0 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 input 1 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 input 2 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 input 3 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 input 4 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 5 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 6 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 7 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 input 8 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 input 9 \xer_ca + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 10 \muxid$1 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 output 11 \op__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 output 12 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 output 13 \op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 output 14 \op__is_32bit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 15 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 16 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 17 \fast1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 18 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 19 \xer_so$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 20 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 21 \xer_ov$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 22 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 23 \xer_ca$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 24 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42" + wire width 10 \spr + process $group_0 + assign \spr 10'0000000000 + assign \spr { { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] } { \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] } } + sync init + end + process $group_1 + assign \fast1$6 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + assign \fast1$6 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + end + sync init + end + process $group_2 + assign \fast1_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + assign \fast1_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + end + sync init + end + process $group_3 + assign \xer_so$7 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + assign \xer_so$7 \ra [31] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + end + sync init + end + process $group_4 + assign \xer_so_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + assign \xer_so_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + end + sync init + end + process $group_5 + assign \xer_ov$8 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + assign \xer_ov$8 [0] \ra [30] + assign \xer_ov$8 [1] \ra [19] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + end + sync init + end + process $group_6 + assign \xer_ov_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + assign \xer_ov_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + end + sync init + end + process $group_7 + assign \xer_ca$9 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + assign \xer_ca$9 [0] \ra [29] + assign \xer_ca$9 [1] \ra [18] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + end + sync init + end + process $group_8 + assign \xer_ca_ok 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:51" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:55" + case 10'0000000001 + assign \xer_ca_ok 1'1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + end + sync init + end + process $group_10 + assign \o_ok 1'0 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" + attribute \nmigen.decoding "OP_MTSPR/49" + case 7'0110001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" + attribute \nmigen.decoding "OP_MFSPR/46" + case 7'0101110 + assign \o_ok 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:72" + switch \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:74" + case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011 + assign \o \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" + case 10'0000000001 + assign { \o_ok \o } [31] \xer_so + assign { \o_ok \o } [30] \xer_ov [0] + assign { \o_ok \o } [19] \xer_ov [1] + assign { \o_ok \o } [29] \xer_ca [0] + assign { \o_ok \o } [18] \xer_ca [1] + end + end + sync init + end + process $group_11 + assign \muxid$1 2'00 + assign \muxid$1 \muxid + sync init + end + process $group_12 + assign \op__insn_type$2 7'0000000 + assign \op__fn_unit$3 11'00000000000 + assign \op__insn$4 32'00000000000000000000000000000000 + assign \op__is_32bit$5 1'0 + assign { \op__is_32bit$5 \op__insn$4 \op__fn_unit$3 \op__insn_type$2 } { \op__is_32bit \op__insn \op__fn_unit \op__insn_type } + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe" +module \pipe$60 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 4 \muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 input 5 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 input 6 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 input 7 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 input 8 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 9 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 10 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 11 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 12 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 input 13 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 input 14 \xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 15 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 16 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 17 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$1$next + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 output 18 \op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 \op__insn_type$2$next + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 output 19 \op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 \op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 output 20 \op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 \op__insn$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 output 21 \op__is_32bit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 \op__is_32bit$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 24 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \spr1$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 25 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \spr1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 26 \fast1$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \fast1$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 27 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 28 \xer_so$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_so$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 29 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 30 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \xer_ov$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 31 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 32 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \xer_ca$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 33 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_ca_ok$next + cell \p$61 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$62 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \spr_main_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 \spr_main_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 \spr_main_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 \spr_main_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 \spr_main_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \spr_main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \spr_main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \spr_main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 \spr_main_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 \spr_main_xer_ca + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \spr_main_muxid$11 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 \spr_main_op__insn_type$12 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 \spr_main_op__fn_unit$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 \spr_main_op__insn$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 \spr_main_op__is_32bit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \spr_main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \spr_main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \spr_main_fast1$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \spr_main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \spr_main_xer_so$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \spr_main_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \spr_main_xer_ov$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \spr_main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \spr_main_xer_ca$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \spr_main_xer_ca_ok + cell \spr_main \spr_main + connect \muxid \spr_main_muxid + connect \op__insn_type \spr_main_op__insn_type + connect \op__fn_unit \spr_main_op__fn_unit + connect \op__insn \spr_main_op__insn + connect \op__is_32bit \spr_main_op__is_32bit + connect \ra \spr_main_ra + connect \fast1 \spr_main_fast1 + connect \xer_so \spr_main_xer_so + connect \xer_ov \spr_main_xer_ov + connect \xer_ca \spr_main_xer_ca + connect \muxid$1 \spr_main_muxid$11 + connect \op__insn_type$2 \spr_main_op__insn_type$12 + connect \op__fn_unit$3 \spr_main_op__fn_unit$13 + connect \op__insn$4 \spr_main_op__insn$14 + connect \op__is_32bit$5 \spr_main_op__is_32bit$15 + connect \o \spr_main_o + connect \o_ok \spr_main_o_ok + connect \fast1$6 \spr_main_fast1$16 + connect \fast1_ok \spr_main_fast1_ok + connect \xer_so$7 \spr_main_xer_so$17 + connect \xer_so_ok \spr_main_xer_so_ok + connect \xer_ov$8 \spr_main_xer_ov$18 + connect \xer_ov_ok \spr_main_xer_ov_ok + connect \xer_ca$9 \spr_main_xer_ca$19 + connect \xer_ca_ok \spr_main_xer_ca_ok + end + process $group_0 + assign \spr_main_muxid 2'00 + assign \spr_main_muxid \muxid + sync init + end + process $group_1 + assign \spr_main_op__insn_type 7'0000000 + assign \spr_main_op__fn_unit 11'00000000000 + assign \spr_main_op__insn 32'00000000000000000000000000000000 + assign \spr_main_op__is_32bit 1'0 + assign { \spr_main_op__is_32bit \spr_main_op__insn \spr_main_op__fn_unit \spr_main_op__insn_type } { \op__is_32bit \op__insn \op__fn_unit \op__insn_type } + sync init + end + process $group_5 + assign \spr_main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \spr_main_ra \ra + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \spr1$20 + process $group_6 + assign \spr1$20 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \spr1$20 \spr1 + sync init + end + process $group_7 + assign \spr_main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \spr_main_fast1 \fast1 + sync init + end + process $group_8 + assign \spr_main_xer_so 1'0 + assign \spr_main_xer_so \xer_so + sync init + end + process $group_9 + assign \spr_main_xer_ov 2'00 + assign \spr_main_xer_ov \xer_ov + sync init + end + process $group_10 + assign \spr_main_xer_ca 2'00 + assign \spr_main_xer_ca \xer_ca + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i$21 + process $group_11 + assign \p_valid_i$21 1'0 + assign \p_valid_i$21 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_12 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$21 + connect \B \p_ready_o + connect \Y $22 + end + process $group_13 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$24 + process $group_14 + assign \muxid$24 2'00 + assign \muxid$24 \spr_main_muxid$11 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 \op__insn_type$25 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 \op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 \op__insn$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 \op__is_32bit$28 + process $group_15 + assign \op__insn_type$25 7'0000000 + assign \op__fn_unit$26 11'00000000000 + assign \op__insn$27 32'00000000000000000000000000000000 + assign \op__is_32bit$28 1'0 + assign { \op__is_32bit$28 \op__insn$27 \op__fn_unit$26 \op__insn_type$25 } { \spr_main_op__is_32bit$15 \spr_main_op__insn$14 \spr_main_op__fn_unit$13 \spr_main_op__insn_type$12 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \o_ok$30 + process $group_19 + assign \o$29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok$30 1'0 + assign { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \spr1$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \spr1_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \spr1$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \spr1_ok$34 + process $group_21 + assign \spr1$31 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \spr1_ok$32 1'0 + assign { \spr1_ok$32 \spr1$31 } { \spr1_ok$34 \spr1$33 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \fast1$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fast1_ok$36 + process $group_23 + assign \fast1$35 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast1_ok$36 1'0 + assign { \fast1_ok$36 \fast1$35 } { \spr_main_fast1_ok \spr_main_fast1$16 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_so$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_so_ok$38 + process $group_25 + assign \xer_so$37 1'0 + assign \xer_so_ok$38 1'0 + assign { \xer_so_ok$38 \xer_so$37 } { \spr_main_xer_so_ok \spr_main_xer_so$17 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \xer_ov$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_ov_ok$40 + process $group_27 + assign \xer_ov$39 2'00 + assign \xer_ov_ok$40 1'0 + assign { \xer_ov_ok$40 \xer_ov$39 } { \spr_main_xer_ov_ok \spr_main_xer_ov$18 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \xer_ca$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \xer_ca_ok$42 + process $group_29 + assign \xer_ca$41 2'00 + assign \xer_ca_ok$42 1'0 + assign { \xer_ca_ok$42 \xer_ca$41 } { \spr_main_xer_ca_ok \spr_main_xer_ca$19 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_31 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_32 + assign \muxid$1$next \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$1$next \muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$1$next \muxid$24 + end + sync init + update \muxid$1 2'00 + sync posedge \clk + update \muxid$1 \muxid$1$next + end + process $group_33 + assign \op__insn_type$2$next \op__insn_type$2 + assign \op__fn_unit$3$next \op__fn_unit$3 + assign \op__insn$4$next \op__insn$4 + assign \op__is_32bit$5$next \op__is_32bit$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \op__is_32bit$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__is_32bit$28 \op__insn$27 \op__fn_unit$26 \op__insn_type$25 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \op__is_32bit$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__is_32bit$28 \op__insn$27 \op__fn_unit$26 \op__insn_type$25 } + end + sync init + update \op__insn_type$2 7'0000000 + update \op__fn_unit$3 11'00000000000 + update \op__insn$4 32'00000000000000000000000000000000 + update \op__is_32bit$5 1'0 + sync posedge \clk + update \op__insn_type$2 \op__insn_type$2$next + update \op__fn_unit$3 \op__fn_unit$3$next + update \op__insn$4 \op__insn$4$next + update \op__is_32bit$5 \op__is_32bit$5$next + end + process $group_37 + assign \o$next \o + assign \o_ok$next \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \o_ok$next \o$next } { \o_ok$30 \o$29 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \o_ok$next \o$next } { \o_ok$30 \o$29 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \o_ok$next 1'0 + end + sync init + update \o 64'0000000000000000000000000000000000000000000000000000000000000000 + update \o_ok 1'0 + sync posedge \clk + update \o \o$next + update \o_ok \o_ok$next + end + process $group_39 + assign \spr1$6$next \spr1$6 + assign \spr1_ok$next \spr1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \spr1_ok$next \spr1$6$next } { \spr1_ok$32 \spr1$31 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \spr1_ok$next \spr1$6$next } { \spr1_ok$32 \spr1$31 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \spr1_ok$next 1'0 + end + sync init + update \spr1$6 64'0000000000000000000000000000000000000000000000000000000000000000 + update \spr1_ok 1'0 + sync posedge \clk + update \spr1$6 \spr1$6$next + update \spr1_ok \spr1_ok$next + end + process $group_41 + assign \fast1$7$next \fast1$7 + assign \fast1_ok$next \fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \fast1_ok$next \fast1$7$next } { \fast1_ok$36 \fast1$35 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \fast1_ok$next \fast1$7$next } { \fast1_ok$36 \fast1$35 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \fast1_ok$next 1'0 + end + sync init + update \fast1$7 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast1_ok 1'0 + sync posedge \clk + update \fast1$7 \fast1$7$next + update \fast1_ok \fast1_ok$next + end + process $group_43 + assign \xer_so$8$next \xer_so$8 + assign \xer_so_ok$next \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_so_ok$next \xer_so$8$next } { \xer_so_ok$38 \xer_so$37 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_so_ok$next \xer_so$8$next } { \xer_so_ok$38 \xer_so$37 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \xer_so_ok$next 1'0 + end + sync init + update \xer_so$8 1'0 + update \xer_so_ok 1'0 + sync posedge \clk + update \xer_so$8 \xer_so$8$next + update \xer_so_ok \xer_so_ok$next + end + process $group_45 + assign \xer_ov$9$next \xer_ov$9 + assign \xer_ov_ok$next \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ov_ok$next \xer_ov$9$next } { \xer_ov_ok$40 \xer_ov$39 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ov_ok$next \xer_ov$9$next } { \xer_ov_ok$40 \xer_ov$39 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \xer_ov_ok$next 1'0 + end + sync init + update \xer_ov$9 2'00 + update \xer_ov_ok 1'0 + sync posedge \clk + update \xer_ov$9 \xer_ov$9$next + update \xer_ov_ok \xer_ov_ok$next + end + process $group_47 + assign \xer_ca$10$next \xer_ca$10 + assign \xer_ca_ok$next \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign { \xer_ca_ok$next \xer_ca$10$next } { \xer_ca_ok$42 \xer_ca$41 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign { \xer_ca_ok$next \xer_ca$10$next } { \xer_ca_ok$42 \xer_ca$41 } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \xer_ca_ok$next 1'0 + end + sync init + update \xer_ca$10 2'00 + update \xer_ca_ok 1'0 + sync posedge \clk + update \xer_ca$10 \xer_ca$10$next + update \xer_ca_ok \xer_ca_ok$next + end + process $group_49 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_50 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end + connect \spr1$33 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \spr1_ok$34 1'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0" +module \alu_spr0 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 3 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 4 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 5 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 6 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 7 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 8 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 9 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 10 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 11 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 12 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 13 \spr1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 output 14 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 input 15 \n_ready_i + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 input 16 \op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 input 17 \op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 input 18 \op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 input 19 \op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 20 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 21 \spr1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 input 22 \fast1$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 input 23 \xer_so$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 input 24 \xer_ov$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 input 25 \xer_ca$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 input 26 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 output 27 \p_ready_o + cell \p$58 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n$59 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" + wire width 1 \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" + wire width 1 \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_muxid + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 \pipe_op__insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 \pipe_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 \pipe_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 \pipe_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \pipe_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 \pipe_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 \pipe_xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" + wire width 1 \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" + wire width 1 \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pipe_muxid$6 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 \pipe_op__insn_type$7 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 \pipe_op__fn_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 \pipe_op__insn$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 \pipe_op__is_32bit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \pipe_spr1$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \pipe_spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \pipe_xer_so$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \pipe_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \pipe_xer_ov$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \pipe_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \pipe_xer_ca$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \pipe_xer_ca_ok + cell \pipe$60 \pipe + connect \rst \rst + connect \clk \clk + connect \p_valid_i \pipe_p_valid_i + connect \p_ready_o \pipe_p_ready_o + connect \muxid \pipe_muxid + connect \op__insn_type \pipe_op__insn_type + connect \op__fn_unit \pipe_op__fn_unit + connect \op__insn \pipe_op__insn + connect \op__is_32bit \pipe_op__is_32bit + connect \ra \pipe_ra + connect \spr1 \pipe_spr1 + connect \fast1 \pipe_fast1 + connect \xer_so \pipe_xer_so + connect \xer_ov \pipe_xer_ov + connect \xer_ca \pipe_xer_ca + connect \n_valid_o \pipe_n_valid_o + connect \n_ready_i \pipe_n_ready_i + connect \muxid$1 \pipe_muxid$6 + connect \op__insn_type$2 \pipe_op__insn_type$7 + connect \op__fn_unit$3 \pipe_op__fn_unit$8 + connect \op__insn$4 \pipe_op__insn$9 + connect \op__is_32bit$5 \pipe_op__is_32bit$10 + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \spr1$6 \pipe_spr1$11 + connect \spr1_ok \pipe_spr1_ok + connect \fast1$7 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \xer_so$8 \pipe_xer_so$13 + connect \xer_so_ok \pipe_xer_so_ok + connect \xer_ov$9 \pipe_xer_ov$14 + connect \xer_ov_ok \pipe_xer_ov_ok + connect \xer_ca$10 \pipe_xer_ca$15 + connect \xer_ca_ok \pipe_xer_ca_ok + end + process $group_0 + assign \pipe_p_valid_i 1'0 + assign \pipe_p_valid_i \p_valid_i + sync init + end + process $group_1 + assign \p_ready_o 1'0 + assign \p_ready_o \pipe_p_ready_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid + process $group_2 + assign \pipe_muxid 2'00 + assign \pipe_muxid \muxid + sync init + end + process $group_3 + assign \pipe_op__insn_type 7'0000000 + assign \pipe_op__fn_unit 11'00000000000 + assign \pipe_op__insn 32'00000000000000000000000000000000 + assign \pipe_op__is_32bit 1'0 + assign { \pipe_op__is_32bit \pipe_op__insn \pipe_op__fn_unit \pipe_op__insn_type } { \op__is_32bit \op__insn \op__fn_unit \op__insn_type } + sync init + end + process $group_7 + assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_ra \ra + sync init + end + process $group_8 + assign \pipe_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_spr1 \spr1$1 + sync init + end + process $group_9 + assign \pipe_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pipe_fast1 \fast1$2 + sync init + end + process $group_10 + assign \pipe_xer_so 1'0 + assign \pipe_xer_so \xer_so$3 + sync init + end + process $group_11 + assign \pipe_xer_ov 2'00 + assign \pipe_xer_ov \xer_ov$4 + sync init + end + process $group_12 + assign \pipe_xer_ca 2'00 + assign \pipe_xer_ca \xer_ca$5 + sync init + end + process $group_13 + assign \n_valid_o 1'0 + assign \n_valid_o \pipe_n_valid_o + sync init + end + process $group_14 + assign \pipe_n_ready_i 1'0 + assign \pipe_n_ready_i \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$16 + process $group_15 + assign \muxid$16 2'00 + assign \muxid$16 \pipe_muxid$6 + sync init + end + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 \op__insn_type$17 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 \op__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 \op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 \op__is_32bit$20 + process $group_16 + assign \op__insn_type$17 7'0000000 + assign \op__fn_unit$18 11'00000000000 + assign \op__insn$19 32'00000000000000000000000000000000 + assign \op__is_32bit$20 1'0 + assign { \op__is_32bit$20 \op__insn$19 \op__fn_unit$18 \op__insn_type$17 } { \pipe_op__is_32bit$10 \pipe_op__insn$9 \pipe_op__fn_unit$8 \pipe_op__insn_type$7 } + sync init + end + process $group_20 + assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \o_ok 1'0 + assign { \o_ok \o } { \pipe_o_ok \pipe_o } + sync init + end + process $group_22 + assign \spr1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \spr1_ok 1'0 + assign { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } + sync init + end + process $group_24 + assign \fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast1_ok 1'0 + assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + sync init + end + process $group_26 + assign \xer_so 1'0 + assign \xer_so_ok 1'0 + assign { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$13 } + sync init + end + process $group_28 + assign \xer_ov 2'00 + assign \xer_ov_ok 1'0 + assign { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov$14 } + sync init + end + process $group_30 + assign \xer_ca 2'00 + assign \xer_ca_ok 1'0 + assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$15 } + sync init + end + connect \muxid 2'00 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.src_l" +module \src_l$63 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $3 + connect \B \s_src + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \q_int$next 6'000000 + end + sync init + update \q_int 6'000000 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $9 + connect \B \s_src + connect \Y $11 + end + process $group_1 + assign \q_src 6'000000 + assign \q_src $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 6 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \Y $13 + end + process $group_2 + assign \qn_src 6'000000 + assign \qn_src $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 6 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 6 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_src 6'000000 + assign \qlq_src $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.opc_l" +module \opc_l$64 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -77154,54 +84836,54 @@ module \opc_l$51 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l" -module \req_l$52 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.req_l" +module \req_l$65 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 2 \q_req + wire width 6 output 2 \q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req + wire width 6 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req + wire width 6 input 4 \r_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int + wire width 6 \q_int attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next + wire width 6 \q_int$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 + wire width 6 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \r_req connect \Y $1 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 + wire width 6 $3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $and $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_int connect \B $1 connect \Y $3 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 + wire width 6 $5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" cell $or $6 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A $3 connect \B \s_req connect \Y $5 @@ -77212,95 +84894,95 @@ module \req_l$52 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \q_int$next 3'000 + assign \q_int$next 6'000000 end sync init - update \q_int 3'000 + update \q_int 6'000000 sync posedge \clk update \q_int \q_int$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 + wire width 6 $7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $not $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \r_req connect \Y $7 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 + wire width 6 $9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $and $10 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_int connect \B $7 connect \Y $9 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 + wire width 6 $11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" cell $or $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A $9 connect \B \s_req connect \Y $11 end process $group_1 - assign \q_req 3'000 + assign \q_req 6'000000 assign \q_req $11 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req + wire width 6 \qn_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 + wire width 6 $13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" cell $not $14 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_req connect \Y $13 end process $group_2 - assign \qn_req 3'000 + assign \qn_req 6'000000 assign \qn_req $13 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_req + wire width 6 \qlq_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 + wire width 6 $15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" cell $or $16 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \q_req connect \B \q_int connect \Y $15 end process $group_3 - assign \qlq_req 3'000 + assign \qlq_req 6'000000 assign \qlq_req $15 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l" -module \rst_l$53 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rst_l" +module \rst_l$66 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -77444,8 +85126,8 @@ module \rst_l$53 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l" -module \rok_l$54 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rok_l" +module \rok_l$67 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -77589,8 +85271,8 @@ module \rok_l$54 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l" -module \alui_l$55 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alui_l" +module \alui_l$68 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -77734,8 +85416,8 @@ module \alui_l$55 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l" -module \alu_l$56 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_l" +module \alu_l$69 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -77879,8 +85561,8 @@ module \alu_l$56 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0" -module \logical0 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0" +module \spr0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -77957,101 +85639,86 @@ module \logical0 attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" wire width 7 input 2 \oper_i__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 input 3 \oper_i__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 64 input 4 \oper_i__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 5 \oper_i__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 6 \oper_i__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 7 \oper_i__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 8 \oper_i__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 9 \oper_i__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 10 \oper_i__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 11 \oper_i__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 12 \oper_i__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 2 input 13 \oper_i__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 14 \oper_i__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 3 input 15 \oper_i__write_cr__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 16 \oper_i__write_cr__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 17 \oper_i__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 18 \oper_i__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 19 \oper_i__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 4 input 20 \oper_i__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 32 input 21 \oper_i__insn + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 input 3 \oper_i__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 input 4 \oper_i__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 input 5 \oper_i__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 input 22 \issue_i + wire width 1 input 6 \issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 23 \busy_o + wire width 1 output 7 \busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 2 input 24 \rdmaskn + wire width 6 input 8 \rdmaskn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 25 \rd__rel + wire width 6 output 9 \rd__rel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 input 26 \rd__go + wire width 6 input 10 \rd__go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 27 \src1_i + wire width 64 input 11 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 28 \src2_i + wire width 1 input 12 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 2 input 13 \src6_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 2 input 14 \src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 input 15 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 input 16 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 29 \o_ok + wire width 1 output 17 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 30 \wr__rel + wire width 6 output 18 \wr__rel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 31 \wr__go + wire width 6 input 19 \wr__go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 32 \o + wire width 64 output 20 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 33 \cr_a_ok + wire width 1 output 21 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 output 34 \cr_a + wire width 2 output 22 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 35 \xer_ca_ok + wire width 1 output 23 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 output 36 \xer_ca + wire width 2 output 24 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 25 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 26 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 27 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 28 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 29 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 30 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 37 \go_die_i + wire width 1 input 31 \go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 38 \shadown_i + wire width 1 input 32 \shadown_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 39 \dest1_o + wire width 64 output 33 \dest1_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" - wire width 1 \alu_logical0_n_valid_o + wire width 1 \alu_spr0_n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" - wire width 1 \alu_logical0_n_ready_i + wire width 1 \alu_spr0_n_ready_i attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -78124,116 +85791,83 @@ module \logical0 attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 7 \alu_logical0_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 \alu_spr0_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \alu_logical0_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 64 \alu_logical0_op__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_logical0_op__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_logical0_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_logical0_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_logical0_op__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_logical0_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_logical0_op__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_logical0_op__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_logical0_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 2 \alu_logical0_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_logical0_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 3 \alu_logical0_op__write_cr__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_logical0_op__write_cr__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_logical0_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_logical0_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \alu_logical0_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 4 \alu_logical0_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 32 \alu_logical0_op__insn + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 \alu_spr0_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 \alu_spr0_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 \alu_spr0_op__is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_logical0_ra + wire width 64 \alu_spr0_ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" - wire width 64 \alu_logical0_rb + wire width 64 \alu_spr0_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 64 \alu_spr0_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 1 \alu_spr0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 \alu_spr0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" + wire width 2 \alu_spr0_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" - wire width 1 \alu_logical0_p_valid_i + wire width 1 \alu_spr0_p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" - wire width 1 \alu_logical0_p_ready_o - cell \alu_logical0 \alu_logical0 + wire width 1 \alu_spr0_p_ready_o + cell \alu_spr0 \alu_spr0 connect \rst \rst connect \clk \clk connect \o_ok \o_ok connect \o \o - connect \cr_a_ok \cr_a_ok - connect \cr_a \cr_a connect \xer_ca_ok \xer_ca_ok connect \xer_ca \xer_ca - connect \n_valid_o \alu_logical0_n_valid_o - connect \n_ready_i \alu_logical0_n_ready_i - connect \op__insn_type \alu_logical0_op__insn_type - connect \op__fn_unit \alu_logical0_op__fn_unit - connect \op__imm_data__imm \alu_logical0_op__imm_data__imm - connect \op__imm_data__imm_ok \alu_logical0_op__imm_data__imm_ok - connect \op__lk \alu_logical0_op__lk - connect \op__rc__rc \alu_logical0_op__rc__rc - connect \op__rc__rc_ok \alu_logical0_op__rc__rc_ok - connect \op__oe__oe \alu_logical0_op__oe__oe - connect \op__oe__oe_ok \alu_logical0_op__oe__oe_ok - connect \op__invert_a \alu_logical0_op__invert_a - connect \op__zero_a \alu_logical0_op__zero_a - connect \op__input_carry \alu_logical0_op__input_carry - connect \op__invert_out \alu_logical0_op__invert_out - connect \op__write_cr__data \alu_logical0_op__write_cr__data - connect \op__write_cr__ok \alu_logical0_op__write_cr__ok - connect \op__output_carry \alu_logical0_op__output_carry - connect \op__is_32bit \alu_logical0_op__is_32bit - connect \op__is_signed \alu_logical0_op__is_signed - connect \op__data_len \alu_logical0_op__data_len - connect \op__insn \alu_logical0_op__insn - connect \ra \alu_logical0_ra - connect \rb \alu_logical0_rb - connect \p_valid_i \alu_logical0_p_valid_i - connect \p_ready_o \alu_logical0_p_ready_o + connect \xer_ov_ok \xer_ov_ok + connect \xer_ov \xer_ov + connect \xer_so_ok \xer_so_ok + connect \xer_so \xer_so + connect \fast1_ok \fast1_ok + connect \fast1 \fast1 + connect \spr1_ok \spr1_ok + connect \spr1 \spr1 + connect \n_valid_o \alu_spr0_n_valid_o + connect \n_ready_i \alu_spr0_n_ready_i + connect \op__insn_type \alu_spr0_op__insn_type + connect \op__fn_unit \alu_spr0_op__fn_unit + connect \op__insn \alu_spr0_op__insn + connect \op__is_32bit \alu_spr0_op__is_32bit + connect \ra \alu_spr0_ra + connect \spr1$1 \alu_spr0_spr1 + connect \fast1$2 \alu_spr0_fast1 + connect \xer_so$3 \alu_spr0_xer_so + connect \xer_ov$4 \alu_spr0_xer_ov + connect \xer_ca$5 \alu_spr0_xer_ca + connect \p_valid_i \alu_spr0_p_valid_i + connect \p_ready_o \alu_spr0_p_ready_o end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 \src_l_s_src + wire width 6 \src_l_s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 \src_l_s_src$next + wire width 6 \src_l_s_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 \src_l_r_src + wire width 6 \src_l_r_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 \src_l_r_src$next + wire width 6 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 2 \src_l_q_src - cell \src_l$50 \src_l + wire width 6 \src_l_q_src + cell \src_l$63 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src @@ -78250,7 +85884,7 @@ module \logical0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$51 \opc_l + cell \opc_l$64 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc @@ -78258,12 +85892,12 @@ module \logical0 connect \q_opc \opc_l_q_opc end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \req_l_q_req + wire width 6 \req_l_q_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req + wire width 6 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req - cell \req_l$52 \req_l + wire width 6 \req_l_r_req + cell \req_l$65 \req_l connect \rst \rst connect \clk \clk connect \q_req \req_l_q_req @@ -78274,7 +85908,7 @@ module \logical0 wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst - cell \rst_l$53 \rst_l + cell \rst_l$66 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst @@ -78288,7 +85922,7 @@ module \logical0 wire width 1 \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$54 \rok_l + cell \rok_l$67 \rok_l connect \rst \rst connect \clk \clk connect \q_rdok \rok_l_q_rdok @@ -78303,7 +85937,7 @@ module \logical0 wire width 1 \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$55 \alui_l + cell \alui_l$68 \alui_l connect \rst \rst connect \clk \clk connect \q_alui \alui_l_q_alui @@ -78318,7 +85952,7 @@ module \logical0 wire width 1 \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$56 \alu_l + cell \alu_l$69 \alu_l connect \rst \rst connect \clk \clk connect \q_alu \alu_l_q_alu @@ -78343,24 +85977,24 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" wire width 1 $3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" - wire width 2 $4 + wire width 6 $4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $not $5 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \rd__rel connect \Y $4 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" - wire width 2 $6 + wire width 6 $6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $or $7 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A $4 connect \B \rd__go connect \Y $6 @@ -78368,7 +86002,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180" cell $reduce_and $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A $6 connect \Y $3 @@ -78437,7 +86071,7 @@ module \logical0 wire width 1 \alu_done process $group_3 assign \alu_done 1'0 - assign \alu_done \alu_logical0_n_valid_o + assign \alu_done \alu_spr0_n_valid_o sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190" @@ -78483,27 +86117,27 @@ module \logical0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 3 \alu_pulsem + wire width 6 \alu_pulsem process $group_6 - assign \alu_pulsem 3'000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + assign \alu_pulsem 6'000000 + assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" - wire width 3 \prev_wr_go + wire width 6 \prev_wr_go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199" - wire width 3 \prev_wr_go$next + wire width 6 \prev_wr_go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" - wire width 3 $19 + wire width 6 $19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201" cell $and $20 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \wr__go - connect \B { \busy_o \busy_o \busy_o } + connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o \busy_o } connect \Y $19 end process $group_7 @@ -78512,10 +86146,10 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \prev_wr_go$next 3'000 + assign \prev_wr_go$next 6'000000 end sync init - update \prev_wr_go 3'000 + update \prev_wr_go 6'000000 sync posedge \clk update \prev_wr_go \prev_wr_go$next end @@ -78526,26 +86160,26 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" wire width 1 $22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - wire width 3 $23 + wire width 6 $23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93" - wire width 3 \wrmask + wire width 6 \wrmask attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $not $24 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \wrmask connect \Y $23 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" - wire width 3 $25 + wire width 6 $25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $and $26 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \wr__rel connect \B $23 connect \Y $25 @@ -78553,7 +86187,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209" cell $reduce_bool $27 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A $25 connect \Y $22 @@ -78591,7 +86225,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $32 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \wr__go connect \Y $31 @@ -78601,7 +86235,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210" cell $reduce_bool $34 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \prev_wr_go connect \Y $33 @@ -78633,7 +86267,7 @@ module \logical0 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_logical0_n_ready_i + connect \A \alu_spr0_n_ready_i connect \Y $37 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" @@ -78650,14 +86284,14 @@ module \logical0 connect \Y $39 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire width 3 $41 + wire width 6 $41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $and $42 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B \wrmask connect \Y $41 @@ -78667,7 +86301,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" cell $eq $44 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 @@ -78693,7 +86327,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" cell $eq $48 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 @@ -78711,7 +86345,7 @@ module \logical0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $47 - connect \B \alu_logical0_n_ready_i + connect \B \alu_spr0_n_ready_i connect \Y $49 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" @@ -78724,7 +86358,7 @@ module \logical0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $49 - connect \B \alu_logical0_n_valid_o + connect \B \alu_spr0_n_valid_o connect \Y $51 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" @@ -78792,42 +86426,42 @@ module \logical0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223" - wire width 3 \reset_w + wire width 6 \reset_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire width 3 $59 + wire width 6 $59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" cell $or $60 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \wr__go - connect \B { \go_die_i \go_die_i \go_die_i } + connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i } connect \Y $59 end process $group_13 - assign \reset_w 3'000 + assign \reset_w 6'000000 assign \reset_w $59 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224" - wire width 2 \reset_r + wire width 6 \reset_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 2 $61 + wire width 6 $61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" cell $or $62 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \rd__go - connect \B { \go_die_i \go_die_i } + connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i } connect \Y $61 end process $group_14 - assign \reset_r 2'00 + assign \reset_r 6'000000 assign \reset_r $61 sync init end @@ -78845,7 +86479,7 @@ module \logical0 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_logical0_n_valid_o + connect \A \alu_spr0_n_valid_o connect \B \busy_o connect \Y $63 end @@ -78900,14 +86534,14 @@ module \logical0 end process $group_21 assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \issue_i \issue_i } + assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i } attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \src_l_s_src$next 2'00 + assign \src_l_s_src$next 6'000000 end sync init - update \src_l_s_src 2'00 + update \src_l_s_src 6'000000 sync posedge \clk update \src_l_s_src \src_l_s_src$next end @@ -78917,46 +86551,46 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \src_l_r_src$next 2'11 + assign \src_l_r_src$next 6'111111 end sync init - update \src_l_r_src 2'11 + update \src_l_r_src 6'111111 sync posedge \clk update \src_l_r_src \src_l_r_src$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" - wire width 3 $65 + wire width 6 $65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247" cell $and $66 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \alu_pulsem connect \B \wrmask connect \Y $65 end process $group_23 - assign \req_l_s_req 3'000 + assign \req_l_s_req 6'000000 assign \req_l_s_req $65 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" - wire width 3 $67 + wire width 6 $67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248" cell $or $68 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \reset_w connect \B \prev_wr_go connect \Y $67 end process $group_24 - assign \req_l_r_req 3'111 + assign \req_l_r_req 6'111111 assign \req_l_r_req $67 sync init end @@ -79032,257 +86666,81 @@ module \logical0 attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" wire width 7 \oper_r__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 \oper_r__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 64 \oper_r__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \oper_r__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \oper_r__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \oper_r__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \oper_r__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \oper_r__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \oper_r__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \oper_r__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \oper_r__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 2 \oper_r__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \oper_r__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 3 \oper_r__write_cr__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \oper_r__write_cr__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \oper_r__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \oper_r__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \oper_r__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 4 \oper_r__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 \oper_r__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" wire width 32 \oper_r__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 \oper_r__is_32bit attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 7 \oper_l__insn_type attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 7 \oper_l__insn_type$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 10 \oper_l__fn_unit - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 10 \oper_l__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 64 \oper_l__imm_data__imm$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__imm_data__imm_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__lk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__lk$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__rc__rc_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__oe__oe_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__zero_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \oper_l__input_carry + wire width 11 \oper_l__fn_unit attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \oper_l__input_carry$next + wire width 11 \oper_l__fn_unit$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_out - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__invert_out$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 3 \oper_l__write_cr__data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 3 \oper_l__write_cr__data$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__write_cr__ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__write_cr__ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__output_carry + wire width 32 \oper_l__insn attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__output_carry$next + wire width 32 \oper_l__insn$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \oper_l__is_32bit attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 1 \oper_l__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \oper_l__is_signed$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \oper_l__data_len - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \oper_l__data_len$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 32 \oper_l__insn$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 135 $69 + wire width 51 $69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" cell $mux $70 - parameter \WIDTH 135 - connect \A { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } \oper_l__invert_out \oper_l__input_carry \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } - connect \B { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } + parameter \WIDTH 51 + connect \A { \oper_l__is_32bit \oper_l__insn \oper_l__fn_unit \oper_l__insn_type } + connect \B { \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type } connect \S \issue_i connect \Y $69 end process $group_25 assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 10'0000000000 - assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_r__imm_data__imm_ok 1'0 - assign \oper_r__lk 1'0 - assign \oper_r__rc__rc 1'0 - assign \oper_r__rc__rc_ok 1'0 - assign \oper_r__oe__oe 1'0 - assign \oper_r__oe__oe_ok 1'0 - assign \oper_r__invert_a 1'0 - assign \oper_r__zero_a 1'0 - assign \oper_r__input_carry 2'00 - assign \oper_r__invert_out 1'0 - assign \oper_r__write_cr__data 3'000 - assign \oper_r__write_cr__ok 1'0 - assign \oper_r__output_carry 1'0 - assign \oper_r__is_32bit 1'0 - assign \oper_r__is_signed 1'0 - assign \oper_r__data_len 4'0000 + assign \oper_r__fn_unit 11'00000000000 assign \oper_r__insn 32'00000000000000000000000000000000 - assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $69 + assign \oper_r__is_32bit 1'0 + assign { \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } $69 sync init end - process $group_45 + process $group_29 assign \oper_l__insn_type$next \oper_l__insn_type assign \oper_l__fn_unit$next \oper_l__fn_unit - assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm - assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok - assign \oper_l__lk$next \oper_l__lk - assign \oper_l__rc__rc$next \oper_l__rc__rc - assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok - assign \oper_l__oe__oe$next \oper_l__oe__oe - assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok - assign \oper_l__invert_a$next \oper_l__invert_a - assign \oper_l__zero_a$next \oper_l__zero_a - assign \oper_l__input_carry$next \oper_l__input_carry - assign \oper_l__invert_out$next \oper_l__invert_out - assign \oper_l__write_cr__data$next \oper_l__write_cr__data - assign \oper_l__write_cr__ok$next \oper_l__write_cr__ok - assign \oper_l__output_carry$next \oper_l__output_carry - assign \oper_l__is_32bit$next \oper_l__is_32bit - assign \oper_l__is_signed$next \oper_l__is_signed - assign \oper_l__data_len$next \oper_l__data_len assign \oper_l__insn$next \oper_l__insn + assign \oper_l__is_32bit$next \oper_l__is_32bit attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { \issue_i } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_l__imm_data__imm_ok$next 1'0 - assign \oper_l__rc__rc$next 1'0 - assign \oper_l__rc__rc_ok$next 1'0 - assign \oper_l__oe__oe$next 1'0 - assign \oper_l__oe__oe_ok$next 1'0 - assign \oper_l__write_cr__data$next 3'000 - assign \oper_l__write_cr__ok$next 1'0 - assign \oper_l__insn$next 32'00000000000000000000000000000000 + assign { \oper_l__is_32bit$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type } end sync init update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 10'0000000000 - update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_l__imm_data__imm_ok 1'0 - update \oper_l__lk 1'0 - update \oper_l__rc__rc 1'0 - update \oper_l__rc__rc_ok 1'0 - update \oper_l__oe__oe 1'0 - update \oper_l__oe__oe_ok 1'0 - update \oper_l__invert_a 1'0 - update \oper_l__zero_a 1'0 - update \oper_l__input_carry 2'00 - update \oper_l__invert_out 1'0 - update \oper_l__write_cr__data 3'000 - update \oper_l__write_cr__ok 1'0 - update \oper_l__output_carry 1'0 - update \oper_l__is_32bit 1'0 - update \oper_l__is_signed 1'0 - update \oper_l__data_len 4'0000 + update \oper_l__fn_unit 11'00000000000 update \oper_l__insn 32'00000000000000000000000000000000 + update \oper_l__is_32bit 1'0 sync posedge \clk update \oper_l__insn_type \oper_l__insn_type$next update \oper_l__fn_unit \oper_l__fn_unit$next - update \oper_l__imm_data__imm \oper_l__imm_data__imm$next - update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next - update \oper_l__lk \oper_l__lk$next - update \oper_l__rc__rc \oper_l__rc__rc$next - update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next - update \oper_l__oe__oe \oper_l__oe__oe$next - update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next - update \oper_l__invert_a \oper_l__invert_a$next - update \oper_l__zero_a \oper_l__zero_a$next - update \oper_l__input_carry \oper_l__input_carry$next - update \oper_l__invert_out \oper_l__invert_out$next - update \oper_l__write_cr__data \oper_l__write_cr__data$next - update \oper_l__write_cr__ok \oper_l__write_cr__ok$next - update \oper_l__output_carry \oper_l__output_carry$next - update \oper_l__is_32bit \oper_l__is_32bit$next - update \oper_l__is_signed \oper_l__is_signed$next - update \oper_l__data_len \oper_l__data_len$next update \oper_l__insn \oper_l__insn$next + update \oper_l__is_32bit \oper_l__is_32bit$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" wire width 64 \data_r0__o @@ -79303,7 +86761,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" cell $reduce_bool $73 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \alu_pulsem connect \Y $72 @@ -79316,7 +86774,7 @@ module \logical0 connect \S $72 connect \Y $71 end - process $group_65 + process $group_33 assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 assign \data_r0__o_ok 1'0 assign { \data_r0__o_ok \data_r0__o } $71 @@ -79327,12 +86785,12 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" cell $reduce_bool $76 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \alu_pulsem connect \Y $75 end - process $group_67 + process $group_35 assign \data_r0_l__o$next \data_r0_l__o assign \data_r0_l__o_ok$next \data_r0_l__o_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" @@ -79354,41 +86812,41 @@ module \logical0 update \data_r0_l__o_ok \data_r0_l__o_ok$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" - wire width 4 \data_r1__cr_a + wire width 64 \data_r1__spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" - wire width 1 \data_r1__cr_a_ok + wire width 1 \data_r1__spr1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r1_l__cr_a + wire width 64 \data_r1_l__spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 4 \data_r1_l__cr_a$next + wire width 64 \data_r1_l__spr1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__cr_a_ok + wire width 1 \data_r1_l__spr1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r1_l__cr_a_ok$next + wire width 1 \data_r1_l__spr1_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 5 $77 + wire width 65 $77 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" wire width 1 $78 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" cell $reduce_bool $79 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \alu_pulsem connect \Y $78 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" cell $mux $80 - parameter \WIDTH 5 - connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a } - connect \B { \cr_a_ok \cr_a } + parameter \WIDTH 65 + connect \A { \data_r1_l__spr1_ok \data_r1_l__spr1 } + connect \B { \spr1_ok \spr1 } connect \S $78 connect \Y $77 end - process $group_69 - assign \data_r1__cr_a 4'0000 - assign \data_r1__cr_a_ok 1'0 - assign { \data_r1__cr_a_ok \data_r1__cr_a } $77 + process $group_37 + assign \data_r1__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r1__spr1_ok 1'0 + assign { \data_r1__spr1_ok \data_r1__spr1 } $77 sync init end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" @@ -79396,68 +86854,68 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" cell $reduce_bool $82 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \alu_pulsem connect \Y $81 end - process $group_71 - assign \data_r1_l__cr_a$next \data_r1_l__cr_a - assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok + process $group_39 + assign \data_r1_l__spr1$next \data_r1_l__spr1 + assign \data_r1_l__spr1_ok$next \data_r1_l__spr1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { $81 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \cr_a } + assign { \data_r1_l__spr1_ok$next \data_r1_l__spr1$next } { \spr1_ok \spr1 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \data_r1_l__cr_a_ok$next 1'0 + assign \data_r1_l__spr1_ok$next 1'0 end sync init - update \data_r1_l__cr_a 4'0000 - update \data_r1_l__cr_a_ok 1'0 + update \data_r1_l__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r1_l__spr1_ok 1'0 sync posedge \clk - update \data_r1_l__cr_a \data_r1_l__cr_a$next - update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next + update \data_r1_l__spr1 \data_r1_l__spr1$next + update \data_r1_l__spr1_ok \data_r1_l__spr1_ok$next end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" - wire width 2 \data_r2__xer_ca + wire width 64 \data_r2__fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" - wire width 1 \data_r2__xer_ca_ok + wire width 1 \data_r2__fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r2_l__xer_ca + wire width 64 \data_r2_l__fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 2 \data_r2_l__xer_ca$next + wire width 64 \data_r2_l__fast1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__xer_ca_ok + wire width 1 \data_r2_l__fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 1 \data_r2_l__xer_ca_ok$next + wire width 1 \data_r2_l__fast1_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 3 $83 + wire width 65 $83 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" wire width 1 $84 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" cell $reduce_bool $85 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \alu_pulsem connect \Y $84 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" cell $mux $86 - parameter \WIDTH 3 - connect \A { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca } - connect \B { \xer_ca_ok \xer_ca } + parameter \WIDTH 65 + connect \A { \data_r2_l__fast1_ok \data_r2_l__fast1 } + connect \B { \fast1_ok \fast1 } connect \S $84 connect \Y $83 end - process $group_73 - assign \data_r2__xer_ca 2'00 - assign \data_r2__xer_ca_ok 1'0 - assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $83 + process $group_41 + assign \data_r2__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \data_r2__fast1_ok 1'0 + assign { \data_r2__fast1_ok \data_r2__fast1 } $83 sync init end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" @@ -79465,127 +86923,250 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" cell $reduce_bool $88 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \alu_pulsem connect \Y $87 end - process $group_75 - assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca - assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok + process $group_43 + assign \data_r2_l__fast1$next \data_r2_l__fast1 + assign \data_r2_l__fast1_ok$next \data_r2_l__fast1_ok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" switch { $87 } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \xer_ca } + assign { \data_r2_l__fast1_ok$next \data_r2_l__fast1$next } { \fast1_ok \fast1 } end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \data_r2_l__xer_ca_ok$next 1'0 + assign \data_r2_l__fast1_ok$next 1'0 end sync init - update \data_r2_l__xer_ca 2'00 - update \data_r2_l__xer_ca_ok 1'0 + update \data_r2_l__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + update \data_r2_l__fast1_ok 1'0 sync posedge \clk - update \data_r2_l__xer_ca \data_r2_l__xer_ca$next - update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next + update \data_r2_l__fast1 \data_r2_l__fast1$next + update \data_r2_l__fast1_ok \data_r2_l__fast1_ok$next end - process $group_77 - assign \wrmask 3'000 - assign \wrmask { \data_r2__xer_ca_ok \data_r1__cr_a_ok \data_r0__o_ok } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r3_l__xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r3_l__xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r3_l__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r3_l__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 $89 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $90 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $91 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $90 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $92 + parameter \WIDTH 2 + connect \A { \data_r3_l__xer_so_ok \data_r3_l__xer_so } + connect \B { \xer_so_ok \xer_so } + connect \S $90 + connect \Y $89 + end + process $group_45 + assign \data_r3__xer_so 1'0 + assign \data_r3__xer_so_ok 1'0 + assign { \data_r3__xer_so_ok \data_r3__xer_so } $89 sync init end - process $group_78 - assign \alu_logical0_op__insn_type 7'0000000 - assign \alu_logical0_op__fn_unit 10'0000000000 - assign \alu_logical0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_logical0_op__imm_data__imm_ok 1'0 - assign \alu_logical0_op__lk 1'0 - assign \alu_logical0_op__rc__rc 1'0 - assign \alu_logical0_op__rc__rc_ok 1'0 - assign \alu_logical0_op__oe__oe 1'0 - assign \alu_logical0_op__oe__oe_ok 1'0 - assign \alu_logical0_op__invert_a 1'0 - assign \alu_logical0_op__zero_a 1'0 - assign \alu_logical0_op__input_carry 2'00 - assign \alu_logical0_op__invert_out 1'0 - assign \alu_logical0_op__write_cr__data 3'000 - assign \alu_logical0_op__write_cr__ok 1'0 - assign \alu_logical0_op__output_carry 1'0 - assign \alu_logical0_op__is_32bit 1'0 - assign \alu_logical0_op__is_signed 1'0 - assign \alu_logical0_op__data_len 4'0000 - assign \alu_logical0_op__insn 32'00000000000000000000000000000000 - assign { \alu_logical0_op__insn \alu_logical0_op__data_len \alu_logical0_op__is_signed \alu_logical0_op__is_32bit \alu_logical0_op__output_carry { \alu_logical0_op__write_cr__ok \alu_logical0_op__write_cr__data } \alu_logical0_op__invert_out \alu_logical0_op__input_carry \alu_logical0_op__zero_a \alu_logical0_op__invert_a { \alu_logical0_op__oe__oe_ok \alu_logical0_op__oe__oe } { \alu_logical0_op__rc__rc_ok \alu_logical0_op__rc__rc } \alu_logical0_op__lk { \alu_logical0_op__imm_data__imm_ok \alu_logical0_op__imm_data__imm } \alu_logical0_op__fn_unit \alu_logical0_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $93 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $93 + end + process $group_47 + assign \data_r3_l__xer_so$next \data_r3_l__xer_so + assign \data_r3_l__xer_so_ok$next \data_r3_l__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $93 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign { \data_r3_l__xer_so_ok$next \data_r3_l__xer_so$next } { \xer_so_ok \xer_so } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \data_r3_l__xer_so_ok$next 1'0 + end sync init + update \data_r3_l__xer_so 1'0 + update \data_r3_l__xer_so_ok 1'0 + sync posedge \clk + update \data_r3_l__xer_so \data_r3_l__xer_so$next + update \data_r3_l__xer_so_ok \data_r3_l__xer_so_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - cell $mux $90 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \oper_r__zero_a - connect \Y $89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 2 \data_r4__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r4__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r4_l__xer_ov + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r4_l__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r4_l__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r4_l__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 3 $95 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $96 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $96 end - process $group_98 - assign \src_sel 1'0 - assign \src_sel $89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $98 + parameter \WIDTH 3 + connect \A { \data_r4_l__xer_ov_ok \data_r4_l__xer_ov } + connect \B { \xer_ov_ok \xer_ov } + connect \S $96 + connect \Y $95 + end + process $group_49 + assign \data_r4__xer_ov 2'00 + assign \data_r4__xer_ov_ok 1'0 + assign { \data_r4__xer_ov_ok \data_r4__xer_ov } $95 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" - wire width 64 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" - cell $mux $92 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \oper_r__zero_a - connect \Y $91 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $99 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $99 end - process $group_99 - assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $91 + process $group_51 + assign \data_r4_l__xer_ov$next \data_r4_l__xer_ov + assign \data_r4_l__xer_ov_ok$next \data_r4_l__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $99 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign { \data_r4_l__xer_ov_ok$next \data_r4_l__xer_ov$next } { \xer_ov_ok \xer_ov } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \data_r4_l__xer_ov_ok$next 1'0 + end sync init + update \data_r4_l__xer_ov 2'00 + update \data_r4_l__xer_ov_ok 1'0 + sync posedge \clk + update \data_r4_l__xer_ov \data_r4_l__xer_ov$next + update \data_r4_l__xer_ov_ok \data_r4_l__xer_ov_ok$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158" - wire width 1 \src_sel$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - wire width 1 $94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159" - cell $mux $95 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \oper_r__imm_data__imm_ok - connect \Y $94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 2 \data_r5__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262" + wire width 1 \data_r5__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r5_l__xer_ca + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 2 \data_r5_l__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r5_l__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" + wire width 1 \data_r5_l__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 3 $101 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + wire width 1 $102 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730" + cell $reduce_bool $103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $102 end - process $group_100 - assign \src_sel$93 1'0 - assign \src_sel$93 $94 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $104 + parameter \WIDTH 3 + connect \A { \data_r5_l__xer_ca_ok \data_r5_l__xer_ca } + connect \B { \xer_ca_ok \xer_ca } + connect \S $102 + connect \Y $101 + end + process $group_53 + assign \data_r5__xer_ca 2'00 + assign \data_r5__xer_ca_ok 1'0 + assign { \data_r5__xer_ca_ok \data_r5__xer_ca } $101 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157" - wire width 64 \src_or_imm$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" - wire width 64 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160" - cell $mux $98 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \oper_r__imm_data__imm - connect \S \oper_r__imm_data__imm_ok - connect \Y $97 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + wire width 1 $105 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" + cell $reduce_bool $106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \alu_pulsem + connect \Y $105 end - process $group_101 - assign \src_or_imm$96 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm$96 $97 + process $group_55 + assign \data_r5_l__xer_ca$next \data_r5_l__xer_ca + assign \data_r5_l__xer_ca_ok$next \data_r5_l__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { $105 } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign { \data_r5_l__xer_ca_ok$next \data_r5_l__xer_ca$next } { \xer_ca_ok \xer_ca } + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \data_r5_l__xer_ca_ok$next 1'0 + end + sync init + update \data_r5_l__xer_ca 2'00 + update \data_r5_l__xer_ca_ok 1'0 + sync posedge \clk + update \data_r5_l__xer_ca \data_r5_l__xer_ca$next + update \data_r5_l__xer_ca_ok \data_r5_l__xer_ca_ok$next + end + process $group_57 + assign \wrmask 6'000000 + assign \wrmask { \data_r5__xer_ca_ok \data_r4__xer_ov_ok \data_r3__xer_so_ok \data_r2__fast1_ok \data_r1__spr1_ok \data_r0__o_ok } + sync init + end + process $group_58 + assign \alu_spr0_op__insn_type 7'0000000 + assign \alu_spr0_op__fn_unit 11'00000000000 + assign \alu_spr0_op__insn 32'00000000000000000000000000000000 + assign \alu_spr0_op__is_32bit 1'0 + assign { \alu_spr0_op__is_32bit \alu_spr0_op__insn \alu_spr0_op__fn_unit \alu_spr0_op__insn_type } { \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" @@ -79593,27 +87174,27 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r0$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $99 + wire width 64 $107 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $100 + cell $mux $108 parameter \WIDTH 64 connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $99 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $107 end - process $group_102 - assign \alu_logical0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_logical0_ra $99 + process $group_62 + assign \alu_spr0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_spr0_ra $107 sync init end - process $group_103 + process $group_63 assign \src_r0$next \src_r0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel } + switch { \src_l_q_src [0] } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign \src_r0$next \src_or_imm + assign \src_r0$next \src1_i end sync init update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -79625,54 +87206,182 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" wire width 64 \src_r1$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $101 + wire width 64 $109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $102 + cell $mux $110 parameter \WIDTH 64 connect \A \src_r1 - connect \B \src_or_imm$96 - connect \S \src_sel$93 - connect \Y $101 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $109 end - process $group_104 - assign \alu_logical0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_logical0_rb $101 + process $group_64 + assign \alu_spr0_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_spr0_spr1 $109 sync init end - process $group_105 + process $group_65 assign \src_r1$next \src_r1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel$93 } + switch { \src_l_q_src [1] } attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" case 1'1 - assign \src_r1$next \src_or_imm$96 + assign \src_r1$next \src2_i end sync init update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk update \src_r1 \src_r1$next end - process $group_106 - assign \alu_logical0_p_valid_i 1'0 - assign \alu_logical0_p_valid_i \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 64 $111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $112 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $111 + end + process $group_66 + assign \alu_spr0_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_spr0_fast1 $111 + sync init + end + process $group_67 + assign \src_r2$next \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [2] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r2$next \src3_i + end + sync init + update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \src_r2 \src_r2$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 1 \src_r3$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 1 $113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $114 + parameter \WIDTH 1 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $113 + end + process $group_68 + assign \alu_spr0_xer_so 1'0 + assign \alu_spr0_xer_so $113 + sync init + end + process $group_69 + assign \src_r3$next \src_r3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [3] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r3$next \src4_i + end + sync init + update \src_r3 1'0 + sync posedge \clk + update \src_r3 \src_r3$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r4$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 $115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $116 + parameter \WIDTH 2 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $115 + end + process $group_70 + assign \alu_spr0_xer_ov 2'00 + assign \alu_spr0_xer_ov $115 + sync init + end + process $group_71 + assign \src_r4$next \src_r4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [4] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r4$next \src5_i + end + sync init + update \src_r4 2'00 + sync posedge \clk + update \src_r4 \src_r4$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 2 \src_r5$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire width 2 $117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $118 + parameter \WIDTH 2 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $117 + end + process $group_72 + assign \alu_spr0_xer_ca 2'00 + assign \alu_spr0_xer_ca $117 + sync init + end + process $group_73 + assign \src_r5$next \src_r5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch { \src_l_q_src [5] } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + case 1'1 + assign \src_r5$next \src6_i + end + sync init + update \src_r5 2'00 + sync posedge \clk + update \src_r5 \src_r5$next + end + process $group_74 + assign \alu_spr0_p_valid_i 1'0 + assign \alu_spr0_p_valid_i \alui_l_q_alui sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" - wire width 1 $103 + wire width 1 $119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321" - cell $and $104 + cell $and $120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_logical0_p_ready_o + connect \A \alu_spr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $103 + connect \Y $119 end - process $group_107 + process $group_75 assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $103 + assign \alui_l_r_alui$next $119 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -79683,32 +87392,32 @@ module \logical0 sync posedge \clk update \alui_l_r_alui \alui_l_r_alui$next end - process $group_108 + process $group_76 assign \alui_l_s_alui 1'0 assign \alui_l_s_alui \all_rd_pulse sync init end - process $group_109 - assign \alu_logical0_n_ready_i 1'0 - assign \alu_logical0_n_ready_i \alu_l_q_alu + process $group_77 + assign \alu_spr0_n_ready_i 1'0 + assign \alu_spr0_n_ready_i \alu_l_q_alu sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" - wire width 1 $105 + wire width 1 $121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328" - cell $and $106 + cell $and $122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_logical0_n_valid_o + connect \A \alu_spr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $105 + connect \Y $121 end - process $group_110 + process $group_78 assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $105 + assign \alu_l_r_alu$next $121 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -79719,94 +87428,74 @@ module \logical0 sync posedge \clk update \alu_l_r_alu \alu_l_r_alu$next end - process $group_111 + process $group_79 assign \alu_l_s_alu 1'0 assign \alu_l_s_alu \all_rd_pulse sync init end - process $group_112 + process $group_80 assign \busy_o 1'0 assign \busy_o \opc_l_q_opc sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" - wire width 2 $107 + wire width 6 $123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" - cell $and $108 + cell $and $124 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \src_l_q_src - connect \B { \busy_o \busy_o } - connect \Y $107 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" - cell $not $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \oper_r__zero_a - connect \Y $109 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164" - cell $not $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \oper_r__imm_data__imm_ok - connect \Y $111 + connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o \busy_o } + connect \Y $123 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" - wire width 2 $113 + wire width 6 $125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" - cell $and $114 + cell $and $126 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $107 - connect \B { $111 $109 } - connect \Y $113 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $123 + connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 } + connect \Y $125 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" - wire width 2 $115 + wire width 6 $127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" - cell $not $116 + cell $not $128 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \rdmaskn - connect \Y $115 + connect \Y $127 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" - wire width 2 $117 + wire width 6 $129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341" - cell $and $118 + cell $and $130 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $113 - connect \B $115 - connect \Y $117 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $125 + connect \B $127 + connect \Y $129 end - process $group_113 - assign \rd__rel 2'00 - assign \rd__rel $117 + process $group_81 + assign \rd__rel 6'000000 + assign \rd__rel $129 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 1 $119 + wire width 1 $131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $120 + cell $and $132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -79814,12 +87503,12 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $119 + connect \Y $131 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 1 $121 + wire width 1 $133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $122 + cell $and $134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -79827,12 +87516,12 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $121 + connect \Y $133 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - wire width 1 $123 + wire width 1 $135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" - cell $and $124 + cell $and $136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -79840,40 +87529,79 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \busy_o connect \B \shadown_i - connect \Y $123 + connect \Y $135 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B \shadown_i + connect \Y $137 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B \shadown_i + connect \Y $139 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + wire width 1 $141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344" + cell $and $142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_o + connect \B \shadown_i + connect \Y $141 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" - wire width 3 $125 + wire width 6 $143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" - cell $and $126 + cell $and $144 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 connect \A \req_l_q_req - connect \B { $119 $121 $123 } - connect \Y $125 + connect \B { $131 $133 $135 $137 $139 $141 } + connect \Y $143 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" - wire width 3 $127 + wire width 6 $145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345" - cell $and $128 + cell $and $146 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $125 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $143 connect \B \wrmask - connect \Y $127 + connect \Y $145 end - process $group_114 - assign \wr__rel 3'000 - assign \wr__rel $127 + process $group_82 + assign \wr__rel 6'000000 + assign \wr__rel $145 sync init end - process $group_115 + process $group_83 assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [0] } @@ -79884,33 +87612,69 @@ module \logical0 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 4 \dest2_o - process $group_116 - assign \dest2_o 4'0000 + wire width 64 \dest2_o + process $group_84 + assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [1] } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 - assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] + assign \dest2_o { \data_r1__spr1_ok \data_r1__spr1 } [63:0] end sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 2 \dest3_o - process $group_117 - assign \dest3_o 2'00 + wire width 64 \dest3_o + process $group_85 + assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" switch { \wr__go [2] } attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" case 1'1 - assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] + assign \dest3_o { \data_r2__fast1_ok \data_r2__fast1 } [63:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 1 \dest4_o + process $group_86 + assign \dest4_o 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" + switch { \wr__go [3] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" + case 1'1 + assign \dest4_o { \data_r3__xer_so_ok \data_r3__xer_so } [0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 2 \dest5_o + process $group_87 + assign \dest5_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" + switch { \wr__go [4] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" + case 1'1 + assign \dest5_o { \data_r4__xer_ov_ok \data_r4__xer_ov } [1:0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 2 \dest6_o + process $group_88 + assign \dest6_o 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" + switch { \wr__go [5] } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349" + case 1'1 + assign \dest6_o { \data_r5__xer_ca_ok \data_r5__xer_ca } [1:0] end sync init end end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p" -module \p$57 +module \p$70 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -79938,7 +87702,7 @@ module \p$57 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.n" -module \n$58 +module \n$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -79966,7 +87730,7 @@ module \n$58 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.p" -module \p$60 +module \p$73 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151" wire width 1 input 0 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" @@ -79994,7 +87758,7 @@ module \p$60 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.n" -module \n$61 +module \n$74 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244" wire width 1 input 0 \n_valid_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245" @@ -80022,7 +87786,7 @@ module \n$61 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.input" -module \input$62 +module \input$75 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -80100,18 +87864,19 @@ module \input$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 input 1 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 input 2 \op__fn_unit + wire width 11 input 2 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 input 3 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -80231,18 +87996,19 @@ module \input$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 output 23 \op__insn_type$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 output 24 \op__fn_unit$3 + wire width 11 output 24 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 output 25 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -80323,7 +88089,7 @@ module \input$62 end process $group_4 assign \op__insn_type$2 7'0000000 - assign \op__fn_unit$3 10'0000000000 + assign \op__fn_unit$3 11'00000000000 assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$5 1'0 assign \op__rc__rc$6 1'0 @@ -81190,7 +88956,7 @@ module \rotator end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main" -module \main$63 +module \main$76 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -81268,18 +89034,19 @@ module \main$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 input 1 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 input 2 \op__fn_unit + wire width 11 input 2 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 input 3 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -81397,18 +89164,19 @@ module \main$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 output 22 \op__insn_type$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 output 23 \op__fn_unit$3 + wire width 11 output 23 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 output 24 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -81645,7 +89413,7 @@ module \main$63 end process $group_20 assign \op__insn_type$2 7'0000000 - assign \op__fn_unit$3 10'0000000000 + assign \op__fn_unit$3 11'00000000000 assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$5 1'0 assign \op__rc__rc$6 1'0 @@ -81667,7 +89435,7 @@ module \main$63 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.output" -module \output$64 +module \output$77 attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60" wire width 2 input 0 \muxid attribute \enum_base_type "InternalOp" @@ -81745,18 +89513,19 @@ module \output$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 input 1 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 input 2 \op__fn_unit + wire width 11 input 2 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 input 3 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -81876,18 +89645,19 @@ module \output$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 output 23 \op__insn_type$2 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 output 24 \op__fn_unit$3 + wire width 11 output 24 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 output 25 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -82167,7 +89937,7 @@ module \output$64 end process $group_16 assign \op__insn_type$2 7'0000000 - assign \op__fn_unit$3 10'0000000000 + assign \op__fn_unit$3 11'00000000000 assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$5 1'0 assign \op__rc__rc$6 1'0 @@ -82190,7 +89960,7 @@ module \output$64 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe" -module \pipe$59 +module \pipe$72 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -82276,18 +90046,19 @@ module \pipe$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 input 5 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 input 6 \op__fn_unit + wire width 11 input 6 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 input 7 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -82415,20 +90186,21 @@ module \pipe$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 \op__insn_type$2$next attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 output 30 \op__fn_unit$3 + wire width 11 output 30 \op__fn_unit$3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \op__fn_unit$3$next + wire width 11 \op__fn_unit$3$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 output 31 \op__imm_data__imm$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -82517,11 +90289,11 @@ module \pipe$59 wire width 1 output 51 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \xer_ca_ok$next - cell \p$60 \p + cell \p$73 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$61 \n + cell \n$74 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -82602,18 +90374,19 @@ module \pipe$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 \input_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \input_op__fn_unit + wire width 11 \input_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 \input_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -82733,18 +90506,19 @@ module \pipe$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 \input_op__insn_type$21 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \input_op__fn_unit$22 + wire width 11 \input_op__fn_unit$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 \input_op__imm_data__imm$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -82787,7 +90561,7 @@ module \pipe$59 wire width 64 \input_rc$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19" wire width 2 \input_xer_ca$41 - cell \input$62 \input + cell \input$75 \input connect \muxid \input_muxid connect \op__insn_type \input_op__insn_type connect \op__fn_unit \input_op__fn_unit @@ -82910,18 +90684,19 @@ module \pipe$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 \main_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \main_op__fn_unit + wire width 11 \main_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 \main_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -83039,18 +90814,19 @@ module \pipe$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 \main_op__insn_type$43 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \main_op__fn_unit$44 + wire width 11 \main_op__fn_unit$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 \main_op__imm_data__imm$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -83091,7 +90867,7 @@ module \pipe$59 wire width 1 \main_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 2 \main_xer_ca - cell \main$63 \main + cell \main$76 \main connect \muxid \main_muxid connect \op__insn_type \main_op__insn_type connect \op__fn_unit \main_op__fn_unit @@ -83212,18 +90988,19 @@ module \pipe$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 \output_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \output_op__fn_unit + wire width 11 \output_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 \output_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -83343,18 +91120,19 @@ module \pipe$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 \output_op__insn_type$61 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \output_op__fn_unit$62 + wire width 11 \output_op__fn_unit$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 \output_op__imm_data__imm$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -83401,7 +91179,7 @@ module \pipe$59 wire width 2 \output_xer_ca$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \output_xer_ca_ok - cell \output$64 \output + cell \output$77 \output connect \muxid \output_muxid connect \op__insn_type \output_op__insn_type connect \op__fn_unit \output_op__fn_unit @@ -83456,7 +91234,7 @@ module \pipe$59 end process $group_1 assign \input_op__insn_type 7'0000000 - assign \input_op__fn_unit 10'0000000000 + assign \input_op__fn_unit 11'00000000000 assign \input_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \input_op__imm_data__imm_ok 1'0 assign \input_op__rc__rc 1'0 @@ -83502,7 +91280,7 @@ module \pipe$59 end process $group_23 assign \main_op__insn_type 7'0000000 - assign \main_op__fn_unit 10'0000000000 + assign \main_op__fn_unit 11'00000000000 assign \main_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \main_op__imm_data__imm_ok 1'0 assign \main_op__rc__rc 1'0 @@ -83550,7 +91328,7 @@ module \pipe$59 end process $group_45 assign \output_op__insn_type 7'0000000 - assign \output_op__fn_unit 10'0000000000 + assign \output_op__fn_unit 11'00000000000 assign \output_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \output_op__imm_data__imm_ok 1'0 assign \output_op__rc__rc 1'0 @@ -83713,18 +91491,19 @@ module \pipe$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 \op__insn_type$92 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \op__fn_unit$93 + wire width 11 \op__fn_unit$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 \op__imm_data__imm$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -83761,7 +91540,7 @@ module \pipe$59 wire width 32 \op__insn$108 process $group_72 assign \op__insn_type$92 7'0000000 - assign \op__fn_unit$93 10'0000000000 + assign \op__fn_unit$93 11'00000000000 assign \op__imm_data__imm$94 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$95 1'0 assign \op__rc__rc$96 1'0 @@ -83893,7 +91672,7 @@ module \pipe$59 end sync init update \op__insn_type$2 7'0000000 - update \op__fn_unit$3 10'0000000000 + update \op__fn_unit$3 11'00000000000 update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000 update \op__imm_data__imm_ok$5 1'0 update \op__rc__rc$6 1'0 @@ -84112,18 +91891,19 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 input 10 \op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 input 11 \op__fn_unit + wire width 11 input 11 \op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 input 12 \op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -84170,11 +91950,11 @@ module \alu_shift_rot0 wire width 1 input 31 \p_valid_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152" wire width 1 output 32 \p_ready_o - cell \p$57 \p + cell \p$70 \p connect \p_valid_i \p_valid_i connect \p_ready_o \p_ready_o end - cell \n$58 \n + cell \n$71 \n connect \n_valid_o \n_valid_o connect \n_ready_i \n_ready_i end @@ -84259,18 +92039,19 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 \pipe_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \pipe_op__fn_unit + wire width 11 \pipe_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 \pipe_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -84394,18 +92175,19 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 \pipe_op__insn_type$3 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \pipe_op__fn_unit$4 + wire width 11 \pipe_op__fn_unit$4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 \pipe_op__imm_data__imm$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -84452,7 +92234,7 @@ module \alu_shift_rot0 wire width 2 \pipe_xer_ca$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \pipe_xer_ca_ok - cell \pipe$59 \pipe + cell \pipe$72 \pipe connect \rst \rst connect \clk \clk connect \p_valid_i \pipe_p_valid_i @@ -84525,7 +92307,7 @@ module \alu_shift_rot0 end process $group_3 assign \pipe_op__insn_type 7'0000000 - assign \pipe_op__fn_unit 10'0000000000 + assign \pipe_op__fn_unit 11'00000000000 assign \pipe_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \pipe_op__imm_data__imm_ok 1'0 assign \pipe_op__rc__rc 1'0 @@ -84656,18 +92438,19 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 \op__insn_type$22 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \op__fn_unit$23 + wire width 11 \op__fn_unit$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 \op__imm_data__imm$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -84704,7 +92487,7 @@ module \alu_shift_rot0 wire width 32 \op__insn$38 process $group_27 assign \op__insn_type$22 7'0000000 - assign \op__fn_unit$23 10'0000000000 + assign \op__fn_unit$23 11'00000000000 assign \op__imm_data__imm$24 64'0000000000000000000000000000000000000000000000000000000000000000 assign \op__imm_data__imm_ok$25 1'0 assign \op__rc__rc$26 1'0 @@ -84745,7 +92528,7 @@ module \alu_shift_rot0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l" -module \src_l$65 +module \src_l$78 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -84890,7 +92673,7 @@ module \src_l$65 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l" -module \opc_l$66 +module \opc_l$79 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -85035,7 +92818,7 @@ module \opc_l$66 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l" -module \req_l$67 +module \req_l$80 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -85180,7 +92963,7 @@ module \req_l$67 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l" -module \rst_l$68 +module \rst_l$81 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -85325,7 +93108,7 @@ module \rst_l$68 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l" -module \rok_l$69 +module \rok_l$82 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -85470,7 +93253,7 @@ module \rok_l$69 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l" -module \alui_l$70 +module \alui_l$83 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -85615,7 +93398,7 @@ module \alui_l$70 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l" -module \alu_l$71 +module \alu_l$84 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -85840,18 +93623,19 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 input 2 \oper_i__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 input 3 \oper_i__fn_unit + wire width 11 input 3 \oper_i__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 input 4 \oper_i__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -86005,18 +93789,19 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 \alu_shift_rot0_op__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \alu_shift_rot0_op__fn_unit + wire width 11 \alu_shift_rot0_op__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 \alu_shift_rot0_op__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -86108,7 +93893,7 @@ module \shiftrot0 wire width 4 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 4 \src_l_q_src - cell \src_l$65 \src_l + cell \src_l$78 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src @@ -86125,7 +93910,7 @@ module \shiftrot0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$66 \opc_l + cell \opc_l$79 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc @@ -86138,7 +93923,7 @@ module \shiftrot0 wire width 3 \req_l_s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 3 \req_l_r_req - cell \req_l$67 \req_l + cell \req_l$80 \req_l connect \rst \rst connect \clk \clk connect \q_req \req_l_q_req @@ -86149,7 +93934,7 @@ module \shiftrot0 wire width 1 \rst_l_s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rst_l_r_rst - cell \rst_l$68 \rst_l + cell \rst_l$81 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst @@ -86163,7 +93948,7 @@ module \shiftrot0 wire width 1 \rok_l_r_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" wire width 1 \rok_l_r_rdok$next - cell \rok_l$69 \rok_l + cell \rok_l$82 \rok_l connect \rst \rst connect \clk \clk connect \q_rdok \rok_l_q_rdok @@ -86178,7 +93963,7 @@ module \shiftrot0 wire width 1 \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alui_l_s_alui - cell \alui_l$70 \alui_l + cell \alui_l$83 \alui_l connect \rst \rst connect \clk \clk connect \q_alui \alui_l_q_alui @@ -86193,7 +93978,7 @@ module \shiftrot0 wire width 1 \alu_l_r_alu$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" wire width 1 \alu_l_s_alu - cell \alu_l$71 \alu_l + cell \alu_l$84 \alu_l connect \rst \rst connect \clk \clk connect \q_alu \alu_l_q_alu @@ -86910,18 +94695,19 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 7 \oper_r__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \oper_r__fn_unit + wire width 11 \oper_r__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" wire width 64 \oper_r__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" @@ -86961,9 +94747,9 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 7 \oper_l__insn_type$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 10 \oper_l__fn_unit + wire width 11 \oper_l__fn_unit attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" - wire width 10 \oper_l__fn_unit$next + wire width 11 \oper_l__fn_unit$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 64 \oper_l__imm_data__imm attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" @@ -87025,10 +94811,10 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37" wire width 32 \oper_l__insn$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 129 $69 + wire width 130 $69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" cell $mux $70 - parameter \WIDTH 129 + parameter \WIDTH 130 connect \A { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type } connect \B { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type } connect \S \issue_i @@ -87036,7 +94822,7 @@ module \shiftrot0 end process $group_25 assign \oper_r__insn_type 7'0000000 - assign \oper_r__fn_unit 10'0000000000 + assign \oper_r__fn_unit 11'00000000000 assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \oper_r__imm_data__imm_ok 1'0 assign \oper_r__rc__rc 1'0 @@ -87094,7 +94880,7 @@ module \shiftrot0 end sync init update \oper_l__insn_type 7'0000000 - update \oper_l__fn_unit 10'0000000000 + update \oper_l__fn_unit 11'00000000000 update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 update \oper_l__imm_data__imm_ok 1'0 update \oper_l__rc__rc 1'0 @@ -87343,7 +95129,7 @@ module \shiftrot0 end process $group_72 assign \alu_shift_rot0_op__insn_type 7'0000000 - assign \alu_shift_rot0_op__fn_unit 10'0000000000 + assign \alu_shift_rot0_op__fn_unit 11'00000000000 assign \alu_shift_rot0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \alu_shift_rot0_op__imm_data__imm_ok 1'0 assign \alu_shift_rot0_op__rc__rc 1'0 @@ -87772,7 +95558,7 @@ module \shiftrot0 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l" -module \opc_l$72 +module \opc_l$85 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -87917,7 +95703,7 @@ module \opc_l$72 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l" -module \src_l$73 +module \src_l$86 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -88062,7 +95848,7 @@ module \src_l$73 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l" -module \alu_l$74 +module \alu_l$87 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -88932,7 +96718,7 @@ module \upd_l end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l" -module \rst_l$75 +module \rst_l$88 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -89246,7 +97032,7 @@ module \ldst0 wire width 1 \opc_l_r_opc$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \opc_l_q_opc - cell \opc_l$72 \opc_l + cell \opc_l$85 \opc_l connect \rst \rst connect \clk \clk connect \s_opc \opc_l_s_opc @@ -89263,7 +97049,7 @@ module \ldst0 wire width 3 \src_l_r_src$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 3 \src_l_q_src - cell \src_l$73 \src_l + cell \src_l$86 \src_l connect \rst \rst connect \clk \clk connect \s_src \src_l_s_src @@ -89276,7 +97062,7 @@ module \ldst0 wire width 1 \alu_l_r_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \alu_l_q_alu - cell \alu_l$74 \alu_l + cell \alu_l$87 \alu_l connect \rst \rst connect \clk \clk connect \s_alu \alu_l_s_alu @@ -89365,7 +97151,7 @@ module \ldst0 wire width 1 \rst_l_r_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \rst_l_q_rst - cell \rst_l$75 \rst_l + cell \rst_l$88 \rst_l connect \rst \rst connect \clk \clk connect \s_rst \rst_l_s_rst @@ -91230,18 +99016,19 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 7 input 6 \oper_i__insn_type attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 input 7 \oper_i__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 input 7 \oper_i__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 input 8 \oper_i__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -91368,33 +99155,138 @@ module \fus attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 7 input 33 \oper_i__insn_type$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 7 input 33 \oper_i__insn_type$1 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 11 input 34 \oper_i__fn_unit$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 32 input 35 \oper_i__insn$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 1 input 36 \oper_i__read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 1 input 37 \oper_i__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" + wire width 1 input 38 \issue_i$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" + wire width 1 output 39 \busy_o$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" + wire width 6 input 40 \rdmaskn$6 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 7 input 41 \oper_i__insn_type$7 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 input 34 \oper_i__fn_unit$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 32 input 35 \oper_i__insn$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 1 input 36 \oper_i__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 1 input 37 \oper_i__write_cr_whole + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 11 input 42 \oper_i__fn_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 64 input 43 \oper_i__imm_data__imm$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 1 input 44 \oper_i__imm_data__imm_ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 1 input 45 \oper_i__lk$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 1 input 46 \oper_i__is_32bit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 32 input 47 \oper_i__insn$13 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 input 38 \issue_i$4 + wire width 1 input 48 \issue_i$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 39 \busy_o$5 + wire width 1 output 49 \busy_o$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 6 input 40 \rdmaskn$6 + wire width 4 input 50 \rdmaskn$16 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -91467,37 +99359,36 @@ module \fus attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 7 input 41 \oper_i__insn_type$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 7 input 51 \oper_i__insn_type$17 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 input 42 \oper_i__fn_unit$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 64 input 43 \oper_i__imm_data__imm$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 input 44 \oper_i__imm_data__imm_ok$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 input 45 \oper_i__lk$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 input 46 \oper_i__is_32bit$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 32 input 47 \oper_i__insn$13 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 11 input 52 \oper_i__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 32 input 53 \oper_i__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 1 input 54 \oper_i__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 5 input 55 \oper_i__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 13 input 56 \oper_i__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 input 48 \issue_i$14 + wire width 1 input 57 \issue_i$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 49 \busy_o$15 + wire width 1 output 58 \busy_o$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 4 input 50 \rdmaskn$16 + wire width 6 input 59 \rdmaskn$23 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -91570,35 +99461,68 @@ module \fus attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 7 input 51 \oper_i__insn_type$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 input 60 \oper_i__insn_type$24 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 input 52 \oper_i__fn_unit$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 32 input 53 \oper_i__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 1 input 54 \oper_i__is_32bit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 input 55 \oper_i__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 13 input 56 \oper_i__trapaddr + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 input 61 \oper_i__fn_unit$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 64 input 62 \oper_i__imm_data__imm$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 63 \oper_i__imm_data__imm_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 64 \oper_i__lk$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 65 \oper_i__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 66 \oper_i__rc__rc_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 67 \oper_i__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 68 \oper_i__oe__oe_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 69 \oper_i__invert_a$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 70 \oper_i__zero_a$34 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 input 71 \oper_i__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 72 \oper_i__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 3 input 73 \oper_i__write_cr__data$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 74 \oper_i__write_cr__ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 75 \oper_i__output_carry$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 76 \oper_i__is_32bit$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 input 77 \oper_i__is_signed$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 input 78 \oper_i__data_len$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 32 input 79 \oper_i__insn$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 input 57 \issue_i$21 + wire width 1 input 80 \issue_i$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 58 \busy_o$22 + wire width 1 output 81 \busy_o$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 6 input 59 \rdmaskn$23 + wire width 2 input 82 \rdmaskn$46 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -91671,67 +99595,32 @@ module \fus attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 7 input 60 \oper_i__insn_type$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 input 83 \oper_i__insn_type$47 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 input 61 \oper_i__fn_unit$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 64 input 62 \oper_i__imm_data__imm$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 63 \oper_i__imm_data__imm_ok$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 64 \oper_i__lk$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 65 \oper_i__rc__rc$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 66 \oper_i__rc__rc_ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 67 \oper_i__oe__oe$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 68 \oper_i__oe__oe_ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 69 \oper_i__invert_a$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 70 \oper_i__zero_a$34 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 2 input 71 \oper_i__input_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 72 \oper_i__invert_out$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 3 input 73 \oper_i__write_cr__data$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 74 \oper_i__write_cr__ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 75 \oper_i__output_carry$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 76 \oper_i__is_32bit$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 input 77 \oper_i__is_signed$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 4 input 78 \oper_i__data_len$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 32 input 79 \oper_i__insn$43 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 input 84 \oper_i__fn_unit$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 input 85 \oper_i__insn$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 input 86 \oper_i__is_32bit$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 input 80 \issue_i$44 + wire width 1 input 87 \issue_i$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 81 \busy_o$45 + wire width 1 output 88 \busy_o$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 2 input 82 \rdmaskn$46 + wire width 6 input 89 \rdmaskn$53 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -91805,60 +99694,61 @@ module \fus attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 7 input 83 \oper_i__insn_type$47 + wire width 7 input 90 \oper_i__insn_type$54 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 input 84 \oper_i__fn_unit$48 + wire width 11 input 91 \oper_i__fn_unit$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 64 input 85 \oper_i__imm_data__imm$49 + wire width 64 input 92 \oper_i__imm_data__imm$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 86 \oper_i__imm_data__imm_ok$50 + wire width 1 input 93 \oper_i__imm_data__imm_ok$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 87 \oper_i__rc__rc$51 + wire width 1 input 94 \oper_i__rc__rc$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 88 \oper_i__rc__rc_ok$52 + wire width 1 input 95 \oper_i__rc__rc_ok$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 89 \oper_i__oe__oe$53 + wire width 1 input 96 \oper_i__oe__oe$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 90 \oper_i__oe__oe_ok$54 + wire width 1 input 97 \oper_i__oe__oe_ok$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 3 input 91 \oper_i__write_cr__data$55 + wire width 3 input 98 \oper_i__write_cr__data$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 92 \oper_i__write_cr__ok$56 + wire width 1 input 99 \oper_i__write_cr__ok$63 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 2 input 93 \oper_i__input_carry$57 + wire width 2 input 100 \oper_i__input_carry$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 94 \oper_i__output_carry$58 + wire width 1 input 101 \oper_i__output_carry$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 95 \oper_i__input_cr$59 + wire width 1 input 102 \oper_i__input_cr$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 96 \oper_i__output_cr$60 + wire width 1 input 103 \oper_i__output_cr$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 97 \oper_i__is_32bit$61 + wire width 1 input 104 \oper_i__is_32bit$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 input 98 \oper_i__is_signed$62 + wire width 1 input 105 \oper_i__is_signed$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 32 input 99 \oper_i__insn$63 + wire width 32 input 106 \oper_i__insn$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 input 100 \issue_i$64 + wire width 1 input 107 \issue_i$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 101 \busy_o$65 + wire width 1 output 108 \busy_o$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 4 input 102 \rdmaskn$66 + wire width 4 input 109 \rdmaskn$73 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -91932,303 +99822,353 @@ module \fus attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 7 input 103 \oper_i__insn_type$67 + wire width 7 input 110 \oper_i__insn_type$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 64 input 104 \oper_i__imm_data__imm$68 + wire width 64 input 111 \oper_i__imm_data__imm$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 105 \oper_i__imm_data__imm_ok$69 + wire width 1 input 112 \oper_i__imm_data__imm_ok$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 106 \oper_i__zero_a$70 + wire width 1 input 113 \oper_i__zero_a$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 107 \oper_i__is_32bit$71 + wire width 1 input 114 \oper_i__is_32bit$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 108 \oper_i__is_signed$72 + wire width 1 input 115 \oper_i__is_signed$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 4 input 109 \oper_i__data_len$73 + wire width 4 input 116 \oper_i__data_len$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 110 \oper_i__byte_reverse$74 + wire width 1 input 117 \oper_i__byte_reverse$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 111 \oper_i__sign_extend$75 + wire width 1 input 118 \oper_i__sign_extend$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 input 112 \oper_i__update + wire width 1 input 119 \oper_i__update attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 input 113 \issue_i$76 + wire width 1 input 120 \issue_i$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 114 \busy_o$77 + wire width 1 output 121 \busy_o$84 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 3 input 115 \rdmaskn$78 + wire width 3 input 122 \rdmaskn$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 4 output 123 \rd__rel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 4 input 124 \rd__go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 input 125 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 116 \rd__rel + wire width 6 output 126 \rd__rel$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 117 \rd__go + wire width 6 input 127 \rd__go$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 118 \src1_i + wire width 64 input 128 \src1_i$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 119 \rd__rel$79 + wire width 6 output 129 \rd__rel$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 input 120 \rd__go$80 + wire width 6 input 130 \rd__go$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 121 \src1_i$81 + wire width 64 input 131 \src1_i$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 122 \rd__rel$82 + wire width 2 output 132 \rd__rel$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 input 123 \rd__go$83 + wire width 2 input 133 \rd__go$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 124 \src1_i$84 + wire width 64 input 134 \src1_i$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 125 \rd__rel$85 + wire width 6 output 135 \rd__rel$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 input 126 \rd__go$86 + wire width 6 input 136 \rd__go$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 127 \src1_i$87 + wire width 64 input 137 \src1_i$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 128 \rd__rel$88 + wire width 4 output 138 \rd__rel$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 129 \rd__go$89 + wire width 4 input 139 \rd__go$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 130 \src1_i$90 + wire width 64 input 140 \src1_i$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 131 \rd__rel$91 + wire width 3 output 141 \rd__rel$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 132 \rd__go$92 + wire width 3 input 142 \rd__go$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 133 \src1_i$93 + wire width 64 input 143 \src1_i$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 134 \src2_i + wire width 64 input 144 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 135 \src2_i$94 + wire width 64 input 145 \src2_i$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 136 \src2_i$95 + wire width 64 input 146 \src2_i$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 137 \src2_i$96 + wire width 64 input 147 \src2_i$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 138 \src2_i$97 + wire width 64 input 148 \src2_i$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 139 \src2_i$98 + wire width 64 input 149 \src2_i$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 140 \src3_i + wire width 64 input 150 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 141 \src3_i$99 + wire width 64 input 151 \src3_i$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 1 input 142 \src3_i$100 + wire width 1 input 152 \src3_i$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 2 input 143 \src4_i + wire width 1 input 153 \src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 2 input 144 \src4_i$101 + wire width 2 input 154 \src4_i$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 32 input 145 \src3_i$102 + wire width 2 input 155 \src6_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 input 146 \src4_i$103 + wire width 2 input 156 \src4_i$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 2 input 157 \src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 32 input 158 \src3_i$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 4 input 159 \src4_i$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 147 \rd__rel$104 + wire width 4 output 160 \rd__rel$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 input 148 \rd__go$105 + wire width 4 input 161 \rd__go$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 4 input 162 \src3_i$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 4 input 163 \src5_i$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 input 149 \src3_i$106 + wire width 4 input 164 \src6_i$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 input 150 \src5_i + wire width 64 input 165 \src1_i$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 input 151 \src6_i + wire width 64 input 166 \src3_i$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 152 \src1_i$107 + wire width 64 input 167 \src3_i$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 153 \src3_i$108 + wire width 64 input 168 \src2_i$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 154 \src2_i$109 + wire width 64 input 169 \src4_i$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 155 \src4_i$110 + wire width 64 input 170 \src4_i$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 156 \src4_i$111 + wire width 64 input 171 \src5_i$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 157 \src5_i$112 + wire width 64 input 172 \src6_i$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 input 158 \src6_i$113 + wire width 64 input 173 \src2_i$128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 159 \o_ok + wire width 1 output 174 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 160 \wr__rel + wire width 5 output 175 \wr__rel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 input 161 \wr__go + wire width 5 input 176 \wr__go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 162 \o_ok$114 + wire width 1 output 177 \o_ok$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 163 \wr__rel$115 + wire width 3 output 178 \wr__rel$130 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 164 \wr__go$116 + wire width 3 input 179 \wr__go$131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 165 \o_ok$117 + wire width 1 output 180 \o_ok$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 166 \wr__rel$118 + wire width 5 output 181 \wr__rel$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 input 167 \wr__go$119 + wire width 5 input 182 \wr__go$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 168 \o_ok$120 + wire width 1 output 183 \o_ok$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 169 \wr__rel$121 + wire width 3 output 184 \wr__rel$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 170 \wr__go$122 + wire width 3 input 185 \wr__go$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 171 \o_ok$123 + wire width 1 output 186 \o_ok$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 172 \wr__rel$124 + wire width 6 output 187 \wr__rel$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 173 \wr__go$125 + wire width 6 input 188 \wr__go$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 189 \o_ok$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 output 190 \wr__rel$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 174 \wr__rel$126 + wire width 3 input 191 \wr__go$143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 input 175 \wr__go$127 + wire width 2 output 192 \wr__rel$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 2 input 193 \wr__go$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 194 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 176 \o + wire width 64 output 195 \o$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 177 \o$128 + wire width 64 output 196 \o$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 178 \o$129 + wire width 64 output 197 \o$148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 179 \o$130 + wire width 64 output 198 \o$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 180 \o$131 + wire width 64 output 199 \o$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 181 \o$132 + wire width 64 output 200 \o$151 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 182 \ea + wire width 64 output 201 \ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 183 \full_cr_ok + wire width 1 output 202 \full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 32 output 184 \full_cr + wire width 32 output 203 \full_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 185 \cr_a_ok + wire width 1 output 204 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 186 \cr_a_ok$133 + wire width 1 output 205 \cr_a_ok$152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 187 \cr_a_ok$134 + wire width 1 output 206 \cr_a_ok$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 188 \cr_a_ok$135 + wire width 1 output 207 \cr_a_ok$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 output 189 \cr_a + wire width 4 output 208 \cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 output 190 \cr_a$136 + wire width 4 output 209 \cr_a$155 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 output 191 \cr_a$137 + wire width 4 output 210 \cr_a$156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 output 192 \cr_a$138 + wire width 4 output 211 \cr_a$157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 193 \xer_ca_ok + wire width 1 output 212 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 194 \xer_ca_ok$139 + wire width 1 output 213 \xer_ca_ok$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 195 \xer_ca_ok$140 + wire width 1 output 214 \xer_ca_ok$159 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 output 196 \xer_ca + wire width 1 output 215 \xer_ca_ok$160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 output 197 \xer_ca$141 + wire width 2 output 216 \xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 output 198 \xer_ca$142 + wire width 2 output 217 \xer_ca$161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 199 \xer_ov_ok + wire width 2 output 218 \xer_ca$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 output 200 \xer_ov + wire width 2 output 219 \xer_ca$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 201 \xer_so_ok + wire width 1 output 220 \xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 202 \xer_so + wire width 1 output 221 \xer_ov_ok$164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 203 \spr1_ok + wire width 2 output 222 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 output 223 \xer_ov$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 224 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 225 \xer_so_ok$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 226 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 227 \xer_so$167 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 228 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 204 \wr__rel$143 + wire width 3 output 229 \wr__rel$168 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 input 205 \wr__go$144 + wire width 3 input 230 \wr__go$169 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 231 \fast1_ok$170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 232 \fast1_ok$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 206 \spr1_ok$145 + wire width 64 output 233 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 207 \spr1 + wire width 64 output 234 \fast1$172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 208 \spr1$146 + wire width 64 output 235 \fast1$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 209 \spr2_ok + wire width 1 output 236 \fast2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 210 \spr2_ok$147 + wire width 1 output 237 \fast2_ok$174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 211 \spr2 + wire width 64 output 238 \fast2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 212 \spr2$148 + wire width 64 output 239 \fast2$175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 213 \nia_ok + wire width 1 output 240 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 214 \nia_ok$149 + wire width 1 output 241 \nia_ok$176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 215 \nia + wire width 64 output 242 \nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 216 \nia$150 + wire width 64 output 243 \nia$177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 217 \msr_ok + wire width 1 output 244 \msr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 218 \msr + wire width 64 output 245 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 246 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 247 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 1 input 248 \go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" + wire width 1 input 249 \shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 64 output 250 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 219 \go_die_i + wire width 1 input 251 \go_die_i$178 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 220 \shadown_i + wire width 1 input 252 \shadown_i$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 221 \dest1_o + wire width 64 output 253 \dest1_o$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 222 \go_die_i$151 + wire width 1 input 254 \go_die_i$181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 223 \shadown_i$152 + wire width 1 input 255 \shadown_i$182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 224 \dest1_o$153 + wire width 64 output 256 \dest1_o$183 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 225 \go_die_i$154 + wire width 1 input 257 \go_die_i$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 226 \shadown_i$155 + wire width 1 input 258 \shadown_i$185 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 227 \dest1_o$156 + wire width 64 output 259 \dest1_o$186 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 228 \go_die_i$157 + wire width 1 input 260 \go_die_i$187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 229 \shadown_i$158 + wire width 1 input 261 \shadown_i$188 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 230 \dest1_o$159 + wire width 64 output 262 \dest1_o$189 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 231 \go_die_i$160 + wire width 1 input 263 \go_die_i$190 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 232 \shadown_i$161 + wire width 1 input 264 \shadown_i$191 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 233 \dest1_o$162 + wire width 64 output 265 \dest1_o$192 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 234 \go_die_i$163 + wire width 1 input 266 \go_die_i$193 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 235 \shadown_i$164 + wire width 1 input 267 \shadown_i$194 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 236 \dest1_o$165 + wire width 64 output 268 \dest1_o$195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 237 \go_die_i$166 + wire width 1 input 269 \go_die_i$196 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112" - wire width 1 output 238 \load_mem_o + wire width 1 output 270 \load_mem_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" - wire width 1 output 239 \stwd_mem_o + wire width 1 output 271 \stwd_mem_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 240 \shadown_i$167 + wire width 1 input 272 \shadown_i$197 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 output 241 \ldst_port0_is_ld_i + wire width 1 output 273 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 output 242 \ldst_port0_is_st_i + wire width 1 output 274 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 output 243 \ldst_port0_data_len + wire width 4 output 275 \ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 96 output 244 \ldst_port0_addr_i + wire width 96 output 276 \ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 245 \ldst_port0_addr_i_ok + wire width 1 output 277 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 input 246 \ldst_port0_addr_exc_o + wire width 1 input 278 \ldst_port0_addr_exc_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 input 247 \ldst_port0_addr_ok_o + wire width 1 input 279 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 input 248 \ldst_port0_ld_data_o + wire width 64 input 280 \ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 input 249 \ldst_port0_ld_data_o_ok + wire width 1 input 281 \ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 250 \ldst_port0_st_data_i + wire width 64 output 282 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 251 \ldst_port0_st_data_i_ok + wire width 1 output 283 \ldst_port0_st_data_i_ok cell \alu0 \alu0 connect \rst \rst connect \clk \clk @@ -92263,8 +100203,8 @@ module \fus connect \rd__go \rd__go connect \src1_i \src1_i connect \src2_i \src2_i - connect \src3_i \src3_i$100 - connect \src4_i \src4_i + connect \src3_i \src3_i$110 + connect \src4_i \src4_i$111 connect \o_ok \o_ok connect \wr__rel \wr__rel connect \wr__go \wr__go @@ -92292,25 +100232,25 @@ module \fus connect \issue_i \issue_i$4 connect \busy_o \busy_o$5 connect \rdmaskn \rdmaskn$6 - connect \rd__rel \rd__rel$79 - connect \rd__go \rd__go$80 - connect \src1_i \src1_i$81 - connect \src2_i \src2_i$94 - connect \src3_i \src3_i$102 - connect \src4_i \src4_i$103 - connect \src5_i \src5_i - connect \src6_i \src6_i - connect \o_ok \o_ok$114 - connect \wr__rel \wr__rel$115 - connect \wr__go \wr__go$116 - connect \o \o$128 + connect \rd__rel \rd__rel$86 + connect \rd__go \rd__go$87 + connect \src1_i \src1_i$88 + connect \src2_i \src2_i$104 + connect \src3_i \src3_i$113 + connect \src4_i \src4_i$114 + connect \src5_i \src5_i$118 + connect \src6_i \src6_i$119 + connect \o_ok \o_ok$129 + connect \wr__rel \wr__rel$130 + connect \wr__go \wr__go$131 + connect \o \o$146 connect \full_cr_ok \full_cr_ok connect \full_cr \full_cr - connect \cr_a_ok \cr_a_ok$133 - connect \cr_a \cr_a$136 - connect \go_die_i \go_die_i$151 - connect \shadown_i \shadown_i$152 - connect \dest1_o \dest1_o$153 + connect \cr_a_ok \cr_a_ok$152 + connect \cr_a \cr_a$155 + connect \go_die_i \go_die_i$178 + connect \shadown_i \shadown_i$179 + connect \dest1_o \dest1_o$180 end cell \branch0 \branch0 connect \rst \rst @@ -92325,23 +100265,23 @@ module \fus connect \issue_i \issue_i$14 connect \busy_o \busy_o$15 connect \rdmaskn \rdmaskn$16 - connect \rd__rel \rd__rel$104 - connect \rd__go \rd__go$105 - connect \src3_i \src3_i$106 - connect \src1_i \src1_i$107 - connect \src2_i \src2_i$109 - connect \src4_i \src4_i$111 - connect \spr1_ok \spr1_ok - connect \wr__rel \wr__rel$143 - connect \wr__go \wr__go$144 - connect \spr1 \spr1 - connect \spr2_ok \spr2_ok - connect \spr2 \spr2 + connect \rd__rel \rd__rel$115 + connect \rd__go \rd__go$116 + connect \src3_i \src3_i$117 + connect \src1_i \src1_i$120 + connect \src2_i \src2_i$123 + connect \src4_i \src4_i$125 + connect \fast1_ok \fast1_ok + connect \wr__rel \wr__rel$168 + connect \wr__go \wr__go$169 + connect \fast1 \fast1 + connect \fast2_ok \fast2_ok + connect \fast2 \fast2 connect \nia_ok \nia_ok connect \nia \nia - connect \go_die_i \go_die_i$154 - connect \shadown_i \shadown_i$155 - connect \dest1_o \dest1_o$156 + connect \go_die_i \go_die_i$181 + connect \shadown_i \shadown_i$182 + connect \dest1_o \dest1_o$183 end cell \trap0 \trap0 connect \rst \rst @@ -92355,29 +100295,29 @@ module \fus connect \issue_i \issue_i$21 connect \busy_o \busy_o$22 connect \rdmaskn \rdmaskn$23 - connect \rd__rel \rd__rel$82 - connect \rd__go \rd__go$83 - connect \src1_i \src1_i$84 - connect \src2_i \src2_i$95 - connect \src3_i \src3_i$108 - connect \src4_i \src4_i$110 - connect \src5_i \src5_i$112 - connect \src6_i \src6_i$113 - connect \o_ok \o_ok$117 - connect \wr__rel \wr__rel$118 - connect \wr__go \wr__go$119 - connect \o \o$129 - connect \spr1_ok \spr1_ok$145 - connect \spr1 \spr1$146 - connect \spr2_ok \spr2_ok$147 - connect \spr2 \spr2$148 - connect \nia_ok \nia_ok$149 - connect \nia \nia$150 + connect \rd__rel \rd__rel$89 + connect \rd__go \rd__go$90 + connect \src1_i \src1_i$91 + connect \src2_i \src2_i$105 + connect \src3_i \src3_i$121 + connect \src4_i \src4_i$124 + connect \src5_i \src5_i$126 + connect \src6_i \src6_i$127 + connect \o_ok \o_ok$132 + connect \wr__rel \wr__rel$133 + connect \wr__go \wr__go$134 + connect \o \o$147 + connect \fast1_ok \fast1_ok$170 + connect \fast1 \fast1$172 + connect \fast2_ok \fast2_ok$174 + connect \fast2 \fast2$175 + connect \nia_ok \nia_ok$176 + connect \nia \nia$177 connect \msr_ok \msr_ok connect \msr \msr - connect \go_die_i \go_die_i$157 - connect \shadown_i \shadown_i$158 - connect \dest1_o \dest1_o$159 + connect \go_die_i \go_die_i$184 + connect \shadown_i \shadown_i$185 + connect \dest1_o \dest1_o$186 end cell \logical0 \logical0 connect \rst \rst @@ -92405,62 +100345,98 @@ module \fus connect \issue_i \issue_i$44 connect \busy_o \busy_o$45 connect \rdmaskn \rdmaskn$46 - connect \rd__rel \rd__rel$85 - connect \rd__go \rd__go$86 - connect \src1_i \src1_i$87 - connect \src2_i \src2_i$96 - connect \o_ok \o_ok$120 - connect \wr__rel \wr__rel$121 - connect \wr__go \wr__go$122 - connect \o \o$130 - connect \cr_a_ok \cr_a_ok$134 - connect \cr_a \cr_a$137 - connect \xer_ca_ok \xer_ca_ok$139 - connect \xer_ca \xer_ca$141 - connect \go_die_i \go_die_i$160 - connect \shadown_i \shadown_i$161 - connect \dest1_o \dest1_o$162 - end - cell \shiftrot0 \shiftrot0 + connect \rd__rel \rd__rel$92 + connect \rd__go \rd__go$93 + connect \src1_i \src1_i$94 + connect \src2_i \src2_i$106 + connect \o_ok \o_ok$135 + connect \wr__rel \wr__rel$136 + connect \wr__go \wr__go$137 + connect \o \o$148 + connect \cr_a_ok \cr_a_ok$153 + connect \cr_a \cr_a$156 + connect \xer_ca_ok \xer_ca_ok$158 + connect \xer_ca \xer_ca$161 + connect \go_die_i \go_die_i$187 + connect \shadown_i \shadown_i$188 + connect \dest1_o \dest1_o$189 + end + cell \spr0 \spr0 connect \rst \rst connect \clk \clk connect \oper_i__insn_type \oper_i__insn_type$47 connect \oper_i__fn_unit \oper_i__fn_unit$48 - connect \oper_i__imm_data__imm \oper_i__imm_data__imm$49 - connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$50 - connect \oper_i__rc__rc \oper_i__rc__rc$51 - connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$52 - connect \oper_i__oe__oe \oper_i__oe__oe$53 - connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$54 - connect \oper_i__write_cr__data \oper_i__write_cr__data$55 - connect \oper_i__write_cr__ok \oper_i__write_cr__ok$56 - connect \oper_i__input_carry \oper_i__input_carry$57 - connect \oper_i__output_carry \oper_i__output_carry$58 - connect \oper_i__input_cr \oper_i__input_cr$59 - connect \oper_i__output_cr \oper_i__output_cr$60 - connect \oper_i__is_32bit \oper_i__is_32bit$61 - connect \oper_i__is_signed \oper_i__is_signed$62 - connect \oper_i__insn \oper_i__insn$63 - connect \issue_i \issue_i$64 - connect \busy_o \busy_o$65 - connect \rdmaskn \rdmaskn$66 - connect \rd__rel \rd__rel$88 - connect \rd__go \rd__go$89 - connect \src1_i \src1_i$90 - connect \src2_i \src2_i$97 + connect \oper_i__insn \oper_i__insn$49 + connect \oper_i__is_32bit \oper_i__is_32bit$50 + connect \issue_i \issue_i$51 + connect \busy_o \busy_o$52 + connect \rdmaskn \rdmaskn$53 + connect \rd__rel \rd__rel$95 + connect \rd__go \rd__go$96 + connect \src1_i \src1_i$97 + connect \src4_i \src4_i + connect \src6_i \src6_i + connect \src5_i \src5_i + connect \src3_i \src3_i$122 + connect \src2_i \src2_i$128 + connect \o_ok \o_ok$138 + connect \wr__rel \wr__rel$139 + connect \wr__go \wr__go$140 + connect \o \o$149 + connect \xer_ca_ok \xer_ca_ok$159 + connect \xer_ca \xer_ca$162 + connect \xer_ov_ok \xer_ov_ok$164 + connect \xer_ov \xer_ov$165 + connect \xer_so_ok \xer_so_ok$166 + connect \xer_so \xer_so$167 + connect \fast1_ok \fast1_ok$171 + connect \fast1 \fast1$173 + connect \spr1_ok \spr1_ok + connect \spr1 \spr1 + connect \go_die_i \go_die_i$190 + connect \shadown_i \shadown_i$191 + connect \dest1_o \dest1_o$192 + end + cell \shiftrot0 \shiftrot0 + connect \rst \rst + connect \clk \clk + connect \oper_i__insn_type \oper_i__insn_type$54 + connect \oper_i__fn_unit \oper_i__fn_unit$55 + connect \oper_i__imm_data__imm \oper_i__imm_data__imm$56 + connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$57 + connect \oper_i__rc__rc \oper_i__rc__rc$58 + connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$59 + connect \oper_i__oe__oe \oper_i__oe__oe$60 + connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$61 + connect \oper_i__write_cr__data \oper_i__write_cr__data$62 + connect \oper_i__write_cr__ok \oper_i__write_cr__ok$63 + connect \oper_i__input_carry \oper_i__input_carry$64 + connect \oper_i__output_carry \oper_i__output_carry$65 + connect \oper_i__input_cr \oper_i__input_cr$66 + connect \oper_i__output_cr \oper_i__output_cr$67 + connect \oper_i__is_32bit \oper_i__is_32bit$68 + connect \oper_i__is_signed \oper_i__is_signed$69 + connect \oper_i__insn \oper_i__insn$70 + connect \issue_i \issue_i$71 + connect \busy_o \busy_o$72 + connect \rdmaskn \rdmaskn$73 + connect \rd__rel \rd__rel$98 + connect \rd__go \rd__go$99 + connect \src1_i \src1_i$100 + connect \src2_i \src2_i$107 connect \src3_i \src3_i - connect \src4_i \src4_i$101 - connect \o_ok \o_ok$123 - connect \wr__rel \wr__rel$124 - connect \wr__go \wr__go$125 - connect \o \o$131 - connect \cr_a_ok \cr_a_ok$135 - connect \cr_a \cr_a$138 - connect \xer_ca_ok \xer_ca_ok$140 - connect \xer_ca \xer_ca$142 - connect \go_die_i \go_die_i$163 - connect \shadown_i \shadown_i$164 - connect \dest1_o \dest1_o$165 + connect \src4_i \src4_i$112 + connect \o_ok \o_ok$141 + connect \wr__rel \wr__rel$142 + connect \wr__go \wr__go$143 + connect \o \o$150 + connect \cr_a_ok \cr_a_ok$154 + connect \cr_a \cr_a$157 + connect \xer_ca_ok \xer_ca_ok$160 + connect \xer_ca \xer_ca$163 + connect \go_die_i \go_die_i$193 + connect \shadown_i \shadown_i$194 + connect \dest1_o \dest1_o$195 end cell \ldst0 \ldst0 connect \ad__go \ad__go @@ -92469,32 +100445,32 @@ module \fus connect \st__rel \st__rel connect \rst \rst connect \clk \clk - connect \oper_i__insn_type \oper_i__insn_type$67 - connect \oper_i__imm_data__imm \oper_i__imm_data__imm$68 - connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$69 - connect \oper_i__zero_a \oper_i__zero_a$70 - connect \oper_i__is_32bit \oper_i__is_32bit$71 - connect \oper_i__is_signed \oper_i__is_signed$72 - connect \oper_i__data_len \oper_i__data_len$73 - connect \oper_i__byte_reverse \oper_i__byte_reverse$74 - connect \oper_i__sign_extend \oper_i__sign_extend$75 + connect \oper_i__insn_type \oper_i__insn_type$74 + connect \oper_i__imm_data__imm \oper_i__imm_data__imm$75 + connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$76 + connect \oper_i__zero_a \oper_i__zero_a$77 + connect \oper_i__is_32bit \oper_i__is_32bit$78 + connect \oper_i__is_signed \oper_i__is_signed$79 + connect \oper_i__data_len \oper_i__data_len$80 + connect \oper_i__byte_reverse \oper_i__byte_reverse$81 + connect \oper_i__sign_extend \oper_i__sign_extend$82 connect \oper_i__update \oper_i__update - connect \issue_i \issue_i$76 - connect \busy_o \busy_o$77 - connect \rdmaskn \rdmaskn$78 - connect \rd__rel \rd__rel$91 - connect \rd__go \rd__go$92 - connect \src1_i \src1_i$93 - connect \src2_i \src2_i$98 - connect \src3_i \src3_i$99 - connect \wr__rel \wr__rel$126 - connect \wr__go \wr__go$127 - connect \o \o$132 + connect \issue_i \issue_i$83 + connect \busy_o \busy_o$84 + connect \rdmaskn \rdmaskn$85 + connect \rd__rel \rd__rel$101 + connect \rd__go \rd__go$102 + connect \src1_i \src1_i$103 + connect \src2_i \src2_i$108 + connect \src3_i \src3_i$109 + connect \wr__rel \wr__rel$144 + connect \wr__go \wr__go$145 + connect \o \o$151 connect \ea \ea - connect \go_die_i \go_die_i$166 + connect \go_die_i \go_die_i$196 connect \load_mem_o \load_mem_o connect \stwd_mem_o \stwd_mem_o - connect \shadown_i \shadown_i$167 + connect \shadown_i \shadown_i$197 connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i connect \ldst_port0_is_st_i \ldst_port0_is_st_i connect \ldst_port0_data_len \ldst_port0_data_len @@ -94588,7 +102564,7 @@ module \idx_l end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l" -module \reset_l$77 +module \reset_l$90 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -94735,7 +102711,7 @@ module \pick end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.l0.l0" -module \l0$76 +module \l0$89 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -94811,7 +102787,7 @@ module \l0$76 wire width 1 \reset_l_r_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" wire width 1 \reset_l_q_reset - cell \reset_l$77 \reset_l + cell \reset_l$90 \reset_l connect \rst \rst connect \clk \clk connect \s_reset \reset_l_s_reset @@ -96135,7 +104111,7 @@ module \l0 connect \m_valid_i \m_valid_i connect \x_valid_i \x_valid_i end - cell \l0$76 \l0 + cell \l0$89 \l0 connect \rst \rst connect \clk \clk connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i @@ -109660,7 +117636,7 @@ module \int end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0" -module \reg_0$78 +module \reg_0$91 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -110146,7 +118122,7 @@ module \reg_0$78 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1" -module \reg_1$79 +module \reg_1$92 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -110632,7 +118608,7 @@ module \reg_1$79 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2" -module \reg_2$80 +module \reg_2$93 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -111118,7 +119094,7 @@ module \reg_2$80 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3" -module \reg_3$81 +module \reg_3$94 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -111604,7 +119580,7 @@ module \reg_3$81 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4" -module \reg_4$82 +module \reg_4$95 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -112090,7 +120066,7 @@ module \reg_4$82 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5" -module \reg_5$83 +module \reg_5$96 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -112576,7 +120552,7 @@ module \reg_5$83 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6" -module \reg_6$84 +module \reg_6$97 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -113062,7 +121038,7 @@ module \reg_6$84 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7" -module \reg_7$85 +module \reg_7$98 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -113605,7 +121581,7 @@ module \cr wire width 4 \reg_0_w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_0_w0__wen - cell \reg_0$78 \reg_0 + cell \reg_0$91 \reg_0 connect \rst \rst connect \clk \clk connect \src10__ren \reg_0_src10__ren @@ -113651,7 +121627,7 @@ module \cr wire width 4 \reg_1_w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_1_w1__wen - cell \reg_1$79 \reg_1 + cell \reg_1$92 \reg_1 connect \rst \rst connect \clk \clk connect \src11__ren \reg_1_src11__ren @@ -113697,7 +121673,7 @@ module \cr wire width 4 \reg_2_w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_2_w2__wen - cell \reg_2$80 \reg_2 + cell \reg_2$93 \reg_2 connect \rst \rst connect \clk \clk connect \src12__ren \reg_2_src12__ren @@ -113743,7 +121719,7 @@ module \cr wire width 4 \reg_3_w3__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_3_w3__wen - cell \reg_3$81 \reg_3 + cell \reg_3$94 \reg_3 connect \rst \rst connect \clk \clk connect \src13__ren \reg_3_src13__ren @@ -113789,7 +121765,7 @@ module \cr wire width 4 \reg_4_w4__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_4_w4__wen - cell \reg_4$82 \reg_4 + cell \reg_4$95 \reg_4 connect \rst \rst connect \clk \clk connect \src14__ren \reg_4_src14__ren @@ -113835,7 +121811,7 @@ module \cr wire width 4 \reg_5_w5__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_5_w5__wen - cell \reg_5$83 \reg_5 + cell \reg_5$96 \reg_5 connect \rst \rst connect \clk \clk connect \src15__ren \reg_5_src15__ren @@ -113881,7 +121857,7 @@ module \cr wire width 4 \reg_6_w6__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_6_w6__wen - cell \reg_6$84 \reg_6 + cell \reg_6$97 \reg_6 connect \rst \rst connect \clk \clk connect \src16__ren \reg_6_src16__ren @@ -113927,7 +121903,7 @@ module \cr wire width 4 \reg_7_w7__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_7_w7__wen - cell \reg_7$85 \reg_7 + cell \reg_7$98 \reg_7 connect \rst \rst connect \clk \clk connect \src17__ren \reg_7_src17__ren @@ -114423,7 +122399,7 @@ module \cr end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0" -module \reg_0$86 +module \reg_0$99 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -114967,7 +122943,7 @@ module \reg_0$86 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1" -module \reg_1$87 +module \reg_1$100 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -115511,7 +123487,7 @@ module \reg_1$87 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2" -module \reg_2$88 +module \reg_2$101 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -116069,17 +124045,21 @@ module \xer attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 output 5 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 6 \wen + wire width 3 input 6 \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 8 \wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 7 \data_i + wire width 2 input 9 \data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 8 \wen$1 + wire width 3 input 10 \wen$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \data_i$2 + wire width 2 input 11 \data_i$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 10 \wen$3 + wire width 3 input 12 \wen$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \data_i$4 + wire width 2 input 13 \data_i$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_0_src10__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" @@ -116112,7 +124092,7 @@ module \xer wire width 2 \reg_0_w0__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_0_w0__wen - cell \reg_0$86 \reg_0 + cell \reg_0$99 \reg_0 connect \rst \rst connect \clk \clk connect \src10__ren \reg_0_src10__ren @@ -116164,7 +124144,7 @@ module \xer wire width 2 \reg_1_w1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_1_w1__wen - cell \reg_1$87 \reg_1 + cell \reg_1$100 \reg_1 connect \rst \rst connect \clk \clk connect \src11__ren \reg_1_src11__ren @@ -116216,7 +124196,7 @@ module \xer wire width 2 \reg_2_w2__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 1 \reg_2_w2__wen - cell \reg_2$88 \reg_2 + cell \reg_2$101 \reg_2 connect \rst \rst connect \clk \clk connect \src12__ren \reg_2_src12__ren @@ -116312,8 +124292,6 @@ module \xer assign \src2__data_o $11 sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \src3__ren process $group_8 assign \reg_0_src30__ren 1'0 assign \reg_1_src31__ren 1'0 @@ -116321,8 +124299,6 @@ module \xer assign { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" wire width 2 $13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" @@ -116454,14 +124430,13 @@ module \xer assign { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen sync init end - connect \src3__ren 3'000 connect \full_rd__ren 3'000 connect \full_wr__data_i 6'000000 connect \full_wr__wen 3'000 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_0" -module \reg_0$89 +module \reg_0$102 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -117195,7 +125170,7 @@ module \reg_0$89 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_1" -module \reg_1$90 +module \reg_1$103 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -117929,7 +125904,7 @@ module \reg_1$90 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_2" -module \reg_2$91 +module \reg_2$104 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -118663,7 +126638,7 @@ module \reg_2$91 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_3" -module \reg_3$92 +module \reg_3$105 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -119397,7 +127372,7 @@ module \reg_3$92 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_4" -module \reg_4$93 +module \reg_4$106 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -120131,7 +128106,7 @@ module \reg_4$93 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_5" -module \reg_5$94 +module \reg_5$107 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -120865,7 +128840,7 @@ module \reg_5$94 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_6" -module \reg_6$95 +module \reg_6$108 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -121599,7 +129574,7 @@ module \reg_6$95 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.fast.reg_7" -module \reg_7$96 +module \reg_7$109 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" @@ -122418,7 +130393,7 @@ module \fast wire width 1 \reg_0_d_wr10__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_0_d_wr10__data_i - cell \reg_0$89 \reg_0 + cell \reg_0$102 \reg_0 connect \rst \rst connect \clk \clk connect \src10__ren \reg_0_src10__ren @@ -122482,7 +130457,7 @@ module \fast wire width 1 \reg_1_d_wr11__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_1_d_wr11__data_i - cell \reg_1$90 \reg_1 + cell \reg_1$103 \reg_1 connect \rst \rst connect \clk \clk connect \src11__ren \reg_1_src11__ren @@ -122546,7 +130521,7 @@ module \fast wire width 1 \reg_2_d_wr12__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_2_d_wr12__data_i - cell \reg_2$91 \reg_2 + cell \reg_2$104 \reg_2 connect \rst \rst connect \clk \clk connect \src12__ren \reg_2_src12__ren @@ -122610,7 +130585,7 @@ module \fast wire width 1 \reg_3_d_wr13__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_3_d_wr13__data_i - cell \reg_3$92 \reg_3 + cell \reg_3$105 \reg_3 connect \rst \rst connect \clk \clk connect \src13__ren \reg_3_src13__ren @@ -122674,7 +130649,7 @@ module \fast wire width 1 \reg_4_d_wr14__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_4_d_wr14__data_i - cell \reg_4$93 \reg_4 + cell \reg_4$106 \reg_4 connect \rst \rst connect \clk \clk connect \src14__ren \reg_4_src14__ren @@ -122738,7 +130713,7 @@ module \fast wire width 1 \reg_5_d_wr15__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_5_d_wr15__data_i - cell \reg_5$94 \reg_5 + cell \reg_5$107 \reg_5 connect \rst \rst connect \clk \clk connect \src15__ren \reg_5_src15__ren @@ -122802,7 +130777,7 @@ module \fast wire width 1 \reg_6_d_wr16__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_6_d_wr16__data_i - cell \reg_6$95 \reg_6 + cell \reg_6$108 \reg_6 connect \rst \rst connect \clk \clk connect \src16__ren \reg_6_src16__ren @@ -122866,7 +130841,7 @@ module \fast wire width 1 \reg_7_d_wr17__wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \reg_7_d_wr17__data_i - cell \reg_7$96 \reg_7 + cell \reg_7$109 \reg_7 connect \rst \rst connect \clk \clk connect \src17__ren \reg_7_src17__ren @@ -123698,12 +131673,16 @@ module \spr wire width 1 input 0 \rst attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 1 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:197" - wire width 1 \wr_detect attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \src__ren + wire width 1 input 2 \src__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \dest__wen + wire width 64 output 3 \src__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 input 4 \dest__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 5 \dest__data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:197" + wire width 1 \wr_detect attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:201" wire width 1 \addrmatch attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203" @@ -123762,8 +131741,6 @@ module \spr end sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \src__data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203" wire width 1 $5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203" @@ -123777,8 +131754,6 @@ module \spr connect \B \addrmatch connect \Y $5 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \dest__data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:206" wire width 1 $7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:206" @@ -124964,11 +132939,8 @@ module \spr update \reg$116 \reg$116$next update \reg$117 \reg$117$next end - connect \src__ren 1'0 - connect \dest__wen 1'0 connect \dest__waddr 6'000000 connect \src__raddr 6'000000 - connect \dest__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \generator "nMigen" attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_ra" @@ -124976,23 +132948,23 @@ module \rdpick_INT_ra attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 6 input 1 \i + wire width 7 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 6 output 2 \o + wire width 7 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 6 \ni + wire width 7 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 6 $1 + wire width 7 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \i connect \Y $1 end process $group_0 - assign \ni 6'000000 + assign \ni 7'0000000 assign \ni $1 sync init end @@ -125138,24 +133110,51 @@ module \rdpick_INT_ra assign \t5 $19 sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end process $group_7 - assign \o 6'000000 - assign \o { \t5 \t4 \t3 \t2 \t1 \t0 } + assign \t6 1'0 + assign \t6 $23 + sync init + end + process $group_8 + assign \o 7'0000000 + assign \o { \t6 \t5 \t4 \t3 \t2 \t1 \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $23 + wire width 1 $27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $24 + cell $reduce_bool $28 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A \o - connect \Y $23 + connect \Y $27 end - process $group_8 + process $group_9 assign \en_o 1'0 - assign \en_o $23 + assign \en_o $27 sync init end end @@ -125435,23 +133434,23 @@ module \rdpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 1 \i + wire width 2 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 2 \o + wire width 2 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni + wire width 2 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 1 $1 + wire width 2 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \i connect \Y $1 end process $group_0 - assign \ni 1'0 + assign \ni 2'00 assign \ni $1 sync init end @@ -125459,27 +133458,54 @@ module \rdpick_XER_xer_so wire width 1 \t0 process $group_1 assign \t0 1'0 - assign \t0 \i + assign \t0 \i [0] sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end process $group_2 - assign \o 1'0 - assign \o { \t0 } + assign \t1 1'0 + assign \t1 $3 + sync init + end + process $group_3 + assign \o 2'00 + assign \o { \t1 \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $3 + wire width 1 $7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 + cell $reduce_bool $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $3 + connect \Y $7 end - process $group_3 + process $group_4 assign \en_o 1'0 - assign \en_o $3 + assign \en_o $7 sync init end end @@ -125489,23 +133515,23 @@ module \rdpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 2 input 1 \i + wire width 3 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 output 2 \o + wire width 3 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 2 \ni + wire width 3 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 2 $1 + wire width 3 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 connect \A \i connect \Y $1 end process $group_0 - assign \ni 2'00 + assign \ni 3'000 assign \ni $1 sync init end @@ -125543,24 +133569,105 @@ module \rdpick_XER_xer_ca assign \t1 $3 sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end process $group_3 - assign \o 2'00 - assign \o { \t1 \t0 } + assign \t2 1'0 + assign \t2 $7 + sync init + end + process $group_4 + assign \o 3'000 + assign \o { \t2 \t1 \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $7 + wire width 1 $11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $8 + cell $reduce_bool $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $7 + connect \Y $11 end - process $group_4 + process $group_5 assign \en_o 1'0 - assign \en_o $7 + assign \en_o $11 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ov" +module \rdpick_XER_xer_ov + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 0 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 input 1 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 1 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 1'0 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i + sync init + end + process $group_2 + assign \o 1'0 + assign \o { \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $3 + end + process $group_3 + assign \en_o 1'0 + assign \en_o $3 sync init end end @@ -125808,8 +133915,116 @@ module \rdpick_CR_cr_c end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_spr1" -module \rdpick_FAST_spr1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast1" +module \rdpick_FAST_fast1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 0 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 3 input 1 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 3 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 3'000 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + process $group_4 + assign \o 3'000 + assign \o { \t2 \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $11 + end + process $group_5 + assign \en_o 1'0 + assign \en_o $11 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast2" +module \rdpick_FAST_fast2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" @@ -125889,8 +134104,8 @@ module \rdpick_FAST_spr1 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_spr2" -module \rdpick_FAST_spr2 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_cia" +module \rdpick_FAST_cia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" @@ -125970,28 +134185,28 @@ module \rdpick_FAST_spr2 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_cia" -module \rdpick_FAST_cia +attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_msr" +module \rdpick_FAST_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 2 input 1 \i + wire width 1 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 output 2 \o + wire width 1 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 2 \ni + wire width 1 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 2 $1 + wire width 1 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 connect \A \i connect \Y $1 end process $group_0 - assign \ni 2'00 + assign \ni 1'0 assign \ni $1 sync init end @@ -125999,60 +134214,33 @@ module \rdpick_FAST_cia wire width 1 \t0 process $group_1 assign \t0 1'0 - assign \t0 \i [0] + assign \t0 \i sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - process $group_3 - assign \o 2'00 - assign \o { \t1 \t0 } + assign \o 1'0 + assign \o { \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $7 + wire width 1 $3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $8 + cell $reduce_bool $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $7 + connect \Y $3 end - process $group_4 + process $group_3 assign \en_o 1'0 - assign \en_o $7 + assign \en_o $3 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_msr" -module \rdpick_FAST_msr +attribute \nmigen.hierarchy "test_issuer.core.rdpick_SPR_spr1" +module \rdpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" @@ -126110,23 +134298,23 @@ module \wrpick_INT_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 6 input 1 \i + wire width 7 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 6 output 2 \o + wire width 7 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 6 \ni + wire width 7 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 6 $1 + wire width 7 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 connect \A \i connect \Y $1 end process $group_0 - assign \ni 6'000000 + assign \ni 7'0000000 assign \ni $1 sync init end @@ -126272,24 +134460,51 @@ module \wrpick_INT_o assign \t5 $19 sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] } + connect \Y $24 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $26 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $24 + connect \Y $23 + end process $group_7 - assign \o 6'000000 - assign \o { \t5 \t4 \t3 \t2 \t1 \t0 } + assign \t6 1'0 + assign \t6 $23 + sync init + end + process $group_8 + assign \o 7'0000000 + assign \o { \t6 \t5 \t4 \t3 \t2 \t1 \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $23 + wire width 1 $27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $24 + cell $reduce_bool $28 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A \o - connect \Y $23 + connect \Y $27 end - process $group_8 + process $group_9 assign \en_o 1'0 - assign \en_o $23 + assign \en_o $27 sync init end end @@ -126542,23 +134757,23 @@ module \wrpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 3 input 1 \i + wire width 4 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 3 output 2 \o + wire width 4 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 3 \ni + wire width 4 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 3 $1 + wire width 4 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 connect \A \i connect \Y $1 end process $group_0 - assign \ni 3'000 + assign \ni 4'0000 assign \ni $1 sync init end @@ -126623,24 +134838,51 @@ module \wrpick_XER_xer_ca assign \t2 $7 sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] } + connect \Y $12 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $12 + connect \Y $11 + end process $group_4 - assign \o 3'000 - assign \o { \t2 \t1 \t0 } + assign \t3 1'0 + assign \t3 $11 + sync init + end + process $group_5 + assign \o 4'0000 + assign \o { \t3 \t2 \t1 \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $11 + wire width 1 $15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $12 + cell $reduce_bool $16 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $11 + connect \Y $15 end - process $group_5 + process $group_6 assign \en_o 1'0 - assign \en_o $11 + assign \en_o $15 sync init end end @@ -126650,23 +134892,23 @@ module \wrpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 1 \i + wire width 2 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 2 \o + wire width 2 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni + wire width 2 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 1 $1 + wire width 2 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 connect \A \i connect \Y $1 end process $group_0 - assign \ni 1'0 + assign \ni 2'00 assign \ni $1 sync init end @@ -126674,27 +134916,54 @@ module \wrpick_XER_xer_ov wire width 1 \t0 process $group_1 assign \t0 1'0 - assign \t0 \i + assign \t0 \i [0] sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end process $group_2 - assign \o 1'0 - assign \o { \t0 } + assign \t1 1'0 + assign \t1 $3 + sync init + end + process $group_3 + assign \o 2'00 + assign \o { \t1 \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $3 + wire width 1 $7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 + cell $reduce_bool $8 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $3 + connect \Y $7 end - process $group_3 + process $group_4 assign \en_o 1'0 - assign \en_o $3 + assign \en_o $7 sync init end end @@ -126704,23 +134973,104 @@ module \wrpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 input 1 \i + wire width 2 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 output 2 \o + wire width 2 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ni + wire width 2 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 1 $1 + wire width 2 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 2'00 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end + process $group_3 + assign \o 2'00 + assign \o { \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $7 + end + process $group_4 + assign \en_o 1'0 + assign \en_o $7 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_fast1" +module \wrpick_FAST_fast1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 0 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 3 input 1 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 3 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 3 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 connect \A \i connect \Y $1 end process $group_0 - assign \ni 1'0 + assign \ni 3'000 assign \ni $1 sync init end @@ -126728,33 +135078,168 @@ module \wrpick_XER_xer_so wire width 1 \t0 process $group_1 assign \t0 1'0 - assign \t0 \i + assign \t0 \i [0] sync init end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 + connect \Y $3 + end process $group_2 - assign \o 1'0 - assign \o { \t0 } + assign \t1 1'0 + assign \t1 $3 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] } + connect \Y $8 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $8 + connect \Y $7 + end + process $group_3 + assign \t2 1'0 + assign \t2 $7 + sync init + end + process $group_4 + assign \o 3'000 + assign \o { \t2 \t1 \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $3 + wire width 1 $11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $4 + cell $reduce_bool $12 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o + connect \Y $11 + end + process $group_5 + assign \en_o 1'0 + assign \en_o $11 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_fast2" +module \wrpick_FAST_fast2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 output 0 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 2 input 1 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 2 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + wire width 2 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" + cell $not $2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $1 + end + process $group_0 + assign \ni 2'00 + assign \ni $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t0 + process $group_1 + assign \t0 1'0 + assign \t0 \i [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 1 \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + wire width 1 $4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $reduce_bool $5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" + cell $not $6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $4 connect \Y $3 end + process $group_2 + assign \t1 1'0 + assign \t1 $3 + sync init + end process $group_3 + assign \o 2'00 + assign \o { \t1 \t0 } + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + wire width 1 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" + cell $reduce_bool $8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $7 + end + process $group_4 assign \en_o 1'0 - assign \en_o $3 + assign \en_o $7 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_spr1" -module \wrpick_FAST_spr1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_nia" +module \wrpick_FAST_nia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" @@ -126834,109 +135319,28 @@ module \wrpick_FAST_spr1 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_spr2" -module \wrpick_FAST_spr2 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_msr" +module \wrpick_FAST_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 2 input 1 \i + wire width 1 input 1 \i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 output 2 \o + wire width 1 output 2 \o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 2 \ni + wire width 1 \ni attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 2 $1 + wire width 1 $1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \i - connect \Y $1 - end - process $group_0 - assign \ni 2'00 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - process $group_3 - assign \o 2'00 - assign \o { \t1 \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $7 - end - process $group_4 - assign \en_o 1'0 - assign \en_o $7 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_nia" -module \wrpick_FAST_nia - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 output 0 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 2 input 1 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - wire width 2 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 connect \A \i connect \Y $1 end process $group_0 - assign \ni 2'00 + assign \ni 1'0 assign \ni $1 sync init end @@ -126944,60 +135348,33 @@ module \wrpick_FAST_nia wire width 1 \t0 process $group_1 assign \t0 1'0 - assign \t0 \i [0] + assign \t0 \i sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - process $group_3 - assign \o 2'00 - assign \o { \t1 \t0 } + assign \o 1'0 + assign \o { \t0 } sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - wire width 1 $7 + wire width 1 $3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55" - cell $reduce_bool $8 + cell $reduce_bool $4 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $7 + connect \Y $3 end - process $group_4 + process $group_3 assign \en_o 1'0 - assign \en_o $7 + assign \en_o $3 sync init end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_msr" -module \wrpick_FAST_msr +attribute \nmigen.hierarchy "test_issuer.core.wrpick_SPR_spr1" +module \wrpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 output 0 \en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" @@ -127064,9 +135441,9 @@ module \core wire width 8 input 4 \d_rd1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 output 5 \d_rd1__data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:32" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:546" wire width 1 input 6 \valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:75" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:74" wire width 1 input 7 \issue_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:319" wire width 1 input 8 \bigendian @@ -127076,7 +135453,7 @@ module \core wire width 8 output 10 \fast_nia_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 8 \fast_nia_wen$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:75" wire width 1 output 11 \corebusy_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 8 input 12 \wen @@ -127087,18 +135464,19 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" wire width 1 input 15 \clk attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34" - wire width 10 output 16 \fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33" + wire width 11 output 16 \fn_unit attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -127245,7 +135623,7 @@ module \core attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:32" wire width 7 output 18 \insn_type attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 output 19 \imm @@ -127253,7 +135631,7 @@ module \core wire width 1 output 20 \imm_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 1 output 21 \oper_i__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" wire width 1 output 22 \lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 output 23 \rc @@ -127265,13 +135643,13 @@ module \core wire width 1 output 26 \oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 1 output 27 \oper_i__invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" wire width 1 output 28 \invert_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" wire width 1 output 29 \zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 1 output 30 \oper_i__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63" wire width 1 output 31 \invert_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 3 output 32 \cr_out @@ -127287,41 +135665,41 @@ module \core attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64" wire width 2 output 35 \input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 1 output 36 \oper_i__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65" wire width 1 output 37 \output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 1 output 38 \oper_i__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66" wire width 1 output 39 \input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 1 output 40 \oper_i__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67" wire width 1 output 41 \output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 1 output 42 \oper_i__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68" wire width 1 output 43 \is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 1 output 44 \oper_i__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69" wire width 1 output 45 \is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 4 output 46 \oper_i__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" - wire width 4 output 47 \data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71" + wire width 4 output 47 \data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70" wire width 32 output 48 \insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 1 output 49 \oper_i__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" wire width 1 output 50 \byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 1 output 51 \oper_i__sign_extend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73" wire width 1 output 52 \sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" wire width 1 output 53 \issue_i$1 @@ -127403,41 +135781,144 @@ module \core attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 7 output 57 \oper_i__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 7 output 57 \oper_i__insn_type$2 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 11 output 58 \oper_i__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 32 output 59 \oper_i__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 1 output 60 \oper_i__read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 1 output 61 \read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" + wire width 1 output 62 \oper_i__write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" + wire width 1 output 63 \write_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" + wire width 1 output 64 \issue_i$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" + wire width 1 output 65 \busy_o$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 66 \cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 67 \cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 68 \cr_in2_ok$5 + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 7 output 69 \oper_i__insn_type$6 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 output 58 \oper_i__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 32 output 59 \oper_i__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 1 output 60 \oper_i__read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 output 61 \read_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 1 output 62 \oper_i__write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire width 1 output 63 \write_cr_whole + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 11 output 70 \oper_i__fn_unit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 1 output 71 \oper_i__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 1 output 72 \oper_i__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" + wire width 32 output 73 \oper_i__insn$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 64 \issue_i$3 + wire width 1 output 74 \issue_i$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 65 \busy_o$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 66 \cr_in1_ok + wire width 1 output 75 \busy_o$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 67 \cr_in2_ok + wire width 1 output 76 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 68 \cr_in2_ok$5 + wire width 1 output 77 \fast2_ok attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -127510,35 +135991,38 @@ module \core attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 7 output 69 \oper_i__insn_type$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 7 output 78 \oper_i__insn_type$13 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 output 70 \oper_i__fn_unit$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 output 71 \oper_i__lk$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 output 72 \oper_i__is_32bit$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 32 output 73 \oper_i__insn$10 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 11 output 79 \oper_i__fn_unit$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 32 output 80 \oper_i__insn$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 1 output 81 \oper_i__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 5 output 82 \oper_i__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:75" + wire width 5 output 83 \traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" + wire width 13 output 84 \oper_i__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:76" + wire width 13 output 85 \trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 74 \issue_i$11 + wire width 1 output 86 \issue_i$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 75 \busy_o$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 76 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 77 \fast2_ok + wire width 1 output 87 \busy_o$18 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -127611,37 +136095,46 @@ module \core attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 7 output 78 \oper_i__insn_type$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 7 output 88 \oper_i__insn_type$19 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 output 79 \oper_i__fn_unit$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 32 output 80 \oper_i__insn$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 1 output 81 \oper_i__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 output 82 \oper_i__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:76" - wire width 4 input 83 \traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 13 output 84 \oper_i__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:77" - wire width 13 output 85 \trapaddr + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 output 89 \oper_i__fn_unit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 90 \oper_i__lk$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 91 \oper_i__invert_a$22 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 2 output 92 \oper_i__input_carry$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 93 \oper_i__invert_out$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 94 \oper_i__output_carry$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 95 \oper_i__is_32bit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 1 output 96 \oper_i__is_signed$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 4 output 97 \oper_i__data_len$28 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 86 \issue_i$17 + wire width 1 output 98 \issue_i$29 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 87 \busy_o$18 + wire width 1 output 99 \busy_o$30 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -127714,45 +136207,32 @@ module \core attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 7 output 88 \oper_i__insn_type$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 7 output 100 \oper_i__insn_type$31 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 output 89 \oper_i__fn_unit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 90 \oper_i__lk$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 91 \oper_i__invert_a$22 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 2 output 92 \oper_i__input_carry$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 93 \oper_i__invert_out$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 94 \oper_i__output_carry$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 95 \oper_i__is_32bit$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 output 96 \oper_i__is_signed$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 4 output 97 \oper_i__data_len$28 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 output 101 \oper_i__fn_unit$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 output 102 \oper_i__insn$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 output 103 \oper_i__is_32bit$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 98 \issue_i$29 + wire width 1 output 104 \issue_i$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 99 \busy_o$30 + wire width 1 output 105 \busy_o$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 106 \spr1_ok attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -127826,29 +136306,29 @@ module \core attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 7 output 100 \oper_i__insn_type$31 + wire width 7 output 107 \oper_i__insn_type$37 attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 2 output 101 \oper_i__input_carry$32 + wire width 2 output 108 \oper_i__input_carry$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 102 \oper_i__output_carry$33 + wire width 1 output 109 \oper_i__output_carry$39 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 103 \oper_i__input_cr$34 + wire width 1 output 110 \oper_i__input_cr$40 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 104 \oper_i__output_cr$35 + wire width 1 output 111 \oper_i__output_cr$41 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 105 \oper_i__is_32bit$36 + wire width 1 output 112 \oper_i__is_32bit$42 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 106 \oper_i__is_signed$37 + wire width 1 output 113 \oper_i__is_signed$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 107 \issue_i$38 + wire width 1 output 114 \issue_i$44 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 108 \busy_o$39 + wire width 1 output 115 \busy_o$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 109 \reg3_ok + wire width 1 output 116 \reg3_ok attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -127922,161 +136402,401 @@ module \core attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 7 output 110 \oper_i__insn_type$40 + wire width 7 output 117 \oper_i__insn_type$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 111 \oper_i__zero_a + wire width 1 output 118 \oper_i__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 112 \oper_i__is_32bit$41 + wire width 1 output 119 \oper_i__is_32bit$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 113 \oper_i__is_signed$42 + wire width 1 output 120 \oper_i__is_signed$48 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 4 output 114 \oper_i__data_len$43 + wire width 4 output 121 \oper_i__data_len$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 115 \oper_i__byte_reverse$44 + wire width 1 output 122 \oper_i__byte_reverse$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 116 \oper_i__sign_extend$45 + wire width 1 output 123 \oper_i__sign_extend$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 117 \oper_i__update - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:75" - wire width 1 output 118 \update + wire width 1 output 124 \oper_i__update + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74" + wire width 1 output 125 \update attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 119 \issue_i$46 + wire width 1 output 126 \issue_i$52 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 120 \busy_o$47 + wire width 1 output 127 \busy_o$53 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 121 \reg1 + wire width 5 output 128 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 4 output 129 \rd__rel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 4 output 130 \rd__go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 output 131 \src1_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 122 \rd__rel + wire width 6 output 132 \rd__rel$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 123 \rd__go + wire width 6 output 133 \rd__go$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 124 \src1_i + wire width 64 output 134 \src1_i$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 125 \rd__rel$48 + wire width 6 output 135 \rd__rel$57 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 126 \rd__go$49 + wire width 6 output 136 \rd__go$58 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 127 \src1_i$50 + wire width 64 output 137 \src1_i$59 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 128 \rd__rel$51 + wire width 2 output 138 \rd__rel$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 6 output 129 \rd__go$52 + wire width 2 output 139 \rd__go$61 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 130 \src1_i$53 + wire width 64 output 140 \src1_i$62 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 131 \rd__rel$54 + wire width 6 output 141 \rd__rel$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 132 \rd__go$55 + wire width 6 output 142 \rd__go$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 133 \src1_i$56 + wire width 64 output 143 \src1_i$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 134 \rd__rel$57 + wire width 4 output 144 \rd__rel$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 135 \rd__go$58 + wire width 4 output 145 \rd__go$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 136 \src1_i$59 + wire width 64 output 146 \src1_i$68 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 137 \rd__rel$60 + wire width 3 output 147 \rd__rel$69 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 138 \rd__go$61 + wire width 3 output 148 \rd__go$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 139 \src1_i$62 + wire width 64 output 149 \src1_i$71 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 140 \reg2 + wire width 5 output 150 \reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 141 \src2_i + wire width 64 output 151 \src2_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 142 \src2_i$63 + wire width 64 output 152 \src2_i$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 143 \src2_i$64 + wire width 64 output 153 \src2_i$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 144 \src2_i$65 + wire width 64 output 154 \src2_i$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 145 \src2_i$66 + wire width 64 output 155 \src2_i$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 146 \src2_i$67 + wire width 64 output 156 \src2_i$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 147 \reg3 + wire width 5 output 157 \reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 148 \src3_i + wire width 64 output 158 \src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 149 \cr_in1 + wire width 3 output 159 \cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 150 \rd__rel$68 + wire width 4 output 160 \rd__rel$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 151 \rd__go$69 + wire width 4 output 161 \rd__go$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 152 \cr_in2 + wire width 3 output 162 \cr_in2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 153 \cr_in2$70 + wire width 3 output 163 \cr_in2$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 154 \fast1 + wire width 3 output 164 \fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 155 \src1_i$71 + wire width 64 output 165 \src1_i$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 156 \fast2 + wire width 3 output 166 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 output 167 \src2_i$81 + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 10 output 168 \spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 157 \src2_i$72 + wire width 64 output 169 \src2_i$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 158 \rego + wire width 5 output 170 \rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 159 \wr__rel + wire width 5 output 171 \wr__rel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 160 \wr__go + wire width 5 output 172 \wr__go attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" wire width 5 \wr__go$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 161 \wr__rel$73 + wire width 3 output 173 \wr__rel$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 output 174 \wr__go$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 \wr__go$84$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 5 output 175 \wr__rel$85 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 162 \wr__go$74 + wire width 5 output 176 \wr__go$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \wr__go$74$next + wire width 5 \wr__go$86$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 163 \wr__rel$75 + wire width 3 output 177 \wr__rel$87 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 output 164 \wr__go$76 + wire width 3 output 178 \wr__go$88 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 5 \wr__go$76$next + wire width 3 \wr__go$88$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 165 \wr__rel$77 + wire width 6 output 179 \wr__rel$89 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 166 \wr__go$78 + wire width 6 output 180 \wr__go$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \wr__go$78$next + wire width 6 \wr__go$90$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 167 \wr__rel$79 + wire width 3 output 181 \wr__rel$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 168 \wr__go$80 + wire width 3 output 182 \wr__go$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \wr__go$80$next + wire width 3 \wr__go$92$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 input 169 \o_ok + wire width 1 input 183 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 170 \wr__rel$81 + wire width 2 output 184 \wr__rel$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 171 \wr__go$82 + wire width 2 output 185 \wr__go$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 \wr__go$82$next + wire width 2 \wr__go$94$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 172 \o + wire width 64 output 186 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 173 \ea + wire width 5 output 187 \ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 input 174 \ea_ok + wire width 1 input 188 \ea_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 175 \ea$83 + wire width 64 output 189 \ea$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 176 \fasto1 + wire width 3 output 190 \fasto1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 177 \wr__rel$84 + wire width 3 output 191 \wr__rel$96 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 178 \wr__go$85 + wire width 3 output 192 \wr__go$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 \wr__go$85$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 179 \fasto2 + wire width 3 \wr__go$97$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 193 \fasto2 + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 10 output 194 \spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" - wire width 32 output 180 \opcode_in + wire width 32 output 195 \opcode_in attribute \enum_base_type "In1Sel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "RA" @@ -128084,7 +136804,7 @@ module \core attribute \enum_value_011 "SPR" attribute \enum_value_100 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 3 output 181 \in1_sel + wire width 3 output 196 \in1_sel attribute \enum_base_type "In2Sel" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "RB" @@ -128101,26 +136821,26 @@ module \core attribute \enum_value_1100 "SPR" attribute \enum_value_1101 "RS" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 4 output 182 \in2_sel + wire width 4 output 197 \in2_sel attribute \enum_base_type "In3Sel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RS" attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 2 output 183 \in3_sel + wire width 2 output 198 \in3_sel attribute \enum_base_type "OutSel" attribute \enum_value_00 "NONE" attribute \enum_value_01 "RT" attribute \enum_value_10 "RA" attribute \enum_value_11 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 184 \out_sel + wire width 2 output 199 \out_sel attribute \enum_base_type "RC" attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 2 output 185 \rc_sel + wire width 2 output 200 \rc_sel attribute \enum_base_type "CRInSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -128130,7 +136850,7 @@ module \core attribute \enum_value_101 "BC" attribute \enum_value_110 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 3 output 186 \cr_in + wire width 3 output 201 \cr_in attribute \enum_base_type "CROutSel" attribute \enum_value_000 "NONE" attribute \enum_value_001 "CR0" @@ -128138,22 +136858,23 @@ module \core attribute \enum_value_011 "BT" attribute \enum_value_100 "WHOLE_REG" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 187 \cr_out$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37" - wire width 64 output 188 \nia + wire width 3 output 202 \cr_out$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:36" + wire width 64 output 203 \nia attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 189 \function_unit + wire width 11 output 204 \function_unit attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -128227,23 +136948,17 @@ module \core attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 7 output 190 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 191 \rego_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 192 \ea_ok$87 + wire width 7 output 205 \internal_op attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 10 output 193 \spr1 + wire width 1 output 206 \rego_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 194 \spr1_ok + wire width 1 output 207 \ea_ok$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 10 output 195 \spro + wire width 1 output 208 \spro_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 196 \spro_ok + wire width 1 output 209 \fasto1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 197 \fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 198 \fasto2_ok + wire width 1 output 210 \fasto2_ok attribute \enum_base_type "LdstLen" attribute \enum_value_0000 "NONE" attribute \enum_value_0001 "is1B" @@ -128251,25 +136966,27 @@ module \core attribute \enum_value_0100 "is4B" attribute \enum_value_1000 "is8B" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 4 output 199 \ldst_len + wire width 4 output 211 \ldst_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 200 \inv_a + wire width 1 output 212 \inv_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 201 \inv_out + wire width 1 output 213 \inv_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 202 \cry_out + wire width 1 output 214 \cry_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 203 \is_32b + wire width 1 output 215 \is_32b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 204 \sgn + wire width 1 output 216 \sgn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 205 \lk$88 + wire width 1 output 217 \lk$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 206 \br + wire width 1 output 218 \br attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 207 \sgn_ext + wire width 1 output 219 \sgn_ext attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 208 \upd + wire width 1 output 220 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35" + wire width 8 output 221 \asmcode attribute \enum_base_type "Form" attribute \enum_value_00000 "NONE" attribute \enum_value_00001 "I" @@ -128301,157 +137018,163 @@ module \core attribute \enum_value_11011 "Z22" attribute \enum_value_11100 "Z23" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 5 output 209 \form + wire width 5 output 222 \form attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 210 \rsrv + wire width 1 output 223 \rsrv attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 211 \sgl_pipe + wire width 1 output 224 \sgl_pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123" - wire width 8 output 212 \asmcode + wire width 8 output 225 \asmcode$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 1 input 226 \go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" + wire width 1 input 227 \shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 64 output 228 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 213 \go_die_i + wire width 1 input 229 \go_die_i$102 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 214 \shadown_i + wire width 1 input 230 \shadown_i$103 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 215 \dest1_o + wire width 64 output 231 \dest1_o$104 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 216 \go_die_i$89 + wire width 1 input 232 \go_die_i$105 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 217 \shadown_i$90 + wire width 1 input 233 \shadown_i$106 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 218 \dest1_o$91 + wire width 64 output 234 \dest1_o$107 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 219 \go_die_i$92 + wire width 1 input 235 \go_die_i$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 220 \shadown_i$93 + wire width 1 input 236 \shadown_i$109 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 221 \dest1_o$94 + wire width 64 output 237 \dest1_o$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 222 \go_die_i$95 + wire width 1 input 238 \go_die_i$111 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 223 \shadown_i$96 + wire width 1 input 239 \shadown_i$112 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 224 \dest1_o$97 + wire width 64 output 240 \dest1_o$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 225 \go_die_i$98 + wire width 1 input 241 \go_die_i$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 226 \shadown_i$99 + wire width 1 input 242 \shadown_i$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 227 \dest1_o$100 + wire width 64 output 243 \dest1_o$116 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 228 \go_die_i$101 + wire width 1 input 244 \go_die_i$117 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 229 \shadown_i$102 + wire width 1 input 245 \shadown_i$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 230 \dest1_o$103 + wire width 64 output 246 \dest1_o$119 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 231 \go_die_i$104 + wire width 1 input 247 \go_die_i$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112" - wire width 1 output 232 \load_mem_o + wire width 1 output 248 \load_mem_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" - wire width 1 output 233 \stwd_mem_o + wire width 1 output 249 \stwd_mem_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 234 \shadown_i$105 + wire width 1 input 250 \shadown_i$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 output 235 \ldst_port0_is_ld_i + wire width 1 output 251 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 output 236 \ldst_port0_is_st_i + wire width 1 output 252 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 output 237 \ldst_port0_data_len + wire width 4 output 253 \ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 96 output 238 \ldst_port0_addr_i + wire width 96 output 254 \ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 239 \ldst_port0_addr_i_ok + wire width 1 output 255 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 output 240 \ldst_port0_addr_exc_o + wire width 1 output 256 \ldst_port0_addr_exc_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 output 241 \ldst_port0_addr_ok_o + wire width 1 output 257 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 242 \ldst_port0_ld_data_o + wire width 64 output 258 \ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 243 \ldst_port0_ld_data_o_ok + wire width 1 output 259 \ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 244 \ldst_port0_st_data_i + wire width 64 output 260 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 245 \ldst_port0_st_data_i_ok + wire width 1 output 261 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 output 246 \ldst_port0_is_ld_i$106 + wire width 1 output 262 \ldst_port0_is_ld_i$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 1 output 247 \ldst_port0_busy_o + wire width 1 output 263 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 output 248 \ldst_port0_is_st_i$107 + wire width 1 output 264 \ldst_port0_is_st_i$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 output 249 \ldst_port0_data_len$108 + wire width 4 output 265 \ldst_port0_data_len$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 48 output 250 \ldst_port0_addr_i$109 + wire width 48 output 266 \ldst_port0_addr_i$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 251 \ldst_port0_addr_i_ok$110 + wire width 1 output 267 \ldst_port0_addr_i_ok$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27" - wire width 8 output 252 \x_mask_i + wire width 8 output 268 \x_mask_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26" - wire width 48 output 253 \x_addr_i + wire width 48 output 269 \x_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 output 254 \ldst_port0_addr_ok_o$111 + wire width 1 output 270 \ldst_port0_addr_ok_o$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" - wire width 64 output 255 \m_ld_data_o + wire width 64 output 271 \m_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 256 \ldst_port0_ld_data_o$112 + wire width 64 output 272 \ldst_port0_ld_data_o$128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 257 \ldst_port0_ld_data_o_ok$113 + wire width 1 output 273 \ldst_port0_ld_data_o_ok$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42" - wire width 1 output 258 \x_busy_o + wire width 1 output 274 \x_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 259 \ldst_port0_st_data_i_ok$114 + wire width 1 output 275 \ldst_port0_st_data_i_ok$130 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 260 \ldst_port0_st_data_i$115 + wire width 64 output 276 \ldst_port0_st_data_i$131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30" - wire width 64 output 261 \x_st_data_i + wire width 64 output 277 \x_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 input 262 \ldst_port0_addr_exc_o$116 + wire width 1 input 278 \ldst_port0_addr_exc_o$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28" - wire width 1 output 263 \x_ld_i + wire width 1 output 279 \x_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29" - wire width 1 output 264 \x_st_i + wire width 1 output 280 \x_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37" - wire width 1 output 265 \m_valid_i + wire width 1 output 281 \m_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33" - wire width 1 output 266 \x_valid_i + wire width 1 output 282 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" - wire width 1 output 267 \ldst_port0_go_die_i + wire width 1 output 283 \ldst_port0_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" - wire width 1 input 268 \ldst_port0_go_die_i$117 + wire width 1 input 284 \ldst_port0_go_die_i$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 1 output 269 \ldst_port0_busy_o$118 + wire width 1 output 285 \ldst_port0_busy_o$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 270 \dbus__cyc + wire width 1 output 286 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 input 271 \x_stall_i + wire width 1 input 287 \x_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 272 \dbus__ack + wire width 1 input 288 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 273 \dbus__err + wire width 1 input 289 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 274 \dbus__stb + wire width 1 output 290 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 input 275 \dbus__dat_r + wire width 64 input 291 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 45 output 276 \dbus__adr + wire width 45 output 292 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 8 output 277 \dbus__sel + wire width 8 output 293 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 278 \dbus__we + wire width 1 output 294 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 output 279 \dbus__dat_w + wire width 64 output 295 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36" - wire width 1 input 280 \m_stall_i + wire width 1 input 296 \m_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire width 1 output 281 \m_load_err_o + wire width 1 output 297 \m_load_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" - wire width 1 output 282 \m_store_err_o + wire width 1 output 298 \m_store_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" - wire width 45 output 283 \m_badaddr_o + wire width 45 output 299 \m_badaddr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" - wire width 1 output 284 \m_busy_o + wire width 1 output 300 \m_busy_o cell \pdecode2 \pdecode2 connect \bigendian \bigendian connect \raw_opcode_in \raw_opcode_in @@ -128488,7 +137211,9 @@ module \core connect \cr_in2_ok$1 \cr_in2_ok$5 connect \fast1_ok \fast1_ok connect \fast2_ok \fast2_ok + connect \traptype \traptype connect \trapaddr \trapaddr + connect \spr1_ok \spr1_ok connect \reg3_ok \reg3_ok connect \update \update connect \reg1 \reg1 @@ -128496,13 +137221,15 @@ module \core connect \reg3 \reg3 connect \cr_in1 \cr_in1 connect \cr_in2 \cr_in2 - connect \cr_in2$2 \cr_in2$70 + connect \cr_in2$2 \cr_in2$79 connect \fast1 \fast1 connect \fast2 \fast2 + connect \spr1 \spr1 connect \rego \rego connect \ea \ea connect \fasto1 \fasto1 connect \fasto2 \fasto2 + connect \spro \spro connect \opcode_in \opcode_in connect \in1_sel \in1_sel connect \in2_sel \in2_sel @@ -128510,15 +137237,12 @@ module \core connect \out_sel \out_sel connect \rc_sel \rc_sel connect \cr_in \cr_in - connect \cr_out$3 \cr_out$86 + connect \cr_out$3 \cr_out$98 connect \nia \nia connect \function_unit \function_unit connect \internal_op \internal_op connect \rego_ok \rego_ok - connect \ea_ok \ea_ok$87 - connect \spr1 \spr1 - connect \spr1_ok \spr1_ok - connect \spro \spro + connect \ea_ok \ea_ok$99 connect \spro_ok \spro_ok connect \fasto1_ok \fasto1_ok connect \fasto2_ok \fasto2_ok @@ -128528,28 +137252,30 @@ module \core connect \cry_out \cry_out connect \is_32b \is_32b connect \sgn \sgn - connect \lk$4 \lk$88 + connect \lk$4 \lk$100 connect \br \br connect \sgn_ext \sgn_ext connect \upd \upd + connect \asmcode \asmcode connect \form \form connect \rsrv \rsrv connect \sgl_pipe \sgl_pipe - connect \asmcode \asmcode + connect \asmcode$5 \asmcode$101 end attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" - wire width 10 \fus_oper_i__fn_unit + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" + wire width 11 \fus_oper_i__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" wire width 64 \fus_oper_i__imm_data__imm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35" @@ -128573,124 +137299,139 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" wire width 4 \fus_rdmaskn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 6 \fus_rdmaskn$119 + wire width 6 \fus_rdmaskn$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 64 \fus_oper_i__imm_data__imm$120 + wire width 64 \fus_oper_i__imm_data__imm$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 1 \fus_oper_i__imm_data__imm_ok$121 + wire width 1 \fus_oper_i__imm_data__imm_ok$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 4 \fus_rdmaskn$122 + wire width 4 \fus_rdmaskn$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 6 \fus_rdmaskn$123 + wire width 6 \fus_rdmaskn$139 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 64 \fus_oper_i__imm_data__imm$124 + wire width 64 \fus_oper_i__imm_data__imm$140 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__imm_data__imm_ok$125 + wire width 1 \fus_oper_i__imm_data__imm_ok$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__rc__rc$126 + wire width 1 \fus_oper_i__rc__rc$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__rc__rc_ok$127 + wire width 1 \fus_oper_i__rc__rc_ok$143 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__oe__oe$128 + wire width 1 \fus_oper_i__oe__oe$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__oe__oe_ok$129 + wire width 1 \fus_oper_i__oe__oe_ok$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__zero_a$130 + wire width 1 \fus_oper_i__zero_a$146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 3 \fus_oper_i__write_cr__data$131 + wire width 3 \fus_oper_i__write_cr__data$147 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 1 \fus_oper_i__write_cr__ok$132 + wire width 1 \fus_oper_i__write_cr__ok$148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 32 \fus_oper_i__insn$133 + wire width 32 \fus_oper_i__insn$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 2 \fus_rdmaskn$134 + wire width 2 \fus_rdmaskn$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" + wire width 6 \fus_rdmaskn$151 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 10 \fus_oper_i__fn_unit$135 + wire width 11 \fus_oper_i__fn_unit$152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 64 \fus_oper_i__imm_data__imm$136 + wire width 64 \fus_oper_i__imm_data__imm$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \fus_oper_i__imm_data__imm_ok$137 + wire width 1 \fus_oper_i__imm_data__imm_ok$154 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \fus_oper_i__rc__rc$138 + wire width 1 \fus_oper_i__rc__rc$155 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \fus_oper_i__rc__rc_ok$139 + wire width 1 \fus_oper_i__rc__rc_ok$156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \fus_oper_i__oe__oe$140 + wire width 1 \fus_oper_i__oe__oe$157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \fus_oper_i__oe__oe_ok$141 + wire width 1 \fus_oper_i__oe__oe_ok$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 3 \fus_oper_i__write_cr__data$142 + wire width 3 \fus_oper_i__write_cr__data$159 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 \fus_oper_i__write_cr__ok$143 + wire width 1 \fus_oper_i__write_cr__ok$160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 32 \fus_oper_i__insn$144 + wire width 32 \fus_oper_i__insn$161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 4 \fus_rdmaskn$145 + wire width 4 \fus_rdmaskn$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 64 \fus_oper_i__imm_data__imm$146 + wire width 64 \fus_oper_i__imm_data__imm$163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 \fus_oper_i__imm_data__imm_ok$147 + wire width 1 \fus_oper_i__imm_data__imm_ok$164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92" - wire width 3 \fus_rdmaskn$148 + wire width 3 \fus_rdmaskn$165 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" wire width 64 \fus_src3_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 1 \fus_src3_i$149 + wire width 1 \fus_src3_i$166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 1 \fus_src4_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 2 \fus_src4_i + wire width 2 \fus_src4_i$167 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 2 \fus_src4_i$150 + wire width 2 \fus_src6_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 32 \fus_src3_i$151 + wire width 2 \fus_src4_i$168 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 \fus_src4_i$152 + wire width 2 \fus_src5_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 \fus_src3_i$153 + wire width 32 \fus_src3_i$169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 \fus_src5_i + wire width 4 \fus_src4_i$170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 4 \fus_src6_i + wire width 4 \fus_src3_i$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 \fus_src3_i$154 + wire width 4 \fus_src5_i$172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 \fus_src4_i$155 + wire width 4 \fus_src6_i$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 \fus_src4_i$156 + wire width 64 \fus_src3_i$174 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 \fus_src5_i$157 + wire width 64 \fus_src3_i$175 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 \fus_src6_i$158 + wire width 64 \fus_src4_i$176 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 \fus_src4_i$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 \fus_src5_i$178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 \fus_src6_i$179 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_o_ok$159 + wire width 1 \fus_o_ok$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fus_o_ok$181 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_o_ok$160 + wire width 1 \fus_o_ok$182 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_o_ok$161 + wire width 1 \fus_o_ok$183 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_o_ok$162 + wire width 1 \fus_o_ok$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 \fus_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_o$163 + wire width 64 \fus_o$185 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_o$164 + wire width 64 \fus_o$186 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_o$165 + wire width 64 \fus_o$187 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_o$166 + wire width 64 \fus_o$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \fus_o$189 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_full_cr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" @@ -128698,67 +137439,87 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_cr_a_ok$167 + wire width 1 \fus_cr_a_ok$190 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_cr_a_ok$168 + wire width 1 \fus_cr_a_ok$191 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_cr_a_ok$169 + wire width 1 \fus_cr_a_ok$192 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 4 \fus_cr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 \fus_cr_a$170 + wire width 4 \fus_cr_a$193 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 \fus_cr_a$171 + wire width 4 \fus_cr_a$194 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 4 \fus_cr_a$172 + wire width 4 \fus_cr_a$195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_xer_ca_ok$173 + wire width 1 \fus_xer_ca_ok$196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fus_xer_ca_ok$197 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_xer_ca_ok$174 + wire width 1 \fus_xer_ca_ok$198 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 2 \fus_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 \fus_xer_ca$175 + wire width 2 \fus_xer_ca$199 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 \fus_xer_ca$176 + wire width 2 \fus_xer_ca$200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \fus_xer_ca$201 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_xer_ov_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fus_xer_ov_ok$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 2 \fus_xer_ov attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 2 \fus_xer_ov$203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fus_xer_so_ok$204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_spr1_ok + wire width 1 \fus_xer_so$205 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_spr1_ok$177 + wire width 1 \fus_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_spr1 + wire width 1 \fus_fast1_ok$206 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_spr1$178 + wire width 1 \fus_fast1_ok$207 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_spr2_ok + wire width 64 \fus_fast1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_spr2_ok$179 + wire width 64 \fus_fast1$208 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_spr2 + wire width 64 \fus_fast1$209 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_spr2$180 + wire width 1 \fus_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fus_fast2_ok$210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \fus_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \fus_fast2$211 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 \fus_nia_ok$181 + wire width 1 \fus_nia_ok$212 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 \fus_nia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 \fus_nia$182 + wire width 64 \fus_nia$213 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 1 \fus_msr_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" wire width 64 \fus_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 \fus_spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 \fus_spr1 cell \fus \fus connect \ad__go \ad__go connect \ad__rel \ad__rel @@ -128800,17 +137561,17 @@ module \core connect \oper_i__write_cr_whole \oper_i__write_cr_whole connect \issue_i$4 \issue_i$3 connect \busy_o$5 \busy_o$4 - connect \rdmaskn$6 \fus_rdmaskn$119 + connect \rdmaskn$6 \fus_rdmaskn$135 connect \oper_i__insn_type$7 \oper_i__insn_type$6 connect \oper_i__fn_unit$8 \oper_i__fn_unit$7 - connect \oper_i__imm_data__imm$9 \fus_oper_i__imm_data__imm$120 - connect \oper_i__imm_data__imm_ok$10 \fus_oper_i__imm_data__imm_ok$121 + connect \oper_i__imm_data__imm$9 \fus_oper_i__imm_data__imm$136 + connect \oper_i__imm_data__imm_ok$10 \fus_oper_i__imm_data__imm_ok$137 connect \oper_i__lk$11 \oper_i__lk$8 connect \oper_i__is_32bit$12 \oper_i__is_32bit$9 connect \oper_i__insn$13 \oper_i__insn$10 connect \issue_i$14 \issue_i$11 connect \busy_o$15 \busy_o$12 - connect \rdmaskn$16 \fus_rdmaskn$122 + connect \rdmaskn$16 \fus_rdmaskn$138 connect \oper_i__insn_type$17 \oper_i__insn_type$13 connect \oper_i__fn_unit$18 \oper_i__fn_unit$14 connect \oper_i__insn$19 \oper_i__insn$15 @@ -128819,188 +137580,220 @@ module \core connect \oper_i__trapaddr \oper_i__trapaddr connect \issue_i$21 \issue_i$17 connect \busy_o$22 \busy_o$18 - connect \rdmaskn$23 \fus_rdmaskn$123 + connect \rdmaskn$23 \fus_rdmaskn$139 connect \oper_i__insn_type$24 \oper_i__insn_type$19 connect \oper_i__fn_unit$25 \oper_i__fn_unit$20 - connect \oper_i__imm_data__imm$26 \fus_oper_i__imm_data__imm$124 - connect \oper_i__imm_data__imm_ok$27 \fus_oper_i__imm_data__imm_ok$125 + connect \oper_i__imm_data__imm$26 \fus_oper_i__imm_data__imm$140 + connect \oper_i__imm_data__imm_ok$27 \fus_oper_i__imm_data__imm_ok$141 connect \oper_i__lk$28 \oper_i__lk$21 - connect \oper_i__rc__rc$29 \fus_oper_i__rc__rc$126 - connect \oper_i__rc__rc_ok$30 \fus_oper_i__rc__rc_ok$127 - connect \oper_i__oe__oe$31 \fus_oper_i__oe__oe$128 - connect \oper_i__oe__oe_ok$32 \fus_oper_i__oe__oe_ok$129 + connect \oper_i__rc__rc$29 \fus_oper_i__rc__rc$142 + connect \oper_i__rc__rc_ok$30 \fus_oper_i__rc__rc_ok$143 + connect \oper_i__oe__oe$31 \fus_oper_i__oe__oe$144 + connect \oper_i__oe__oe_ok$32 \fus_oper_i__oe__oe_ok$145 connect \oper_i__invert_a$33 \oper_i__invert_a$22 - connect \oper_i__zero_a$34 \fus_oper_i__zero_a$130 + connect \oper_i__zero_a$34 \fus_oper_i__zero_a$146 connect \oper_i__input_carry$35 \oper_i__input_carry$23 connect \oper_i__invert_out$36 \oper_i__invert_out$24 - connect \oper_i__write_cr__data$37 \fus_oper_i__write_cr__data$131 - connect \oper_i__write_cr__ok$38 \fus_oper_i__write_cr__ok$132 + connect \oper_i__write_cr__data$37 \fus_oper_i__write_cr__data$147 + connect \oper_i__write_cr__ok$38 \fus_oper_i__write_cr__ok$148 connect \oper_i__output_carry$39 \oper_i__output_carry$25 connect \oper_i__is_32bit$40 \oper_i__is_32bit$26 connect \oper_i__is_signed$41 \oper_i__is_signed$27 connect \oper_i__data_len$42 \oper_i__data_len$28 - connect \oper_i__insn$43 \fus_oper_i__insn$133 + connect \oper_i__insn$43 \fus_oper_i__insn$149 connect \issue_i$44 \issue_i$29 connect \busy_o$45 \busy_o$30 - connect \rdmaskn$46 \fus_rdmaskn$134 + connect \rdmaskn$46 \fus_rdmaskn$150 connect \oper_i__insn_type$47 \oper_i__insn_type$31 - connect \oper_i__fn_unit$48 \fus_oper_i__fn_unit$135 - connect \oper_i__imm_data__imm$49 \fus_oper_i__imm_data__imm$136 - connect \oper_i__imm_data__imm_ok$50 \fus_oper_i__imm_data__imm_ok$137 - connect \oper_i__rc__rc$51 \fus_oper_i__rc__rc$138 - connect \oper_i__rc__rc_ok$52 \fus_oper_i__rc__rc_ok$139 - connect \oper_i__oe__oe$53 \fus_oper_i__oe__oe$140 - connect \oper_i__oe__oe_ok$54 \fus_oper_i__oe__oe_ok$141 - connect \oper_i__write_cr__data$55 \fus_oper_i__write_cr__data$142 - connect \oper_i__write_cr__ok$56 \fus_oper_i__write_cr__ok$143 - connect \oper_i__input_carry$57 \oper_i__input_carry$32 - connect \oper_i__output_carry$58 \oper_i__output_carry$33 - connect \oper_i__input_cr$59 \oper_i__input_cr$34 - connect \oper_i__output_cr$60 \oper_i__output_cr$35 - connect \oper_i__is_32bit$61 \oper_i__is_32bit$36 - connect \oper_i__is_signed$62 \oper_i__is_signed$37 - connect \oper_i__insn$63 \fus_oper_i__insn$144 - connect \issue_i$64 \issue_i$38 - connect \busy_o$65 \busy_o$39 - connect \rdmaskn$66 \fus_rdmaskn$145 - connect \oper_i__insn_type$67 \oper_i__insn_type$40 - connect \oper_i__imm_data__imm$68 \fus_oper_i__imm_data__imm$146 - connect \oper_i__imm_data__imm_ok$69 \fus_oper_i__imm_data__imm_ok$147 - connect \oper_i__zero_a$70 \oper_i__zero_a - connect \oper_i__is_32bit$71 \oper_i__is_32bit$41 - connect \oper_i__is_signed$72 \oper_i__is_signed$42 - connect \oper_i__data_len$73 \oper_i__data_len$43 - connect \oper_i__byte_reverse$74 \oper_i__byte_reverse$44 - connect \oper_i__sign_extend$75 \oper_i__sign_extend$45 + connect \oper_i__fn_unit$48 \oper_i__fn_unit$32 + connect \oper_i__insn$49 \oper_i__insn$33 + connect \oper_i__is_32bit$50 \oper_i__is_32bit$34 + connect \issue_i$51 \issue_i$35 + connect \busy_o$52 \busy_o$36 + connect \rdmaskn$53 \fus_rdmaskn$151 + connect \oper_i__insn_type$54 \oper_i__insn_type$37 + connect \oper_i__fn_unit$55 \fus_oper_i__fn_unit$152 + connect \oper_i__imm_data__imm$56 \fus_oper_i__imm_data__imm$153 + connect \oper_i__imm_data__imm_ok$57 \fus_oper_i__imm_data__imm_ok$154 + connect \oper_i__rc__rc$58 \fus_oper_i__rc__rc$155 + connect \oper_i__rc__rc_ok$59 \fus_oper_i__rc__rc_ok$156 + connect \oper_i__oe__oe$60 \fus_oper_i__oe__oe$157 + connect \oper_i__oe__oe_ok$61 \fus_oper_i__oe__oe_ok$158 + connect \oper_i__write_cr__data$62 \fus_oper_i__write_cr__data$159 + connect \oper_i__write_cr__ok$63 \fus_oper_i__write_cr__ok$160 + connect \oper_i__input_carry$64 \oper_i__input_carry$38 + connect \oper_i__output_carry$65 \oper_i__output_carry$39 + connect \oper_i__input_cr$66 \oper_i__input_cr$40 + connect \oper_i__output_cr$67 \oper_i__output_cr$41 + connect \oper_i__is_32bit$68 \oper_i__is_32bit$42 + connect \oper_i__is_signed$69 \oper_i__is_signed$43 + connect \oper_i__insn$70 \fus_oper_i__insn$161 + connect \issue_i$71 \issue_i$44 + connect \busy_o$72 \busy_o$45 + connect \rdmaskn$73 \fus_rdmaskn$162 + connect \oper_i__insn_type$74 \oper_i__insn_type$46 + connect \oper_i__imm_data__imm$75 \fus_oper_i__imm_data__imm$163 + connect \oper_i__imm_data__imm_ok$76 \fus_oper_i__imm_data__imm_ok$164 + connect \oper_i__zero_a$77 \oper_i__zero_a + connect \oper_i__is_32bit$78 \oper_i__is_32bit$47 + connect \oper_i__is_signed$79 \oper_i__is_signed$48 + connect \oper_i__data_len$80 \oper_i__data_len$49 + connect \oper_i__byte_reverse$81 \oper_i__byte_reverse$50 + connect \oper_i__sign_extend$82 \oper_i__sign_extend$51 connect \oper_i__update \oper_i__update - connect \issue_i$76 \issue_i$46 - connect \busy_o$77 \busy_o$47 - connect \rdmaskn$78 \fus_rdmaskn$148 + connect \issue_i$83 \issue_i$52 + connect \busy_o$84 \busy_o$53 + connect \rdmaskn$85 \fus_rdmaskn$165 connect \rd__rel \rd__rel connect \rd__go \rd__go connect \src1_i \src1_i - connect \rd__rel$79 \rd__rel$48 - connect \rd__go$80 \rd__go$49 - connect \src1_i$81 \src1_i$50 - connect \rd__rel$82 \rd__rel$51 - connect \rd__go$83 \rd__go$52 - connect \src1_i$84 \src1_i$53 - connect \rd__rel$85 \rd__rel$54 - connect \rd__go$86 \rd__go$55 - connect \src1_i$87 \src1_i$56 - connect \rd__rel$88 \rd__rel$57 - connect \rd__go$89 \rd__go$58 - connect \src1_i$90 \src1_i$59 - connect \rd__rel$91 \rd__rel$60 - connect \rd__go$92 \rd__go$61 - connect \src1_i$93 \src1_i$62 + connect \rd__rel$86 \rd__rel$54 + connect \rd__go$87 \rd__go$55 + connect \src1_i$88 \src1_i$56 + connect \rd__rel$89 \rd__rel$57 + connect \rd__go$90 \rd__go$58 + connect \src1_i$91 \src1_i$59 + connect \rd__rel$92 \rd__rel$60 + connect \rd__go$93 \rd__go$61 + connect \src1_i$94 \src1_i$62 + connect \rd__rel$95 \rd__rel$63 + connect \rd__go$96 \rd__go$64 + connect \src1_i$97 \src1_i$65 + connect \rd__rel$98 \rd__rel$66 + connect \rd__go$99 \rd__go$67 + connect \src1_i$100 \src1_i$68 + connect \rd__rel$101 \rd__rel$69 + connect \rd__go$102 \rd__go$70 + connect \src1_i$103 \src1_i$71 connect \src2_i \src2_i - connect \src2_i$94 \src2_i$63 - connect \src2_i$95 \src2_i$64 - connect \src2_i$96 \src2_i$65 - connect \src2_i$97 \src2_i$66 - connect \src2_i$98 \src2_i$67 + connect \src2_i$104 \src2_i$72 + connect \src2_i$105 \src2_i$73 + connect \src2_i$106 \src2_i$74 + connect \src2_i$107 \src2_i$75 + connect \src2_i$108 \src2_i$76 connect \src3_i \fus_src3_i - connect \src3_i$99 \src3_i - connect \src3_i$100 \fus_src3_i$149 + connect \src3_i$109 \src3_i + connect \src3_i$110 \fus_src3_i$166 connect \src4_i \fus_src4_i - connect \src4_i$101 \fus_src4_i$150 - connect \src3_i$102 \fus_src3_i$151 - connect \src4_i$103 \fus_src4_i$152 - connect \rd__rel$104 \rd__rel$68 - connect \rd__go$105 \rd__go$69 - connect \src3_i$106 \fus_src3_i$153 - connect \src5_i \fus_src5_i + connect \src4_i$111 \fus_src4_i$167 connect \src6_i \fus_src6_i - connect \src1_i$107 \src1_i$71 - connect \src3_i$108 \fus_src3_i$154 - connect \src2_i$109 \src2_i$72 - connect \src4_i$110 \fus_src4_i$155 - connect \src4_i$111 \fus_src4_i$156 - connect \src5_i$112 \fus_src5_i$157 - connect \src6_i$113 \fus_src6_i$158 + connect \src4_i$112 \fus_src4_i$168 + connect \src5_i \fus_src5_i + connect \src3_i$113 \fus_src3_i$169 + connect \src4_i$114 \fus_src4_i$170 + connect \rd__rel$115 \rd__rel$77 + connect \rd__go$116 \rd__go$78 + connect \src3_i$117 \fus_src3_i$171 + connect \src5_i$118 \fus_src5_i$172 + connect \src6_i$119 \fus_src6_i$173 + connect \src1_i$120 \src1_i$80 + connect \src3_i$121 \fus_src3_i$174 + connect \src3_i$122 \fus_src3_i$175 + connect \src2_i$123 \src2_i$81 + connect \src4_i$124 \fus_src4_i$176 + connect \src4_i$125 \fus_src4_i$177 + connect \src5_i$126 \fus_src5_i$178 + connect \src6_i$127 \fus_src6_i$179 + connect \src2_i$128 \src2_i$82 connect \o_ok \fus_o_ok connect \wr__rel \wr__rel connect \wr__go \wr__go - connect \o_ok$114 \fus_o_ok$159 - connect \wr__rel$115 \wr__rel$73 - connect \wr__go$116 \wr__go$74 - connect \o_ok$117 \fus_o_ok$160 - connect \wr__rel$118 \wr__rel$75 - connect \wr__go$119 \wr__go$76 - connect \o_ok$120 \fus_o_ok$161 - connect \wr__rel$121 \wr__rel$77 - connect \wr__go$122 \wr__go$78 - connect \o_ok$123 \fus_o_ok$162 - connect \wr__rel$124 \wr__rel$79 - connect \wr__go$125 \wr__go$80 - connect \wr__rel$126 \wr__rel$81 - connect \wr__go$127 \wr__go$82 + connect \o_ok$129 \fus_o_ok$180 + connect \wr__rel$130 \wr__rel$83 + connect \wr__go$131 \wr__go$84 + connect \o_ok$132 \fus_o_ok$181 + connect \wr__rel$133 \wr__rel$85 + connect \wr__go$134 \wr__go$86 + connect \o_ok$135 \fus_o_ok$182 + connect \wr__rel$136 \wr__rel$87 + connect \wr__go$137 \wr__go$88 + connect \o_ok$138 \fus_o_ok$183 + connect \wr__rel$139 \wr__rel$89 + connect \wr__go$140 \wr__go$90 + connect \o_ok$141 \fus_o_ok$184 + connect \wr__rel$142 \wr__rel$91 + connect \wr__go$143 \wr__go$92 + connect \wr__rel$144 \wr__rel$93 + connect \wr__go$145 \wr__go$94 connect \o \fus_o - connect \o$128 \fus_o$163 - connect \o$129 \fus_o$164 - connect \o$130 \fus_o$165 - connect \o$131 \fus_o$166 - connect \o$132 \o - connect \ea \ea$83 + connect \o$146 \fus_o$185 + connect \o$147 \fus_o$186 + connect \o$148 \fus_o$187 + connect \o$149 \fus_o$188 + connect \o$150 \fus_o$189 + connect \o$151 \o + connect \ea \ea$95 connect \full_cr_ok \fus_full_cr_ok connect \full_cr \fus_full_cr connect \cr_a_ok \fus_cr_a_ok - connect \cr_a_ok$133 \fus_cr_a_ok$167 - connect \cr_a_ok$134 \fus_cr_a_ok$168 - connect \cr_a_ok$135 \fus_cr_a_ok$169 + connect \cr_a_ok$152 \fus_cr_a_ok$190 + connect \cr_a_ok$153 \fus_cr_a_ok$191 + connect \cr_a_ok$154 \fus_cr_a_ok$192 connect \cr_a \fus_cr_a - connect \cr_a$136 \fus_cr_a$170 - connect \cr_a$137 \fus_cr_a$171 - connect \cr_a$138 \fus_cr_a$172 + connect \cr_a$155 \fus_cr_a$193 + connect \cr_a$156 \fus_cr_a$194 + connect \cr_a$157 \fus_cr_a$195 connect \xer_ca_ok \fus_xer_ca_ok - connect \xer_ca_ok$139 \fus_xer_ca_ok$173 - connect \xer_ca_ok$140 \fus_xer_ca_ok$174 + connect \xer_ca_ok$158 \fus_xer_ca_ok$196 + connect \xer_ca_ok$159 \fus_xer_ca_ok$197 + connect \xer_ca_ok$160 \fus_xer_ca_ok$198 connect \xer_ca \fus_xer_ca - connect \xer_ca$141 \fus_xer_ca$175 - connect \xer_ca$142 \fus_xer_ca$176 + connect \xer_ca$161 \fus_xer_ca$199 + connect \xer_ca$162 \fus_xer_ca$200 + connect \xer_ca$163 \fus_xer_ca$201 connect \xer_ov_ok \fus_xer_ov_ok + connect \xer_ov_ok$164 \fus_xer_ov_ok$202 connect \xer_ov \fus_xer_ov + connect \xer_ov$165 \fus_xer_ov$203 connect \xer_so_ok \fus_xer_so_ok + connect \xer_so_ok$166 \fus_xer_so_ok$204 connect \xer_so \fus_xer_so - connect \spr1_ok \fus_spr1_ok - connect \wr__rel$143 \wr__rel$84 - connect \wr__go$144 \wr__go$85 - connect \spr1_ok$145 \fus_spr1_ok$177 - connect \spr1 \fus_spr1 - connect \spr1$146 \fus_spr1$178 - connect \spr2_ok \fus_spr2_ok - connect \spr2_ok$147 \fus_spr2_ok$179 - connect \spr2 \fus_spr2 - connect \spr2$148 \fus_spr2$180 + connect \xer_so$167 \fus_xer_so$205 + connect \fast1_ok \fus_fast1_ok + connect \wr__rel$168 \wr__rel$96 + connect \wr__go$169 \wr__go$97 + connect \fast1_ok$170 \fus_fast1_ok$206 + connect \fast1_ok$171 \fus_fast1_ok$207 + connect \fast1 \fus_fast1 + connect \fast1$172 \fus_fast1$208 + connect \fast1$173 \fus_fast1$209 + connect \fast2_ok \fus_fast2_ok + connect \fast2_ok$174 \fus_fast2_ok$210 + connect \fast2 \fus_fast2 + connect \fast2$175 \fus_fast2$211 connect \nia_ok \fus_nia_ok - connect \nia_ok$149 \fus_nia_ok$181 + connect \nia_ok$176 \fus_nia_ok$212 connect \nia \fus_nia - connect \nia$150 \fus_nia$182 + connect \nia$177 \fus_nia$213 connect \msr_ok \fus_msr_ok connect \msr \fus_msr + connect \spr1_ok \fus_spr1_ok + connect \spr1 \fus_spr1 connect \go_die_i \go_die_i connect \shadown_i \shadown_i connect \dest1_o \dest1_o - connect \go_die_i$151 \go_die_i$89 - connect \shadown_i$152 \shadown_i$90 - connect \dest1_o$153 \dest1_o$91 - connect \go_die_i$154 \go_die_i$92 - connect \shadown_i$155 \shadown_i$93 - connect \dest1_o$156 \dest1_o$94 - connect \go_die_i$157 \go_die_i$95 - connect \shadown_i$158 \shadown_i$96 - connect \dest1_o$159 \dest1_o$97 - connect \go_die_i$160 \go_die_i$98 - connect \shadown_i$161 \shadown_i$99 - connect \dest1_o$162 \dest1_o$100 - connect \go_die_i$163 \go_die_i$101 - connect \shadown_i$164 \shadown_i$102 - connect \dest1_o$165 \dest1_o$103 - connect \go_die_i$166 \go_die_i$104 + connect \go_die_i$178 \go_die_i$102 + connect \shadown_i$179 \shadown_i$103 + connect \dest1_o$180 \dest1_o$104 + connect \go_die_i$181 \go_die_i$105 + connect \shadown_i$182 \shadown_i$106 + connect \dest1_o$183 \dest1_o$107 + connect \go_die_i$184 \go_die_i$108 + connect \shadown_i$185 \shadown_i$109 + connect \dest1_o$186 \dest1_o$110 + connect \go_die_i$187 \go_die_i$111 + connect \shadown_i$188 \shadown_i$112 + connect \dest1_o$189 \dest1_o$113 + connect \go_die_i$190 \go_die_i$114 + connect \shadown_i$191 \shadown_i$115 + connect \dest1_o$192 \dest1_o$116 + connect \go_die_i$193 \go_die_i$117 + connect \shadown_i$194 \shadown_i$118 + connect \dest1_o$195 \dest1_o$119 + connect \go_die_i$196 \go_die_i$120 connect \load_mem_o \load_mem_o connect \stwd_mem_o \stwd_mem_o - connect \shadown_i$167 \shadown_i$105 + connect \shadown_i$197 \shadown_i$121 connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i connect \ldst_port0_is_st_i \ldst_port0_is_st_i connect \ldst_port0_data_len \ldst_port0_data_len @@ -129027,30 +137820,30 @@ module \core connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok connect \ldst_port0_st_data_i \ldst_port0_st_data_i connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok - connect \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i$106 + connect \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i$122 connect \ldst_port0_busy_o \ldst_port0_busy_o - connect \ldst_port0_is_st_i$2 \ldst_port0_is_st_i$107 - connect \ldst_port0_data_len$3 \ldst_port0_data_len$108 - connect \ldst_port0_addr_i$4 \ldst_port0_addr_i$109 - connect \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok$110 + connect \ldst_port0_is_st_i$2 \ldst_port0_is_st_i$123 + connect \ldst_port0_data_len$3 \ldst_port0_data_len$124 + connect \ldst_port0_addr_i$4 \ldst_port0_addr_i$125 + connect \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok$126 connect \x_mask_i \x_mask_i connect \x_addr_i \x_addr_i - connect \ldst_port0_addr_ok_o$6 \ldst_port0_addr_ok_o$111 + connect \ldst_port0_addr_ok_o$6 \ldst_port0_addr_ok_o$127 connect \m_ld_data_o \m_ld_data_o - connect \ldst_port0_ld_data_o$7 \ldst_port0_ld_data_o$112 - connect \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o_ok$113 + connect \ldst_port0_ld_data_o$7 \ldst_port0_ld_data_o$128 + connect \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o_ok$129 connect \x_busy_o \x_busy_o - connect \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i_ok$114 - connect \ldst_port0_st_data_i$10 \ldst_port0_st_data_i$115 + connect \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i_ok$130 + connect \ldst_port0_st_data_i$10 \ldst_port0_st_data_i$131 connect \x_st_data_i \x_st_data_i - connect \ldst_port0_addr_exc_o$11 \ldst_port0_addr_exc_o$116 + connect \ldst_port0_addr_exc_o$11 \ldst_port0_addr_exc_o$132 connect \x_ld_i \x_ld_i connect \x_st_i \x_st_i connect \m_valid_i \m_valid_i connect \x_valid_i \x_valid_i connect \ldst_port0_go_die_i \ldst_port0_go_die_i - connect \ldst_port0_go_die_i$12 \ldst_port0_go_die_i$117 - connect \ldst_port0_busy_o$13 \ldst_port0_busy_o$118 + connect \ldst_port0_go_die_i$12 \ldst_port0_go_die_i$133 + connect \ldst_port0_busy_o$13 \ldst_port0_busy_o$134 connect \dbus__cyc \dbus__cyc connect \x_stall_i \x_stall_i connect \dbus__ack \dbus__ack @@ -129088,13 +137881,13 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \int_data_i$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \int_wen$183 + wire width 32 \int_wen$214 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \int_wen$183$next + wire width 32 \int_wen$214$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_data_i$184 + wire width 64 \int_data_i$215 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_data_i$184$next + wire width 64 \int_data_i$215$next cell \int \int connect \rst \rst connect \clk \clk @@ -129106,8 +137899,8 @@ module \core connect \src3__data_o \int_src3__data_o connect \wen \int_wen connect \data_i \int_data_i - connect \wen$1 \int_wen$183 - connect \data_i$2 \int_data_i$184 + connect \wen$1 \int_wen$214 + connect \data_i$2 \int_data_i$215 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 8 \cr_full_rd__ren @@ -129166,6 +137959,10 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 \xer_src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \xer_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \xer_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 3 \xer_wen attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 3 \xer_wen$next @@ -129174,21 +137971,21 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 2 \xer_data_i$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$185 + wire width 3 \xer_wen$216 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$185$next + wire width 3 \xer_wen$216$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$186 + wire width 2 \xer_data_i$217 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$186$next + wire width 2 \xer_data_i$217$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$187 + wire width 3 \xer_wen$218 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$187$next + wire width 3 \xer_wen$218$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$188 + wire width 2 \xer_data_i$219 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$188$next + wire width 2 \xer_data_i$219$next cell \xer \xer connect \rst \rst connect \clk \clk @@ -129196,12 +137993,14 @@ module \core connect \src1__data_o \xer_src1__data_o connect \src2__ren \xer_src2__ren connect \src2__data_o \xer_src2__data_o + connect \src3__ren \xer_src3__ren + connect \src3__data_o \xer_src3__data_o connect \wen \xer_wen connect \data_i \xer_data_i - connect \wen$1 \xer_wen$185 - connect \data_i$2 \xer_data_i$186 - connect \wen$3 \xer_wen$187 - connect \data_i$4 \xer_data_i$188 + connect \wen$1 \xer_wen$216 + connect \data_i$2 \xer_data_i$217 + connect \wen$3 \xer_wen$218 + connect \data_i$4 \xer_data_i$219 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 8 \fast_src3__ren @@ -129228,25 +138027,25 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \fast_data_i$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \fast_wen$189 + wire width 8 \fast_wen$220 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \fast_wen$189$next + wire width 8 \fast_wen$220$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_data_i$190 + wire width 64 \fast_data_i$221 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_data_i$190$next + wire width 64 \fast_data_i$221$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_data_i$191 + wire width 64 \fast_data_i$222 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_data_i$191$next + wire width 64 \fast_data_i$222$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \fast_wen$192 + wire width 8 \fast_wen$223 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \fast_wen$192$next + wire width 8 \fast_wen$223$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_data_i$193 + wire width 64 \fast_data_i$224 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_data_i$193$next + wire width 64 \fast_data_i$224$next cell \fast \fast connect \d_rd1__ren \d_rd1__ren connect \d_rd1__data_o \d_rd1__data_o @@ -129265,22 +138064,38 @@ module \core connect \src2__data_o \fast_src2__data_o connect \wen$1 \fast_wen connect \data_i$2 \fast_data_i - connect \wen$3 \fast_wen$189 - connect \data_i$4 \fast_data_i$190 - connect \data_i$5 \fast_data_i$191 - connect \wen$6 \fast_wen$192 - connect \data_i$7 \fast_data_i$193 + connect \wen$3 \fast_wen$220 + connect \data_i$4 \fast_data_i$221 + connect \data_i$5 \fast_data_i$222 + connect \wen$6 \fast_wen$223 + connect \data_i$7 \fast_data_i$224 end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \spr_src__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \spr_src__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \spr_dest__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 1 \spr_dest__wen$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \spr_dest__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \spr_dest__data_i$next cell \spr \spr connect \rst \rst connect \clk \clk + connect \src__ren \spr_src__ren + connect \src__data_o \spr_src__data_o + connect \dest__wen \spr_dest__wen + connect \dest__data_i \spr_dest__data_i end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \rdpick_INT_ra_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 6 \rdpick_INT_ra_i + wire width 7 \rdpick_INT_ra_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 6 \rdpick_INT_ra_o + wire width 7 \rdpick_INT_ra_o cell \rdpick_INT_ra \rdpick_INT_ra connect \en_o \rdpick_INT_ra_en_o connect \i \rdpick_INT_ra_i @@ -129311,9 +138126,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \rdpick_XER_xer_so_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \rdpick_XER_xer_so_i + wire width 2 \rdpick_XER_xer_so_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \rdpick_XER_xer_so_o + wire width 2 \rdpick_XER_xer_so_o cell \rdpick_XER_xer_so \rdpick_XER_xer_so connect \en_o \rdpick_XER_xer_so_en_o connect \i \rdpick_XER_xer_so_i @@ -129322,15 +138137,26 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \rdpick_XER_xer_ca_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 2 \rdpick_XER_xer_ca_i + wire width 3 \rdpick_XER_xer_ca_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 \rdpick_XER_xer_ca_o + wire width 3 \rdpick_XER_xer_ca_o cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca connect \en_o \rdpick_XER_xer_ca_en_o connect \i \rdpick_XER_xer_ca_i connect \o \rdpick_XER_xer_ca_o end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_XER_xer_ov_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 \rdpick_XER_xer_ov_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 \rdpick_XER_xer_ov_o + cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov + connect \en_o \rdpick_XER_xer_ov_en_o + connect \i \rdpick_XER_xer_ov_i + connect \o \rdpick_XER_xer_ov_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \rdpick_CR_full_cr_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" wire width 1 \rdpick_CR_full_cr_i @@ -129375,26 +138201,26 @@ module \core connect \o \rdpick_CR_cr_c_o end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \rdpick_FAST_spr1_en_o + wire width 1 \rdpick_FAST_fast1_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 2 \rdpick_FAST_spr1_i + wire width 3 \rdpick_FAST_fast1_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 \rdpick_FAST_spr1_o - cell \rdpick_FAST_spr1 \rdpick_FAST_spr1 - connect \en_o \rdpick_FAST_spr1_en_o - connect \i \rdpick_FAST_spr1_i - connect \o \rdpick_FAST_spr1_o + wire width 3 \rdpick_FAST_fast1_o + cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 + connect \en_o \rdpick_FAST_fast1_en_o + connect \i \rdpick_FAST_fast1_i + connect \o \rdpick_FAST_fast1_o end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \rdpick_FAST_spr2_en_o + wire width 1 \rdpick_FAST_fast2_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 2 \rdpick_FAST_spr2_i + wire width 2 \rdpick_FAST_fast2_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 \rdpick_FAST_spr2_o - cell \rdpick_FAST_spr2 \rdpick_FAST_spr2 - connect \en_o \rdpick_FAST_spr2_en_o - connect \i \rdpick_FAST_spr2_i - connect \o \rdpick_FAST_spr2_o + wire width 2 \rdpick_FAST_fast2_o + cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 + connect \en_o \rdpick_FAST_fast2_en_o + connect \i \rdpick_FAST_fast2_i + connect \o \rdpick_FAST_fast2_o end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \rdpick_FAST_cia_en_o @@ -129419,11 +138245,22 @@ module \core connect \o \rdpick_FAST_msr_o end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \rdpick_SPR_spr1_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 \rdpick_SPR_spr1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 \rdpick_SPR_spr1_o + cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 + connect \en_o \rdpick_SPR_spr1_en_o + connect \i \rdpick_SPR_spr1_i + connect \o \rdpick_SPR_spr1_o + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \wrpick_INT_o_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 6 \wrpick_INT_o_i + wire width 7 \wrpick_INT_o_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 6 \wrpick_INT_o_o + wire width 7 \wrpick_INT_o_o cell \wrpick_INT_o \wrpick_INT_o connect \en_o \wrpick_INT_o_en_o connect \i \wrpick_INT_o_i @@ -129465,9 +138302,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \wrpick_XER_xer_ca_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 3 \wrpick_XER_xer_ca_i + wire width 4 \wrpick_XER_xer_ca_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 3 \wrpick_XER_xer_ca_o + wire width 4 \wrpick_XER_xer_ca_o cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca connect \en_o \wrpick_XER_xer_ca_en_o connect \i \wrpick_XER_xer_ca_i @@ -129476,9 +138313,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \wrpick_XER_xer_ov_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \wrpick_XER_xer_ov_i + wire width 2 \wrpick_XER_xer_ov_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \wrpick_XER_xer_ov_o + wire width 2 \wrpick_XER_xer_ov_o cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov connect \en_o \wrpick_XER_xer_ov_en_o connect \i \wrpick_XER_xer_ov_i @@ -129487,35 +138324,35 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \wrpick_XER_xer_so_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 1 \wrpick_XER_xer_so_i + wire width 2 \wrpick_XER_xer_so_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 1 \wrpick_XER_xer_so_o + wire width 2 \wrpick_XER_xer_so_o cell \wrpick_XER_xer_so \wrpick_XER_xer_so connect \en_o \wrpick_XER_xer_so_en_o connect \i \wrpick_XER_xer_so_i connect \o \wrpick_XER_xer_so_o end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \wrpick_FAST_spr1_en_o + wire width 1 \wrpick_FAST_fast1_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 2 \wrpick_FAST_spr1_i + wire width 3 \wrpick_FAST_fast1_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 \wrpick_FAST_spr1_o - cell \wrpick_FAST_spr1 \wrpick_FAST_spr1 - connect \en_o \wrpick_FAST_spr1_en_o - connect \i \wrpick_FAST_spr1_i - connect \o \wrpick_FAST_spr1_o + wire width 3 \wrpick_FAST_fast1_o + cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 + connect \en_o \wrpick_FAST_fast1_en_o + connect \i \wrpick_FAST_fast1_i + connect \o \wrpick_FAST_fast1_o end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" - wire width 1 \wrpick_FAST_spr2_en_o + wire width 1 \wrpick_FAST_fast2_en_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" - wire width 2 \wrpick_FAST_spr2_i + wire width 2 \wrpick_FAST_fast2_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" - wire width 2 \wrpick_FAST_spr2_o - cell \wrpick_FAST_spr2 \wrpick_FAST_spr2 - connect \en_o \wrpick_FAST_spr2_en_o - connect \i \wrpick_FAST_spr2_i - connect \o \wrpick_FAST_spr2_o + wire width 2 \wrpick_FAST_fast2_o + cell \wrpick_FAST_fast2 \wrpick_FAST_fast2 + connect \en_o \wrpick_FAST_fast2_en_o + connect \i \wrpick_FAST_fast2_i + connect \o \wrpick_FAST_fast2_o end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" wire width 1 \wrpick_FAST_nia_en_o @@ -129539,64 +138376,75 @@ module \core connect \i \wrpick_FAST_msr_i connect \o \wrpick_FAST_msr_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35" + wire width 1 \wrpick_SPR_spr1_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33" + wire width 1 \wrpick_SPR_spr1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34" + wire width 1 \wrpick_SPR_spr1_o + cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 + connect \en_o \wrpick_SPR_spr1_en_o + connect \i \wrpick_SPR_spr1_i + connect \o \wrpick_SPR_spr1_o + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire width 1 \en_alu0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 11 $226 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $227 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 2 - parameter \Y_WIDTH 10 + parameter \Y_WIDTH 11 connect \A \fn_unit connect \B 2'10 - connect \Y $195 + connect \Y $226 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $reduce_bool $228 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $195 - connect \Y $194 + connect \A $226 + connect \Y $225 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $194 - connect \Y $198 + connect \B $225 + connect \Y $229 end process $group_0 assign \en_alu0 1'0 - assign \en_alu0 $198 + assign \en_alu0 $229 sync init end process $group_1 assign \oper_i__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__insn_type \insn_type end sync init end process $group_2 - assign \fus_oper_i__fn_unit 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_oper_i__fn_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \fus_oper_i__fn_unit \fn_unit end @@ -129605,9 +138453,9 @@ module \core process $group_3 assign \fus_oper_i__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000 assign \fus_oper_i__imm_data__imm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign { \fus_oper_i__imm_data__imm_ok \fus_oper_i__imm_data__imm } { \imm_ok \imm } end @@ -129615,9 +138463,9 @@ module \core end process $group_5 assign \oper_i__lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__lk \lk end @@ -129626,9 +138474,9 @@ module \core process $group_6 assign \fus_oper_i__rc__rc 1'0 assign \fus_oper_i__rc__rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign { \fus_oper_i__rc__rc_ok \fus_oper_i__rc__rc } { \rc_ok \rc } end @@ -129637,9 +138485,9 @@ module \core process $group_8 assign \fus_oper_i__oe__oe 1'0 assign \fus_oper_i__oe__oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign { \fus_oper_i__oe__oe_ok \fus_oper_i__oe__oe } { \oe_ok \oe } end @@ -129647,9 +138495,9 @@ module \core end process $group_10 assign \oper_i__invert_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__invert_a \invert_a end @@ -129657,9 +138505,9 @@ module \core end process $group_11 assign \fus_oper_i__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \fus_oper_i__zero_a \zero_a end @@ -129667,9 +138515,9 @@ module \core end process $group_12 assign \oper_i__invert_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__invert_out \invert_out end @@ -129678,9 +138526,9 @@ module \core process $group_13 assign \fus_oper_i__write_cr__data 3'000 assign \fus_oper_i__write_cr__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign { \fus_oper_i__write_cr__ok \fus_oper_i__write_cr__data } { \cr_out_ok \cr_out } end @@ -129688,9 +138536,9 @@ module \core end process $group_15 assign \oper_i__input_carry 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__input_carry \input_carry end @@ -129698,9 +138546,9 @@ module \core end process $group_16 assign \oper_i__output_carry 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__output_carry \output_carry end @@ -129708,9 +138556,9 @@ module \core end process $group_17 assign \oper_i__input_cr 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__input_cr \input_cr end @@ -129718,9 +138566,9 @@ module \core end process $group_18 assign \oper_i__output_cr 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__output_cr \output_cr end @@ -129728,9 +138576,9 @@ module \core end process $group_19 assign \oper_i__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__is_32bit \is_32bit end @@ -129738,9 +138586,9 @@ module \core end process $group_20 assign \oper_i__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__is_signed \is_signed end @@ -129748,9 +138596,9 @@ module \core end process $group_21 assign \oper_i__data_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__data_len \data_len end @@ -129758,9 +138606,9 @@ module \core end process $group_22 assign \fus_oper_i__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \fus_oper_i__insn \insn end @@ -129768,9 +138616,9 @@ module \core end process $group_23 assign \oper_i__byte_reverse 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__byte_reverse \byte_reverse end @@ -129778,9 +138626,9 @@ module \core end process $group_24 assign \oper_i__sign_extend 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__sign_extend \sign_extend end @@ -129788,78 +138636,86 @@ module \core end process $group_25 assign \issue_i$1 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \issue_i$1 \issue_i end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire width 1 \en_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire width 1 \en_branch0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire width 1 \en_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire width 1 \en_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" + wire width 1 \en_spr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire width 1 \en_shiftrot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" wire width 1 \en_ldst0 process $group_26 assign \corebusy_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \corebusy_o \busy_o end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_cr0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \corebusy_o \busy_o$4 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_branch0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \corebusy_o \busy_o$12 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_trap0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \corebusy_o \busy_o$18 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \corebusy_o \busy_o$30 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + switch { \en_spr0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + case 1'1 + assign \corebusy_o \busy_o$36 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \corebusy_o \busy_o$39 + assign \corebusy_o \busy_o$45 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_ldst0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \corebusy_o \busy_o$47 + assign \corebusy_o \busy_o$53 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 4 $200 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + wire width 4 $231 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71" - wire width 1 $201 + wire width 1 $232 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71" - cell $and $202 + cell $and $233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -129867,12 +138723,12 @@ module \core parameter \Y_WIDTH 1 connect \A \oe connect \B \oe_ok - connect \Y $201 + connect \Y $232 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" - wire width 1 $203 + wire width 1 $234 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" - cell $eq $204 + cell $eq $235 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -129880,95 +138736,96 @@ module \core parameter \Y_WIDTH 1 connect \A \input_carry connect \B 2'10 - connect \Y $203 + connect \Y $234 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + cell $not $236 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A { $203 $201 \reg2_ok \reg1_ok } - connect \Y $200 + connect \A { $234 $232 \reg2_ok \reg1_ok } + connect \Y $231 end process $group_27 assign \fus_rdmaskn 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_alu0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \fus_rdmaskn $200 + assign \fus_rdmaskn $231 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104" - wire width 7 \fu_enable + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103" + wire width 8 \fu_enable process $group_28 - assign \fu_enable 7'0000000 + assign \fu_enable 8'00000000 assign \fu_enable [0] \en_alu0 assign \fu_enable [1] \en_cr0 assign \fu_enable [2] \en_branch0 assign \fu_enable [3] \en_trap0 assign \fu_enable [4] \en_logical0 - assign \fu_enable [5] \en_shiftrot0 - assign \fu_enable [6] \en_ldst0 + assign \fu_enable [5] \en_spr0 + assign \fu_enable [6] \en_shiftrot0 + assign \fu_enable [7] \en_ldst0 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $207 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $237 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 11 $238 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $239 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 7 - parameter \Y_WIDTH 10 + parameter \Y_WIDTH 11 connect \A \fn_unit connect \B 7'1000000 - connect \Y $207 + connect \Y $238 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $reduce_bool $240 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $207 - connect \Y $206 + connect \A $238 + connect \Y $237 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $241 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $206 - connect \Y $210 + connect \B $237 + connect \Y $241 end process $group_29 assign \en_cr0 1'0 - assign \en_cr0 $210 + assign \en_cr0 $241 sync init end process $group_30 assign \oper_i__insn_type$2 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_cr0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__insn_type$2 \insn_type end sync init end process $group_31 - assign \oper_i__fn_unit 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \oper_i__fn_unit 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_cr0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__fn_unit \fn_unit end @@ -129976,9 +138833,9 @@ module \core end process $group_32 assign \oper_i__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_cr0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__insn \insn end @@ -129986,9 +138843,9 @@ module \core end process $group_33 assign \oper_i__read_cr_whole 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_cr0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__read_cr_whole \read_cr_whole end @@ -129996,9 +138853,9 @@ module \core end process $group_34 assign \oper_i__write_cr_whole 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_cr0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__write_cr_whole \write_cr_whole end @@ -130006,111 +138863,111 @@ module \core end process $group_35 assign \issue_i$3 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_cr0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \issue_i$3 \issue_i end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 6 $212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $213 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + wire width 6 $243 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + cell $not $244 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { \cr_in2_ok$5 \cr_in2_ok \cr_in1_ok \read_cr_whole \reg2_ok \reg1_ok } - connect \Y $212 + connect \Y $243 end process $group_36 - assign \fus_rdmaskn$119 6'000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_rdmaskn$135 6'000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_cr0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \fus_rdmaskn$119 $212 + assign \fus_rdmaskn$135 $243 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $215 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $245 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 11 $246 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $247 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 6 - parameter \Y_WIDTH 10 + parameter \Y_WIDTH 11 connect \A \fn_unit connect \B 6'100000 - connect \Y $215 + connect \Y $246 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $reduce_bool $248 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $215 - connect \Y $214 + connect \A $246 + connect \Y $245 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $214 - connect \Y $218 + connect \B $245 + connect \Y $249 end process $group_37 assign \en_branch0 1'0 - assign \en_branch0 $218 + assign \en_branch0 $249 sync init end process $group_38 assign \oper_i__insn_type$6 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_branch0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__insn_type$6 \insn_type end sync init end process $group_39 - assign \oper_i__fn_unit$7 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \oper_i__fn_unit$7 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_branch0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__fn_unit$7 \fn_unit end sync init end process $group_40 - assign \fus_oper_i__imm_data__imm$120 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i__imm_data__imm_ok$121 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_oper_i__imm_data__imm$136 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i__imm_data__imm_ok$137 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_branch0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign { \fus_oper_i__imm_data__imm_ok$121 \fus_oper_i__imm_data__imm$120 } { \imm_ok \imm } + assign { \fus_oper_i__imm_data__imm_ok$137 \fus_oper_i__imm_data__imm$136 } { \imm_ok \imm } end sync init end process $group_42 assign \oper_i__lk$8 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_branch0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__lk$8 \lk end @@ -130118,9 +138975,9 @@ module \core end process $group_43 assign \oper_i__is_32bit$9 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_branch0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__is_32bit$9 \is_32bit end @@ -130128,9 +138985,9 @@ module \core end process $group_44 assign \oper_i__insn$10 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_branch0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__insn$10 \insn end @@ -130138,90 +138995,90 @@ module \core end process $group_45 assign \issue_i$11 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_branch0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \issue_i$11 \issue_i end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 4 $220 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $221 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + wire width 4 $251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + cell $not $252 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 1'1 \cr_in1_ok \fast2_ok \fast1_ok } - connect \Y $220 + connect \Y $251 end process $group_46 - assign \fus_rdmaskn$122 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_rdmaskn$138 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_branch0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \fus_rdmaskn$122 $220 + assign \fus_rdmaskn$138 $251 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $223 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 11 $254 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $255 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 8 - parameter \Y_WIDTH 10 + parameter \Y_WIDTH 11 connect \A \fn_unit connect \B 8'10000000 - connect \Y $223 + connect \Y $254 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $reduce_bool $256 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $223 - connect \Y $222 + connect \A $254 + connect \Y $253 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $226 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $227 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $257 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $222 - connect \Y $226 + connect \B $253 + connect \Y $257 end process $group_47 assign \en_trap0 1'0 - assign \en_trap0 $226 + assign \en_trap0 $257 sync init end process $group_48 assign \oper_i__insn_type$13 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_trap0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__insn_type$13 \insn_type end sync init end process $group_49 - assign \oper_i__fn_unit$14 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \oper_i__fn_unit$14 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_trap0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__fn_unit$14 \fn_unit end @@ -130229,9 +139086,9 @@ module \core end process $group_50 assign \oper_i__insn$15 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_trap0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__insn$15 \insn end @@ -130239,19 +139096,19 @@ module \core end process $group_51 assign \oper_i__is_32bit$16 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_trap0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__is_32bit$16 \is_32bit end sync init end process $group_52 - assign \oper_i__traptype 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \oper_i__traptype 5'00000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_trap0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__traptype \traptype end @@ -130259,9 +139116,9 @@ module \core end process $group_53 assign \oper_i__trapaddr 13'0000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_trap0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__trapaddr \trapaddr end @@ -130269,163 +139126,163 @@ module \core end process $group_54 assign \issue_i$17 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_trap0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \issue_i$17 \issue_i end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 6 $228 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + wire width 6 $259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + cell $not $260 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 1'1 1'1 \fast2_ok \fast1_ok \reg2_ok \reg1_ok } - connect \Y $228 + connect \Y $259 end process $group_55 - assign \fus_rdmaskn$123 6'000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_rdmaskn$139 6'000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_trap0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \fus_rdmaskn$123 $228 + assign \fus_rdmaskn$139 $259 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $230 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $231 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $232 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 11 $262 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $263 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 5 - parameter \Y_WIDTH 10 + parameter \Y_WIDTH 11 connect \A \fn_unit connect \B 5'10000 - connect \Y $231 + connect \Y $262 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $233 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $reduce_bool $264 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $231 - connect \Y $230 + connect \A $262 + connect \Y $261 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $234 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $235 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $230 - connect \Y $234 + connect \B $261 + connect \Y $265 end process $group_56 assign \en_logical0 1'0 - assign \en_logical0 $234 + assign \en_logical0 $265 sync init end process $group_57 assign \oper_i__insn_type$19 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__insn_type$19 \insn_type end sync init end process $group_58 - assign \oper_i__fn_unit$20 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \oper_i__fn_unit$20 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__fn_unit$20 \fn_unit end sync init end process $group_59 - assign \fus_oper_i__imm_data__imm$124 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i__imm_data__imm_ok$125 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_oper_i__imm_data__imm$140 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i__imm_data__imm_ok$141 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign { \fus_oper_i__imm_data__imm_ok$125 \fus_oper_i__imm_data__imm$124 } { \imm_ok \imm } + assign { \fus_oper_i__imm_data__imm_ok$141 \fus_oper_i__imm_data__imm$140 } { \imm_ok \imm } end sync init end process $group_61 assign \oper_i__lk$21 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__lk$21 \lk end sync init end process $group_62 - assign \fus_oper_i__rc__rc$126 1'0 - assign \fus_oper_i__rc__rc_ok$127 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_oper_i__rc__rc$142 1'0 + assign \fus_oper_i__rc__rc_ok$143 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign { \fus_oper_i__rc__rc_ok$127 \fus_oper_i__rc__rc$126 } { \rc_ok \rc } + assign { \fus_oper_i__rc__rc_ok$143 \fus_oper_i__rc__rc$142 } { \rc_ok \rc } end sync init end process $group_64 - assign \fus_oper_i__oe__oe$128 1'0 - assign \fus_oper_i__oe__oe_ok$129 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_oper_i__oe__oe$144 1'0 + assign \fus_oper_i__oe__oe_ok$145 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign { \fus_oper_i__oe__oe_ok$129 \fus_oper_i__oe__oe$128 } { \oe_ok \oe } + assign { \fus_oper_i__oe__oe_ok$145 \fus_oper_i__oe__oe$144 } { \oe_ok \oe } end sync init end process $group_66 assign \oper_i__invert_a$22 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__invert_a$22 \invert_a end sync init end process $group_67 - assign \fus_oper_i__zero_a$130 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_oper_i__zero_a$146 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \fus_oper_i__zero_a$130 \zero_a + assign \fus_oper_i__zero_a$146 \zero_a end sync init end process $group_68 assign \oper_i__input_carry$23 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__input_carry$23 \input_carry end @@ -130433,30 +139290,30 @@ module \core end process $group_69 assign \oper_i__invert_out$24 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__invert_out$24 \invert_out end sync init end process $group_70 - assign \fus_oper_i__write_cr__data$131 3'000 - assign \fus_oper_i__write_cr__ok$132 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_oper_i__write_cr__data$147 3'000 + assign \fus_oper_i__write_cr__ok$148 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign { \fus_oper_i__write_cr__ok$132 \fus_oper_i__write_cr__data$131 } { \cr_out_ok \cr_out } + assign { \fus_oper_i__write_cr__ok$148 \fus_oper_i__write_cr__data$147 } { \cr_out_ok \cr_out } end sync init end process $group_72 assign \oper_i__output_carry$25 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__output_carry$25 \output_carry end @@ -130464,9 +139321,9 @@ module \core end process $group_73 assign \oper_i__is_32bit$26 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__is_32bit$26 \is_32bit end @@ -130474,9 +139331,9 @@ module \core end process $group_74 assign \oper_i__is_signed$27 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__is_signed$27 \is_signed end @@ -130484,245 +139341,395 @@ module \core end process $group_75 assign \oper_i__data_len$28 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__data_len$28 \data_len end sync init end process $group_76 - assign \fus_oper_i__insn$133 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_oper_i__insn$149 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \fus_oper_i__insn$133 \insn + assign \fus_oper_i__insn$149 \insn end sync init end process $group_77 assign \issue_i$29 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \issue_i$29 \issue_i end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 2 $236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $237 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + wire width 2 $267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + cell $not $268 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A { \reg2_ok \reg1_ok } - connect \Y $236 + connect \Y $267 end process $group_78 - assign \fus_rdmaskn$134 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_rdmaskn$150 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_logical0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \fus_rdmaskn$134 $236 + assign \fus_rdmaskn$150 $267 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $238 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $239 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $240 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $269 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 11 $270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $271 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 10 + parameter \B_WIDTH 11 + parameter \Y_WIDTH 11 connect \A \fn_unit - connect \B 4'1000 - connect \Y $239 + connect \B 11'10000000000 + connect \Y $270 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $241 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $reduce_bool $272 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $239 - connect \Y $238 + connect \A $270 + connect \Y $269 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $243 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $238 - connect \Y $242 + connect \B $269 + connect \Y $273 end process $group_79 - assign \en_shiftrot0 1'0 - assign \en_shiftrot0 $242 + assign \en_spr0 1'0 + assign \en_spr0 $273 sync init end process $group_80 assign \oper_i__insn_type$31 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + switch { \en_spr0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__insn_type$31 \insn_type end sync init end process $group_81 - assign \fus_oper_i__fn_unit$135 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \oper_i__fn_unit$32 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + switch { \en_spr0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \fus_oper_i__fn_unit$135 \fn_unit + assign \oper_i__fn_unit$32 \fn_unit end sync init end process $group_82 - assign \fus_oper_i__imm_data__imm$136 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i__imm_data__imm_ok$137 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \oper_i__insn$33 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + switch { \en_spr0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign { \fus_oper_i__imm_data__imm_ok$137 \fus_oper_i__imm_data__imm$136 } { \imm_ok \imm } + assign \oper_i__insn$33 \insn + end + sync init + end + process $group_83 + assign \oper_i__is_32bit$34 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + switch { \en_spr0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + case 1'1 + assign \oper_i__is_32bit$34 \is_32bit end sync init end process $group_84 - assign \fus_oper_i__rc__rc$138 1'0 - assign \fus_oper_i__rc__rc_ok$139 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" - switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \issue_i$35 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + switch { \en_spr0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + case 1'1 + assign \issue_i$35 \issue_i + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + wire width 6 $275 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71" + wire width 1 $276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71" + cell $and $277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oe + connect \B \oe_ok + connect \Y $276 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:73" + wire width 1 $278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:73" + cell $and $279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oe + connect \B \oe_ok + connect \Y $278 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" + wire width 1 $280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" + cell $eq $281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \input_carry + connect \B 2'10 + connect \Y $280 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + cell $not $282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { $280 $278 $276 \fast1_ok \spr1_ok \reg1_ok } + connect \Y $275 + end + process $group_85 + assign \fus_rdmaskn$151 6'000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + switch { \en_spr0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign { \fus_oper_i__rc__rc_ok$139 \fus_oper_i__rc__rc$138 } { \rc_ok \rc } + assign \fus_rdmaskn$151 $275 end sync init end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $283 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 11 $284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 11 + connect \A \fn_unit + connect \B 4'1000 + connect \Y $284 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $reduce_bool $286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 11 + parameter \Y_WIDTH 1 + connect \A $284 + connect \Y $283 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \valid + connect \B $283 + connect \Y $287 + end process $group_86 - assign \fus_oper_i__oe__oe$140 1'0 - assign \fus_oper_i__oe__oe_ok$141 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \en_shiftrot0 1'0 + assign \en_shiftrot0 $287 + sync init + end + process $group_87 + assign \oper_i__insn_type$37 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign { \fus_oper_i__oe__oe_ok$141 \fus_oper_i__oe__oe$140 } { \oe_ok \oe } + assign \oper_i__insn_type$37 \insn_type end sync init end process $group_88 - assign \fus_oper_i__write_cr__data$142 3'000 - assign \fus_oper_i__write_cr__ok$143 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_oper_i__fn_unit$152 11'00000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign { \fus_oper_i__write_cr__ok$143 \fus_oper_i__write_cr__data$142 } { \cr_out_ok \cr_out } + assign \fus_oper_i__fn_unit$152 \fn_unit end sync init end - process $group_90 - assign \oper_i__input_carry$32 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_89 + assign \fus_oper_i__imm_data__imm$153 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i__imm_data__imm_ok$154 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \oper_i__input_carry$32 \input_carry + assign { \fus_oper_i__imm_data__imm_ok$154 \fus_oper_i__imm_data__imm$153 } { \imm_ok \imm } end sync init end process $group_91 - assign \oper_i__output_carry$33 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + assign \fus_oper_i__rc__rc$155 1'0 + assign \fus_oper_i__rc__rc_ok$156 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \oper_i__output_carry$33 \output_carry + assign { \fus_oper_i__rc__rc_ok$156 \fus_oper_i__rc__rc$155 } { \rc_ok \rc } end sync init end - process $group_92 - assign \oper_i__input_cr$34 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_93 + assign \fus_oper_i__oe__oe$157 1'0 + assign \fus_oper_i__oe__oe_ok$158 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \oper_i__input_cr$34 \input_cr + assign { \fus_oper_i__oe__oe_ok$158 \fus_oper_i__oe__oe$157 } { \oe_ok \oe } end sync init end - process $group_93 - assign \oper_i__output_cr$35 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_95 + assign \fus_oper_i__write_cr__data$159 3'000 + assign \fus_oper_i__write_cr__ok$160 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \oper_i__output_cr$35 \output_cr + assign { \fus_oper_i__write_cr__ok$160 \fus_oper_i__write_cr__data$159 } { \cr_out_ok \cr_out } end sync init end - process $group_94 - assign \oper_i__is_32bit$36 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_97 + assign \oper_i__input_carry$38 2'00 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \oper_i__is_32bit$36 \is_32bit + assign \oper_i__input_carry$38 \input_carry end sync init end - process $group_95 - assign \oper_i__is_signed$37 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_98 + assign \oper_i__output_carry$39 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \oper_i__is_signed$37 \is_signed + assign \oper_i__output_carry$39 \output_carry end sync init end - process $group_96 - assign \fus_oper_i__insn$144 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_99 + assign \oper_i__input_cr$40 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \fus_oper_i__insn$144 \insn + assign \oper_i__input_cr$40 \input_cr end sync init end - process $group_97 - assign \issue_i$38 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_100 + assign \oper_i__output_cr$41 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \issue_i$38 \issue_i + assign \oper_i__output_cr$41 \output_cr end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 4 $244 + process $group_101 + assign \oper_i__is_32bit$42 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + switch { \en_shiftrot0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + case 1'1 + assign \oper_i__is_32bit$42 \is_32bit + end + sync init + end + process $group_102 + assign \oper_i__is_signed$43 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + switch { \en_shiftrot0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + case 1'1 + assign \oper_i__is_signed$43 \is_signed + end + sync init + end + process $group_103 + assign \fus_oper_i__insn$161 32'00000000000000000000000000000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + switch { \en_shiftrot0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + case 1'1 + assign \fus_oper_i__insn$161 \insn + end + sync init + end + process $group_104 + assign \issue_i$44 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + switch { \en_shiftrot0 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" + case 1'1 + assign \issue_i$44 \issue_i + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + wire width 4 $289 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" - wire width 1 $245 + wire width 1 $290 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" - cell $eq $246 + cell $eq $291 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -130730,199 +139737,199 @@ module \core parameter \Y_WIDTH 1 connect \A \input_carry connect \B 2'10 - connect \Y $245 + connect \Y $290 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $247 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + cell $not $292 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A { $245 \reg3_ok \reg2_ok \reg1_ok } - connect \Y $244 + connect \A { $290 \reg3_ok \reg2_ok \reg1_ok } + connect \Y $289 end - process $group_98 - assign \fus_rdmaskn$145 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_105 + assign \fus_rdmaskn$162 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_shiftrot0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \fus_rdmaskn$145 $244 + assign \fus_rdmaskn$162 $289 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $248 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 10 $249 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $293 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 11 $294 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $295 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \B_SIGNED 0 parameter \B_WIDTH 3 - parameter \Y_WIDTH 10 + parameter \Y_WIDTH 11 connect \A \fn_unit connect \B 3'100 - connect \Y $249 + connect \Y $294 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $reduce_bool $251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $reduce_bool $296 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 11 parameter \Y_WIDTH 1 - connect \A $249 - connect \Y $248 + connect \A $294 + connect \Y $293 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - wire width 1 $252 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" - cell $and $253 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + wire width 1 $297 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112" + cell $and $298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \valid - connect \B $248 - connect \Y $252 + connect \B $293 + connect \Y $297 end - process $group_99 + process $group_106 assign \en_ldst0 1'0 - assign \en_ldst0 $252 + assign \en_ldst0 $297 sync init end - process $group_100 - assign \oper_i__insn_type$40 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_107 + assign \oper_i__insn_type$46 7'0000000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_ldst0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \oper_i__insn_type$40 \insn_type + assign \oper_i__insn_type$46 \insn_type end sync init end - process $group_101 - assign \fus_oper_i__imm_data__imm$146 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i__imm_data__imm_ok$147 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_108 + assign \fus_oper_i__imm_data__imm$163 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_oper_i__imm_data__imm_ok$164 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_ldst0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign { \fus_oper_i__imm_data__imm_ok$147 \fus_oper_i__imm_data__imm$146 } { \imm_ok \imm } + assign { \fus_oper_i__imm_data__imm_ok$164 \fus_oper_i__imm_data__imm$163 } { \imm_ok \imm } end sync init end - process $group_103 + process $group_110 assign \oper_i__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_ldst0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__zero_a \zero_a end sync init end - process $group_104 - assign \oper_i__is_32bit$41 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_111 + assign \oper_i__is_32bit$47 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_ldst0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \oper_i__is_32bit$41 \is_32bit + assign \oper_i__is_32bit$47 \is_32bit end sync init end - process $group_105 - assign \oper_i__is_signed$42 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_112 + assign \oper_i__is_signed$48 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_ldst0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \oper_i__is_signed$42 \is_signed + assign \oper_i__is_signed$48 \is_signed end sync init end - process $group_106 - assign \oper_i__data_len$43 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_113 + assign \oper_i__data_len$49 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_ldst0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \oper_i__data_len$43 \data_len + assign \oper_i__data_len$49 \data_len end sync init end - process $group_107 - assign \oper_i__byte_reverse$44 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_114 + assign \oper_i__byte_reverse$50 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_ldst0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \oper_i__byte_reverse$44 \byte_reverse + assign \oper_i__byte_reverse$50 \byte_reverse end sync init end - process $group_108 - assign \oper_i__sign_extend$45 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_115 + assign \oper_i__sign_extend$51 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_ldst0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \oper_i__sign_extend$45 \sign_extend + assign \oper_i__sign_extend$51 \sign_extend end sync init end - process $group_109 + process $group_116 assign \oper_i__update 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_ldst0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 assign \oper_i__update \update end sync init end - process $group_110 - assign \issue_i$46 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_117 + assign \issue_i$52 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_ldst0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \issue_i$46 \issue_i + assign \issue_i$52 \issue_i end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - wire width 3 $254 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:119" - cell $not $255 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + wire width 3 $299 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118" + cell $not $300 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { \reg3_ok \reg2_ok \reg1_ok } - connect \Y $254 + connect \Y $299 end - process $group_111 - assign \fus_rdmaskn$148 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + process $group_118 + assign \fus_rdmaskn$165 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" switch { \en_ldst0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:114" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113" case 1'1 - assign \fus_rdmaskn$148 $254 + assign \fus_rdmaskn$165 $299 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" wire width 1 \rdflag_INT_ra - process $group_112 + process $group_119 assign \rdflag_INT_ra 1'0 assign \rdflag_INT_ra \reg1_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:47" - wire width 32 $256 + wire width 32 $301 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:47" - cell $sshl $257 + cell $sshl $302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -130930,22 +139937,22 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \reg1 - connect \Y $256 + connect \Y $301 end - process $group_113 + process $group_120 assign \int_src1__ren 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" switch { \rdpick_INT_ra_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" case 1'1 - assign \int_src1__ren $256 + assign \int_src1__ren $301 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $258 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $259 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -130953,251 +139960,293 @@ module \core parameter \Y_WIDTH 1 connect \A \rd__rel [0] connect \B \fu_enable [0] - connect \Y $258 + connect \Y $303 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $260 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $258 + connect \A $303 connect \B \rdflag_INT_ra - connect \Y $260 + connect \Y $305 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $263 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$48 [0] + connect \A \rd__rel$54 [0] connect \B \fu_enable [1] - connect \Y $262 + connect \Y $307 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $264 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $265 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $309 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $262 + connect \A $307 connect \B \rdflag_INT_ra - connect \Y $264 + connect \Y $309 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $266 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$51 [0] + connect \A \rd__rel$57 [0] connect \B \fu_enable [3] - connect \Y $266 + connect \Y $311 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $268 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $269 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $313 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $266 + connect \A $311 connect \B \rdflag_INT_ra - connect \Y $268 + connect \Y $313 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $315 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$54 [0] + connect \A \rd__rel$60 [0] connect \B \fu_enable [4] - connect \Y $270 + connect \Y $315 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $272 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $317 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $270 + connect \A $315 connect \B \rdflag_INT_ra - connect \Y $272 + connect \Y $317 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $274 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $275 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $319 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$57 [0] + connect \A \rd__rel$63 [0] connect \B \fu_enable [5] - connect \Y $274 + connect \Y $319 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $276 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $277 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $321 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $274 + connect \A $319 connect \B \rdflag_INT_ra - connect \Y $276 + connect \Y $321 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $278 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $323 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$60 [0] + connect \A \rd__rel$66 [0] connect \B \fu_enable [6] - connect \Y $278 + connect \Y $323 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $280 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $325 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $278 + connect \A $323 connect \B \rdflag_INT_ra - connect \Y $280 + connect \Y $325 end - process $group_114 - assign \rdpick_INT_ra_i 6'000000 - assign \rdpick_INT_ra_i [0] $260 - assign \rdpick_INT_ra_i [1] $264 - assign \rdpick_INT_ra_i [2] $268 - assign \rdpick_INT_ra_i [3] $272 - assign \rdpick_INT_ra_i [4] $276 - assign \rdpick_INT_ra_i [5] $280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rd__rel$69 [0] + connect \B \fu_enable [7] + connect \Y $327 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $327 + connect \B \rdflag_INT_ra + connect \Y $329 + end + process $group_121 + assign \rdpick_INT_ra_i 7'0000000 + assign \rdpick_INT_ra_i [0] $305 + assign \rdpick_INT_ra_i [1] $309 + assign \rdpick_INT_ra_i [2] $313 + assign \rdpick_INT_ra_i [3] $317 + assign \rdpick_INT_ra_i [4] $321 + assign \rdpick_INT_ra_i [5] $325 + assign \rdpick_INT_ra_i [6] $329 sync init end - process $group_115 + process $group_122 assign \rd__go 4'0000 assign \rd__go [0] \rdpick_INT_ra_o [0] assign \rd__go [1] \rdpick_INT_rb_o [0] - assign \rd__go [2] \rdpick_XER_xer_so_o + assign \rd__go [2] \rdpick_XER_xer_so_o [0] assign \rd__go [3] \rdpick_XER_xer_ca_o [0] sync init end - process $group_116 + process $group_123 assign \src1_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \src1_i \int_src1__data_o sync init end - process $group_117 - assign \rd__go$49 6'000000 - assign \rd__go$49 [0] \rdpick_INT_ra_o [1] - assign \rd__go$49 [1] \rdpick_INT_rb_o [1] - assign \rd__go$49 [2] \rdpick_CR_full_cr_o - assign \rd__go$49 [3] \rdpick_CR_cr_a_o [0] - assign \rd__go$49 [4] \rdpick_CR_cr_b_o - assign \rd__go$49 [5] \rdpick_CR_cr_c_o + process $group_124 + assign \rd__go$55 6'000000 + assign \rd__go$55 [0] \rdpick_INT_ra_o [1] + assign \rd__go$55 [1] \rdpick_INT_rb_o [1] + assign \rd__go$55 [2] \rdpick_CR_full_cr_o + assign \rd__go$55 [3] \rdpick_CR_cr_a_o [0] + assign \rd__go$55 [4] \rdpick_CR_cr_b_o + assign \rd__go$55 [5] \rdpick_CR_cr_c_o sync init end - process $group_118 - assign \src1_i$50 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_i$50 \int_src1__data_o + process $group_125 + assign \src1_i$56 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$56 \int_src1__data_o sync init end - process $group_119 - assign \rd__go$52 6'000000 - assign \rd__go$52 [0] \rdpick_INT_ra_o [2] - assign \rd__go$52 [1] \rdpick_INT_rb_o [2] - assign \rd__go$52 [2] \rdpick_FAST_spr1_o [1] - assign \rd__go$52 [3] \rdpick_FAST_spr2_o [1] - assign \rd__go$52 [4] \rdpick_FAST_cia_o [1] - assign \rd__go$52 [5] \rdpick_FAST_msr_o + process $group_126 + assign \rd__go$58 6'000000 + assign \rd__go$58 [0] \rdpick_INT_ra_o [2] + assign \rd__go$58 [1] \rdpick_INT_rb_o [2] + assign \rd__go$58 [2] \rdpick_FAST_fast1_o [1] + assign \rd__go$58 [3] \rdpick_FAST_fast2_o [1] + assign \rd__go$58 [4] \rdpick_FAST_cia_o [1] + assign \rd__go$58 [5] \rdpick_FAST_msr_o sync init end - process $group_120 - assign \src1_i$53 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_i$53 \int_src1__data_o + process $group_127 + assign \src1_i$59 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$59 \int_src1__data_o sync init end - process $group_121 - assign \rd__go$55 2'00 - assign \rd__go$55 [0] \rdpick_INT_ra_o [3] - assign \rd__go$55 [1] \rdpick_INT_rb_o [3] + process $group_128 + assign \rd__go$61 2'00 + assign \rd__go$61 [0] \rdpick_INT_ra_o [3] + assign \rd__go$61 [1] \rdpick_INT_rb_o [3] sync init end - process $group_122 - assign \src1_i$56 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_i$56 \int_src1__data_o + process $group_129 + assign \src1_i$62 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$62 \int_src1__data_o sync init end - process $group_123 - assign \rd__go$58 4'0000 - assign \rd__go$58 [0] \rdpick_INT_ra_o [4] - assign \rd__go$58 [1] \rdpick_INT_rb_o [4] - assign \rd__go$58 [2] \rdpick_INT_rc_o [0] - assign \rd__go$58 [3] \rdpick_XER_xer_ca_o [1] + process $group_130 + assign \rd__go$64 6'000000 + assign \rd__go$64 [0] \rdpick_INT_ra_o [4] + assign \rd__go$64 [3] \rdpick_XER_xer_so_o [1] + assign \rd__go$64 [5] \rdpick_XER_xer_ca_o [1] + assign \rd__go$64 [4] \rdpick_XER_xer_ov_o + assign \rd__go$64 [2] \rdpick_FAST_fast1_o [2] + assign \rd__go$64 [1] \rdpick_SPR_spr1_o sync init end - process $group_124 - assign \src1_i$59 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_i$59 \int_src1__data_o + process $group_131 + assign \src1_i$65 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$65 \int_src1__data_o sync init end - process $group_125 - assign \rd__go$61 3'000 - assign \rd__go$61 [0] \rdpick_INT_ra_o [5] - assign \rd__go$61 [1] \rdpick_INT_rb_o [5] - assign \rd__go$61 [2] \rdpick_INT_rc_o [1] + process $group_132 + assign \rd__go$67 4'0000 + assign \rd__go$67 [0] \rdpick_INT_ra_o [5] + assign \rd__go$67 [1] \rdpick_INT_rb_o [4] + assign \rd__go$67 [2] \rdpick_INT_rc_o [0] + assign \rd__go$67 [3] \rdpick_XER_xer_ca_o [2] sync init end - process $group_126 - assign \src1_i$62 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_i$62 \int_src1__data_o + process $group_133 + assign \src1_i$68 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$68 \int_src1__data_o + sync init + end + process $group_134 + assign \rd__go$70 3'000 + assign \rd__go$70 [0] \rdpick_INT_ra_o [6] + assign \rd__go$70 [1] \rdpick_INT_rb_o [5] + assign \rd__go$70 [2] \rdpick_INT_rc_o [1] + sync init + end + process $group_135 + assign \src1_i$71 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$71 \int_src1__data_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" wire width 1 \rdflag_INT_rb - process $group_127 + process $group_136 assign \rdflag_INT_rb 1'0 assign \rdflag_INT_rb \reg2_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:49" - wire width 32 $282 + wire width 32 $331 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:49" - cell $sshl $283 + cell $sshl $332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -131205,22 +140254,22 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \reg2 - connect \Y $282 + connect \Y $331 end - process $group_128 + process $group_137 assign \int_src2__ren 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" switch { \rdpick_INT_rb_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" case 1'1 - assign \int_src2__ren $282 + assign \int_src2__ren $331 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $284 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -131228,202 +140277,202 @@ module \core parameter \Y_WIDTH 1 connect \A \rd__rel [1] connect \B \fu_enable [0] - connect \Y $284 + connect \Y $333 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $286 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $284 + connect \A $333 connect \B \rdflag_INT_rb - connect \Y $286 + connect \Y $335 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $288 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $289 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$48 [1] + connect \A \rd__rel$54 [1] connect \B \fu_enable [1] - connect \Y $288 + connect \Y $337 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $290 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $291 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $339 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $288 + connect \A $337 connect \B \rdflag_INT_rb - connect \Y $290 + connect \Y $339 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $292 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $293 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $341 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$51 [1] + connect \A \rd__rel$57 [1] connect \B \fu_enable [3] - connect \Y $292 + connect \Y $341 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $294 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $295 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $343 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $292 + connect \A $341 connect \B \rdflag_INT_rb - connect \Y $294 + connect \Y $343 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $296 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $297 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $345 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$54 [1] + connect \A \rd__rel$60 [1] connect \B \fu_enable [4] - connect \Y $296 + connect \Y $345 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $298 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $299 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $347 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $296 + connect \A $345 connect \B \rdflag_INT_rb - connect \Y $298 + connect \Y $347 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $300 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $301 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $349 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$57 [1] - connect \B \fu_enable [5] - connect \Y $300 + connect \A \rd__rel$66 [1] + connect \B \fu_enable [6] + connect \Y $349 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $302 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $303 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $351 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $300 + connect \A $349 connect \B \rdflag_INT_rb - connect \Y $302 + connect \Y $351 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $304 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$60 [1] - connect \B \fu_enable [6] - connect \Y $304 + connect \A \rd__rel$69 [1] + connect \B \fu_enable [7] + connect \Y $353 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $306 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $355 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $304 + connect \A $353 connect \B \rdflag_INT_rb - connect \Y $306 + connect \Y $355 end - process $group_129 + process $group_138 assign \rdpick_INT_rb_i 6'000000 - assign \rdpick_INT_rb_i [0] $286 - assign \rdpick_INT_rb_i [1] $290 - assign \rdpick_INT_rb_i [2] $294 - assign \rdpick_INT_rb_i [3] $298 - assign \rdpick_INT_rb_i [4] $302 - assign \rdpick_INT_rb_i [5] $306 + assign \rdpick_INT_rb_i [0] $335 + assign \rdpick_INT_rb_i [1] $339 + assign \rdpick_INT_rb_i [2] $343 + assign \rdpick_INT_rb_i [3] $347 + assign \rdpick_INT_rb_i [4] $351 + assign \rdpick_INT_rb_i [5] $355 sync init end - process $group_130 + process $group_139 assign \src2_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \src2_i \int_src2__data_o sync init end - process $group_131 - assign \src2_i$63 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_i$63 \int_src2__data_o + process $group_140 + assign \src2_i$72 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$72 \int_src2__data_o sync init end - process $group_132 - assign \src2_i$64 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_i$64 \int_src2__data_o + process $group_141 + assign \src2_i$73 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$73 \int_src2__data_o sync init end - process $group_133 - assign \src2_i$65 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_i$65 \int_src2__data_o + process $group_142 + assign \src2_i$74 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$74 \int_src2__data_o sync init end - process $group_134 - assign \src2_i$66 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_i$66 \int_src2__data_o + process $group_143 + assign \src2_i$75 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$75 \int_src2__data_o sync init end - process $group_135 - assign \src2_i$67 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_i$67 \int_src2__data_o + process $group_144 + assign \src2_i$76 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$76 \int_src2__data_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" wire width 1 \rdflag_INT_rc - process $group_136 + process $group_145 assign \rdflag_INT_rc 1'0 assign \rdflag_INT_rc \reg3_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - wire width 32 $308 + wire width 32 $357 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51" - cell $sshl $309 + cell $sshl $358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -131431,92 +140480,92 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \reg3 - connect \Y $308 + connect \Y $357 end - process $group_137 + process $group_146 assign \int_src3__ren 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" switch { \rdpick_INT_rc_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" case 1'1 - assign \int_src3__ren $308 + assign \int_src3__ren $357 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $310 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$57 [2] - connect \B \fu_enable [5] - connect \Y $310 + connect \A \rd__rel$66 [2] + connect \B \fu_enable [6] + connect \Y $359 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $312 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $313 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $361 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $310 + connect \A $359 connect \B \rdflag_INT_rc - connect \Y $312 + connect \Y $361 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $314 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $315 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$60 [2] - connect \B \fu_enable [6] - connect \Y $314 + connect \A \rd__rel$69 [2] + connect \B \fu_enable [7] + connect \Y $363 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $316 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $317 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $314 + connect \A $363 connect \B \rdflag_INT_rc - connect \Y $316 + connect \Y $365 end - process $group_138 + process $group_147 assign \rdpick_INT_rc_i 2'00 - assign \rdpick_INT_rc_i [0] $312 - assign \rdpick_INT_rc_i [1] $316 + assign \rdpick_INT_rc_i [0] $361 + assign \rdpick_INT_rc_i [1] $365 sync init end - process $group_139 + process $group_148 assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \fus_src3_i \int_src3__data_o sync init end - process $group_140 + process $group_149 assign \src3_i 64'0000000000000000000000000000000000000000000000000000000000000000 assign \src3_i \int_src3__data_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" wire width 1 \rdflag_XER_xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71" - wire width 1 $318 + wire width 1 $367 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71" - cell $and $319 + cell $and $368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -131524,27 +140573,27 @@ module \core parameter \Y_WIDTH 1 connect \A \oe connect \B \oe_ok - connect \Y $318 + connect \Y $367 end - process $group_141 + process $group_150 assign \rdflag_XER_xer_so 1'0 - assign \rdflag_XER_xer_so $318 + assign \rdflag_XER_xer_so $367 sync init end - process $group_142 + process $group_151 assign \xer_src1__ren 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" switch { \rdpick_XER_xer_so_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" case 1'1 assign \xer_src1__ren 3'001 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $320 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $321 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $369 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -131552,37 +140601,69 @@ module \core parameter \Y_WIDTH 1 connect \A \rd__rel [2] connect \B \fu_enable [0] - connect \Y $320 + connect \Y $369 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $322 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $323 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $320 + connect \A $369 connect \B \rdflag_XER_xer_so - connect \Y $322 + connect \Y $371 end - process $group_143 - assign \rdpick_XER_xer_so_i 1'0 - assign \rdpick_XER_xer_so_i $322 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $373 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rd__rel$63 [3] + connect \B \fu_enable [5] + connect \Y $373 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $373 + connect \B \rdflag_XER_xer_so + connect \Y $375 + end + process $group_152 + assign \rdpick_XER_xer_so_i 2'00 + assign \rdpick_XER_xer_so_i [0] $371 + assign \rdpick_XER_xer_so_i [1] $375 sync init end - process $group_144 - assign \fus_src3_i$149 1'0 - assign \fus_src3_i$149 \xer_src1__data_o [0] + process $group_153 + assign \fus_src3_i$166 1'0 + assign \fus_src3_i$166 \xer_src1__data_o [0] sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" + process $group_154 + assign \fus_src4_i 1'0 + assign \fus_src4_i \xer_src1__data_o [0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" wire width 1 \rdflag_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" - wire width 1 $324 + wire width 1 $377 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75" - cell $eq $325 + cell $eq $378 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -131590,27 +140671,27 @@ module \core parameter \Y_WIDTH 1 connect \A \input_carry connect \B 2'10 - connect \Y $324 + connect \Y $377 end - process $group_145 + process $group_155 assign \rdflag_XER_xer_ca 1'0 - assign \rdflag_XER_xer_ca $324 + assign \rdflag_XER_xer_ca $377 sync init end - process $group_146 + process $group_156 assign \xer_src2__ren 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" switch { \rdpick_XER_xer_ca_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" case 1'1 assign \xer_src2__ren 3'010 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $326 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $379 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -131618,129 +140699,227 @@ module \core parameter \Y_WIDTH 1 connect \A \rd__rel [3] connect \B \fu_enable [0] - connect \Y $326 + connect \Y $379 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $328 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $326 + connect \A $379 connect \B \rdflag_XER_xer_ca - connect \Y $328 + connect \Y $381 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $330 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$57 [3] + connect \A \rd__rel$63 [5] connect \B \fu_enable [5] - connect \Y $330 + connect \Y $383 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $332 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $330 + connect \A $383 connect \B \rdflag_XER_xer_ca - connect \Y $332 + connect \Y $385 end - process $group_147 - assign \rdpick_XER_xer_ca_i 2'00 - assign \rdpick_XER_xer_ca_i [0] $328 - assign \rdpick_XER_xer_ca_i [1] $332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $387 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rd__rel$66 [3] + connect \B \fu_enable [6] + connect \Y $387 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $387 + connect \B \rdflag_XER_xer_ca + connect \Y $389 + end + process $group_157 + assign \rdpick_XER_xer_ca_i 3'000 + assign \rdpick_XER_xer_ca_i [0] $381 + assign \rdpick_XER_xer_ca_i [1] $385 + assign \rdpick_XER_xer_ca_i [2] $389 sync init end - process $group_148 - assign \fus_src4_i 2'00 - assign \fus_src4_i \xer_src2__data_o + process $group_158 + assign \fus_src4_i$167 2'00 + assign \fus_src4_i$167 \xer_src2__data_o sync init end - process $group_149 - assign \fus_src4_i$150 2'00 - assign \fus_src4_i$150 \xer_src2__data_o + process $group_159 + assign \fus_src6_i 2'00 + assign \fus_src6_i \xer_src2__data_o + sync init + end + process $group_160 + assign \fus_src4_i$168 2'00 + assign \fus_src4_i$168 \xer_src2__data_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" + wire width 1 \rdflag_XER_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:73" + wire width 1 $391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:73" + cell $and $392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \oe + connect \B \oe_ok + connect \Y $391 + end + process $group_161 + assign \rdflag_XER_xer_ov 1'0 + assign \rdflag_XER_xer_ov $391 + sync init + end + process $group_162 + assign \xer_src3__ren 3'000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \rdpick_XER_xer_ov_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \xer_src3__ren 3'100 + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rd__rel$63 [4] + connect \B \fu_enable [5] + connect \Y $393 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $395 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $393 + connect \B \rdflag_XER_xer_ov + connect \Y $395 + end + process $group_163 + assign \rdpick_XER_xer_ov_i 1'0 + assign \rdpick_XER_xer_ov_i $395 + sync init + end + process $group_164 + assign \fus_src5_i 2'00 + assign \fus_src5_i \xer_src3__data_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" wire width 1 \rdflag_CR_full_cr - process $group_150 + process $group_165 assign \rdflag_CR_full_cr 1'0 assign \rdflag_CR_full_cr \read_cr_whole sync init end - process $group_151 + process $group_166 assign \cr_full_rd__ren 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" switch { \rdpick_CR_full_cr_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" case 1'1 assign \cr_full_rd__ren 8'11111111 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $334 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $397 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$48 [2] + connect \A \rd__rel$54 [2] connect \B \fu_enable [1] - connect \Y $334 + connect \Y $397 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $336 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $399 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $334 + connect \A $397 connect \B \rdflag_CR_full_cr - connect \Y $336 + connect \Y $399 end - process $group_152 + process $group_167 assign \rdpick_CR_full_cr_i 1'0 - assign \rdpick_CR_full_cr_i $336 + assign \rdpick_CR_full_cr_i $399 sync init end - process $group_153 - assign \fus_src3_i$151 32'00000000000000000000000000000000 - assign \fus_src3_i$151 \cr_full_rd__data_o + process $group_168 + assign \fus_src3_i$169 32'00000000000000000000000000000000 + assign \fus_src3_i$169 \cr_full_rd__data_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" wire width 1 \rdflag_CR_cr_a - process $group_154 + process $group_169 assign \rdflag_CR_cr_a 1'0 assign \rdflag_CR_cr_a \cr_in1_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59" - wire width 16 $338 + wire width 16 $401 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59" - wire width 4 $339 + wire width 4 $402 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59" - cell $sub $340 + cell $sub $403 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -131748,121 +140927,121 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \cr_in1 - connect \Y $339 + connect \Y $402 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59" - wire width 16 $341 + wire width 16 $404 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59" - cell $sshl $342 + cell $sshl $405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $339 - connect \Y $341 + connect \B $402 + connect \Y $404 end - connect $338 $341 - process $group_155 + connect $401 $404 + process $group_170 assign \cr_src1__ren 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" switch { \rdpick_CR_cr_a_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" case 1'1 - assign \cr_src1__ren $338 [7:0] + assign \cr_src1__ren $401 [7:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $343 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $344 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$48 [3] + connect \A \rd__rel$54 [3] connect \B \fu_enable [1] - connect \Y $343 + connect \Y $406 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $345 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $346 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $343 + connect \A $406 connect \B \rdflag_CR_cr_a - connect \Y $345 + connect \Y $408 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $347 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $348 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$68 [2] + connect \A \rd__rel$77 [2] connect \B \fu_enable [2] - connect \Y $347 + connect \Y $410 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $349 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $350 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $347 + connect \A $410 connect \B \rdflag_CR_cr_a - connect \Y $349 + connect \Y $412 end - process $group_156 + process $group_171 assign \rdpick_CR_cr_a_i 2'00 - assign \rdpick_CR_cr_a_i [0] $345 - assign \rdpick_CR_cr_a_i [1] $349 + assign \rdpick_CR_cr_a_i [0] $408 + assign \rdpick_CR_cr_a_i [1] $412 sync init end - process $group_157 - assign \fus_src4_i$152 4'0000 - assign \fus_src4_i$152 \cr_src1__data_o + process $group_172 + assign \fus_src4_i$170 4'0000 + assign \fus_src4_i$170 \cr_src1__data_o sync init end - process $group_158 - assign \rd__go$69 4'0000 - assign \rd__go$69 [2] \rdpick_CR_cr_a_o [1] - assign \rd__go$69 [0] \rdpick_FAST_spr1_o [0] - assign \rd__go$69 [1] \rdpick_FAST_spr2_o [0] - assign \rd__go$69 [3] \rdpick_FAST_cia_o [0] + process $group_173 + assign \rd__go$78 4'0000 + assign \rd__go$78 [2] \rdpick_CR_cr_a_o [1] + assign \rd__go$78 [0] \rdpick_FAST_fast1_o [0] + assign \rd__go$78 [1] \rdpick_FAST_fast2_o [0] + assign \rd__go$78 [3] \rdpick_FAST_cia_o [0] sync init end - process $group_159 - assign \fus_src3_i$153 4'0000 - assign \fus_src3_i$153 \cr_src1__data_o + process $group_174 + assign \fus_src3_i$171 4'0000 + assign \fus_src3_i$171 \cr_src1__data_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" wire width 1 \rdflag_CR_cr_b - process $group_160 + process $group_175 assign \rdflag_CR_cr_b 1'0 assign \rdflag_CR_cr_b \cr_in2_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61" - wire width 16 $351 + wire width 16 $414 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61" - wire width 4 $352 + wire width 4 $415 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61" - cell $sub $353 + cell $sub $416 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -131870,161 +141049,161 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \cr_in2 - connect \Y $352 + connect \Y $415 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61" - wire width 16 $354 + wire width 16 $417 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61" - cell $sshl $355 + cell $sshl $418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $352 - connect \Y $354 + connect \B $415 + connect \Y $417 end - connect $351 $354 - process $group_161 + connect $414 $417 + process $group_176 assign \cr_src2__ren 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" switch { \rdpick_CR_cr_b_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" case 1'1 - assign \cr_src2__ren $351 [7:0] + assign \cr_src2__ren $414 [7:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $356 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $357 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$48 [4] + connect \A \rd__rel$54 [4] connect \B \fu_enable [1] - connect \Y $356 + connect \Y $419 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $358 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $421 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $356 + connect \A $419 connect \B \rdflag_CR_cr_b - connect \Y $358 + connect \Y $421 end - process $group_162 + process $group_177 assign \rdpick_CR_cr_b_i 1'0 - assign \rdpick_CR_cr_b_i $358 + assign \rdpick_CR_cr_b_i $421 sync init end - process $group_163 - assign \fus_src5_i 4'0000 - assign \fus_src5_i \cr_src2__data_o + process $group_178 + assign \fus_src5_i$172 4'0000 + assign \fus_src5_i$172 \cr_src2__data_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" wire width 1 \rdflag_CR_cr_c - process $group_164 + process $group_179 assign \rdflag_CR_cr_c 1'0 assign \rdflag_CR_cr_c \cr_in2_ok$5 sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63" - wire width 16 $360 + wire width 16 $423 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63" - wire width 4 $361 + wire width 4 $424 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63" - cell $sub $362 + cell $sub $425 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 3 parameter \Y_WIDTH 4 connect \A 3'111 - connect \B \cr_in2$70 - connect \Y $361 + connect \B \cr_in2$79 + connect \Y $424 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63" - wire width 16 $363 + wire width 16 $426 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63" - cell $sshl $364 + cell $sshl $427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $361 - connect \Y $363 + connect \B $424 + connect \Y $426 end - connect $360 $363 - process $group_165 + connect $423 $426 + process $group_180 assign \cr_src3__ren 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" switch { \rdpick_CR_cr_c_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" case 1'1 - assign \cr_src3__ren $360 [7:0] + assign \cr_src3__ren $423 [7:0] end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $365 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $366 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $428 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$48 [5] + connect \A \rd__rel$54 [5] connect \B \fu_enable [1] - connect \Y $365 + connect \Y $428 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $367 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $368 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $430 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $365 + connect \A $428 connect \B \rdflag_CR_cr_c - connect \Y $367 + connect \Y $430 end - process $group_166 + process $group_181 assign \rdpick_CR_cr_c_i 1'0 - assign \rdpick_CR_cr_c_i $367 + assign \rdpick_CR_cr_c_i $430 sync init end - process $group_167 - assign \fus_src6_i 4'0000 - assign \fus_src6_i \cr_src3__data_o + process $group_182 + assign \fus_src6_i$173 4'0000 + assign \fus_src6_i$173 \cr_src3__data_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" - wire width 1 \rdflag_FAST_spr1 - process $group_168 - assign \rdflag_FAST_spr1 1'0 - assign \rdflag_FAST_spr1 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" + wire width 1 \rdflag_FAST_fast1 + process $group_183 + assign \rdflag_FAST_fast1 1'0 + assign \rdflag_FAST_fast1 \fast1_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:92" - wire width 8 $369 + wire width 8 $432 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:92" - cell $sshl $370 + cell $sshl $433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132032,97 +141211,129 @@ module \core parameter \Y_WIDTH 8 connect \A 1'1 connect \B \fast1 - connect \Y $369 + connect \Y $432 end - process $group_169 + process $group_184 assign \fast_src3__ren 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" - switch { \rdpick_FAST_spr1_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \rdpick_FAST_fast1_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" case 1'1 - assign \fast_src3__ren $369 + assign \fast_src3__ren $432 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $371 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $372 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $434 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$68 [0] + connect \A \rd__rel$77 [0] connect \B \fu_enable [2] - connect \Y $371 + connect \Y $434 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $373 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $374 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $436 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $371 - connect \B \rdflag_FAST_spr1 - connect \Y $373 + connect \A $434 + connect \B \rdflag_FAST_fast1 + connect \Y $436 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $375 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $438 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$51 [2] + connect \A \rd__rel$57 [2] connect \B \fu_enable [3] - connect \Y $375 + connect \Y $438 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $377 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $378 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $440 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $375 - connect \B \rdflag_FAST_spr1 - connect \Y $377 + connect \A $438 + connect \B \rdflag_FAST_fast1 + connect \Y $440 end - process $group_170 - assign \rdpick_FAST_spr1_i 2'00 - assign \rdpick_FAST_spr1_i [0] $373 - assign \rdpick_FAST_spr1_i [1] $377 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $442 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rd__rel$63 [2] + connect \B \fu_enable [5] + connect \Y $442 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $442 + connect \B \rdflag_FAST_fast1 + connect \Y $444 + end + process $group_185 + assign \rdpick_FAST_fast1_i 3'000 + assign \rdpick_FAST_fast1_i [0] $436 + assign \rdpick_FAST_fast1_i [1] $440 + assign \rdpick_FAST_fast1_i [2] $444 sync init end - process $group_171 - assign \src1_i$71 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_i$71 \fast_src3__data_o + process $group_186 + assign \src1_i$80 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src1_i$80 \fast_src3__data_o sync init end - process $group_172 - assign \fus_src3_i$154 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_src3_i$154 \fast_src3__data_o + process $group_187 + assign \fus_src3_i$174 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_src3_i$174 \fast_src3__data_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" - wire width 1 \rdflag_FAST_spr2 - process $group_173 - assign \rdflag_FAST_spr2 1'0 - assign \rdflag_FAST_spr2 \fast2_ok + process $group_188 + assign \fus_src3_i$175 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_src3_i$175 \fast_src3__data_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" + wire width 1 \rdflag_FAST_fast2 + process $group_189 + assign \rdflag_FAST_fast2 1'0 + assign \rdflag_FAST_fast2 \fast2_ok sync init end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:94" - wire width 8 $379 + wire width 8 $446 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:94" - cell $sshl $380 + cell $sshl $447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132130,232 +141341,285 @@ module \core parameter \Y_WIDTH 8 connect \A 1'1 connect \B \fast2 - connect \Y $379 + connect \Y $446 end - process $group_174 + process $group_190 assign \fast_src4__ren 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" - switch { \rdpick_FAST_spr2_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \rdpick_FAST_fast2_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" case 1'1 - assign \fast_src4__ren $379 + assign \fast_src4__ren $446 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $381 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $382 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $448 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$68 [1] + connect \A \rd__rel$77 [1] connect \B \fu_enable [2] - connect \Y $381 + connect \Y $448 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $383 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $384 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $450 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $381 - connect \B \rdflag_FAST_spr2 - connect \Y $383 + connect \A $448 + connect \B \rdflag_FAST_fast2 + connect \Y $450 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $385 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $386 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$51 [3] + connect \A \rd__rel$57 [3] connect \B \fu_enable [3] - connect \Y $385 + connect \Y $452 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $387 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $388 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $454 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $385 - connect \B \rdflag_FAST_spr2 - connect \Y $387 + connect \A $452 + connect \B \rdflag_FAST_fast2 + connect \Y $454 end - process $group_175 - assign \rdpick_FAST_spr2_i 2'00 - assign \rdpick_FAST_spr2_i [0] $383 - assign \rdpick_FAST_spr2_i [1] $387 + process $group_191 + assign \rdpick_FAST_fast2_i 2'00 + assign \rdpick_FAST_fast2_i [0] $450 + assign \rdpick_FAST_fast2_i [1] $454 sync init end - process $group_176 - assign \src2_i$72 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_i$72 \fast_src4__data_o + process $group_192 + assign \src2_i$81 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$81 \fast_src4__data_o sync init end - process $group_177 - assign \fus_src4_i$155 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_src4_i$155 \fast_src4__data_o + process $group_193 + assign \fus_src4_i$176 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_src4_i$176 \fast_src4__data_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" wire width 1 \rdflag_FAST_cia wire width 1 $verilog_initial_trigger - process $group_178 + process $group_194 assign \rdflag_FAST_cia 1'0 assign \rdflag_FAST_cia 1'1 assign $verilog_initial_trigger $verilog_initial_trigger sync init update $verilog_initial_trigger 1'0 end - process $group_179 + process $group_195 assign \fast_src1__ren 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" switch { \rdpick_FAST_cia_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" case 1'1 assign \fast_src1__ren 8'00000001 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $389 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $456 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$68 [3] + connect \A \rd__rel$77 [3] connect \B \fu_enable [2] - connect \Y $389 + connect \Y $456 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $391 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $458 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $389 + connect \A $456 connect \B \rdflag_FAST_cia - connect \Y $391 + connect \Y $458 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $393 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $460 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$51 [4] + connect \A \rd__rel$57 [4] connect \B \fu_enable [3] - connect \Y $393 + connect \Y $460 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $395 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $462 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $393 + connect \A $460 connect \B \rdflag_FAST_cia - connect \Y $395 + connect \Y $462 end - process $group_180 + process $group_196 assign \rdpick_FAST_cia_i 2'00 - assign \rdpick_FAST_cia_i [0] $391 - assign \rdpick_FAST_cia_i [1] $395 + assign \rdpick_FAST_cia_i [0] $458 + assign \rdpick_FAST_cia_i [1] $462 sync init end - process $group_181 - assign \fus_src4_i$156 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_src4_i$156 \fast_src1__data_o + process $group_197 + assign \fus_src4_i$177 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_src4_i$177 \fast_src1__data_o sync init end - process $group_182 - assign \fus_src5_i$157 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_src5_i$157 \fast_src1__data_o + process $group_198 + assign \fus_src5_i$178 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_src5_i$178 \fast_src1__data_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" wire width 1 \rdflag_FAST_msr - process $group_183 + process $group_199 assign \rdflag_FAST_msr 1'0 assign \rdflag_FAST_msr 1'1 assign $verilog_initial_trigger $verilog_initial_trigger sync init end - process $group_184 + process $group_200 assign \fast_src2__ren 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" switch { \rdpick_FAST_msr_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" case 1'1 assign \fast_src2__ren 8'00000010 end sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $397 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $398 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $464 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \rd__rel$51 [5] + connect \A \rd__rel$57 [5] connect \B \fu_enable [3] - connect \Y $397 + connect \Y $464 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - wire width 1 $399 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174" - cell $and $400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $466 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $397 + connect \A $464 connect \B \rdflag_FAST_msr - connect \Y $399 + connect \Y $466 end - process $group_185 + process $group_201 assign \rdpick_FAST_msr_i 1'0 - assign \rdpick_FAST_msr_i $399 + assign \rdpick_FAST_msr_i $466 sync init end - process $group_186 - assign \fus_src6_i$158 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_src6_i$158 \fast_src2__data_o + process $group_202 + assign \fus_src6_i$179 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fus_src6_i$179 \fast_src2__data_o sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - wire width 32 $401 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:108" - cell $sshl $402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151" + wire width 1 \rdflag_SPR_spr1 + process $group_203 + assign \rdflag_SPR_spr1 1'0 + assign \rdflag_SPR_spr1 \spr1_ok + sync init + end + process $group_204 + assign \spr_src__ren 1'0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + switch { \rdpick_SPR_spr1_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163" + case 1'1 + assign \spr_src__ren \spr1 [0] + end + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rd__rel$63 [1] + connect \B \fu_enable [5] + connect \Y $468 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + wire width 1 $470 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173" + cell $and $471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $468 + connect \B \rdflag_SPR_spr1 + connect \Y $470 + end + process $group_205 + assign \rdpick_SPR_spr1_i 1'0 + assign \rdpick_SPR_spr1_i $470 + sync init + end + process $group_206 + assign \src2_i$82 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \src2_i$82 \spr_src__data_o + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:111" + wire width 32 $472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:111" + cell $sshl $473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132363,16 +141627,16 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \rego - connect \Y $401 + connect \Y $472 end - process $group_187 + process $group_207 assign \int_wen$next \int_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" switch { \wrpick_INT_o_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" case 1'1 - assign \int_wen$next $401 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + assign \int_wen$next $472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" case assign \int_wen$next 32'00000000000000000000000000000000 end @@ -132386,17 +141650,17 @@ module \core sync posedge \clk update \int_wen \int_wen$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_alu0_o_0 - process $group_188 + process $group_208 assign \wrflag_alu0_o_0 1'0 assign \wrflag_alu0_o_0 \fus_o_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $403 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $404 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $474 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132404,87 +141668,101 @@ module \core parameter \Y_WIDTH 1 connect \A \wr__rel [0] connect \B \fu_enable [0] - connect \Y $403 + connect \Y $474 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $405 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$73 [0] + connect \A \wr__rel$83 [0] connect \B \fu_enable [1] - connect \Y $405 + connect \Y $476 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $407 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$75 [0] + connect \A \wr__rel$85 [0] connect \B \fu_enable [3] - connect \Y $407 + connect \Y $478 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $409 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $410 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $480 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$77 [0] + connect \A \wr__rel$87 [0] connect \B \fu_enable [4] - connect \Y $409 + connect \Y $480 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $411 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $482 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$79 [0] + connect \A \wr__rel$89 [0] connect \B \fu_enable [5] - connect \Y $411 + connect \Y $482 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $413 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $414 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $484 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$81 [0] + connect \A \wr__rel$91 [0] connect \B \fu_enable [6] - connect \Y $413 + connect \Y $484 end - process $group_189 - assign \wrpick_INT_o_i 6'000000 - assign \wrpick_INT_o_i [0] $403 - assign \wrpick_INT_o_i [1] $405 - assign \wrpick_INT_o_i [2] $407 - assign \wrpick_INT_o_i [3] $409 - assign \wrpick_INT_o_i [4] $411 - assign \wrpick_INT_o_i [5] $413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $486 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr__rel$93 [0] + connect \B \fu_enable [7] + connect \Y $486 + end + process $group_209 + assign \wrpick_INT_o_i 7'0000000 + assign \wrpick_INT_o_i [0] $474 + assign \wrpick_INT_o_i [1] $476 + assign \wrpick_INT_o_i [2] $478 + assign \wrpick_INT_o_i [3] $480 + assign \wrpick_INT_o_i [4] $482 + assign \wrpick_INT_o_i [5] $484 + assign \wrpick_INT_o_i [6] $486 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $415 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $416 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $488 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132492,12 +141770,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [0] connect \B \wrpick_INT_o_en_o - connect \Y $415 + connect \Y $488 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $417 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $418 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $490 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132505,12 +141783,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [0] connect \B \wrpick_CR_cr_a_en_o - connect \Y $417 + connect \Y $490 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $419 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $420 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132518,57 +141796,57 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [0] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $419 + connect \Y $492 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $421 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o + connect \A \wrpick_XER_xer_ov_o [0] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $421 + connect \Y $494 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $423 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $424 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o + connect \A \wrpick_XER_xer_so_o [0] connect \B \wrpick_XER_xer_so_en_o - connect \Y $423 + connect \Y $496 end - process $group_190 + process $group_210 assign \wr__go$next \wr__go - assign \wr__go$next [0] $415 - assign \wr__go$next [1] $417 - assign \wr__go$next [2] $419 - assign \wr__go$next [3] $421 - assign \wr__go$next [4] $423 + assign \wr__go$next [0] $488 + assign \wr__go$next [1] $490 + assign \wr__go$next [2] $492 + assign \wr__go$next [3] $494 + assign \wr__go$next [4] $496 sync init update \wr__go 5'00000 sync posedge \clk update \wr__go \wr__go$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_cr0_o_0 - process $group_191 + process $group_211 assign \wrflag_cr0_o_0 1'0 - assign \wrflag_cr0_o_0 \fus_o_ok$159 + assign \wrflag_cr0_o_0 \fus_o_ok$180 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $425 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $426 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $498 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132576,12 +141854,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [1] connect \B \wrpick_INT_o_en_o - connect \Y $425 + connect \Y $498 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $427 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $428 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $500 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132589,12 +141867,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_full_cr_o connect \B \wrpick_CR_full_cr_en_o - connect \Y $427 + connect \Y $500 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $429 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $430 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132602,29 +141880,29 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [1] connect \B \wrpick_CR_cr_a_en_o - connect \Y $429 + connect \Y $502 end - process $group_192 - assign \wr__go$74$next \wr__go$74 - assign \wr__go$74$next [0] $425 - assign \wr__go$74$next [1] $427 - assign \wr__go$74$next [2] $429 + process $group_212 + assign \wr__go$84$next \wr__go$84 + assign \wr__go$84$next [0] $498 + assign \wr__go$84$next [1] $500 + assign \wr__go$84$next [2] $502 sync init - update \wr__go$74 3'000 + update \wr__go$84 3'000 sync posedge \clk - update \wr__go$74 \wr__go$74$next + update \wr__go$84 \wr__go$84$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_trap0_o_0 - process $group_193 + process $group_213 assign \wrflag_trap0_o_0 1'0 - assign \wrflag_trap0_o_0 \fus_o_ok$160 + assign \wrflag_trap0_o_0 \fus_o_ok$181 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $431 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $432 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $504 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132632,38 +141910,38 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [2] connect \B \wrpick_INT_o_en_o - connect \Y $431 + connect \Y $504 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $433 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $434 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $506 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_spr1_o [1] - connect \B \wrpick_FAST_spr1_en_o - connect \Y $433 + connect \A \wrpick_FAST_fast1_o [1] + connect \B \wrpick_FAST_fast1_en_o + connect \Y $506 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $435 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $436 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_spr2_o [1] - connect \B \wrpick_FAST_spr2_en_o - connect \Y $435 + connect \A \wrpick_FAST_fast2_o [1] + connect \B \wrpick_FAST_fast2_en_o + connect \Y $508 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $437 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $438 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $510 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132671,12 +141949,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_nia_o [1] connect \B \wrpick_FAST_nia_en_o - connect \Y $437 + connect \Y $510 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $439 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $440 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132684,31 +141962,31 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_msr_o connect \B \wrpick_FAST_msr_en_o - connect \Y $439 + connect \Y $512 end - process $group_194 - assign \wr__go$76$next \wr__go$76 - assign \wr__go$76$next [0] $431 - assign \wr__go$76$next [1] $433 - assign \wr__go$76$next [2] $435 - assign \wr__go$76$next [3] $437 - assign \wr__go$76$next [4] $439 - sync init - update \wr__go$76 5'00000 + process $group_214 + assign \wr__go$86$next \wr__go$86 + assign \wr__go$86$next [0] $504 + assign \wr__go$86$next [1] $506 + assign \wr__go$86$next [2] $508 + assign \wr__go$86$next [3] $510 + assign \wr__go$86$next [4] $512 + sync init + update \wr__go$86 5'00000 sync posedge \clk - update \wr__go$76 \wr__go$76$next + update \wr__go$86 \wr__go$86$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_logical0_o_0 - process $group_195 + process $group_215 assign \wrflag_logical0_o_0 1'0 - assign \wrflag_logical0_o_0 \fus_o_ok$161 + assign \wrflag_logical0_o_0 \fus_o_ok$182 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $441 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $442 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132716,12 +141994,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [3] connect \B \wrpick_INT_o_en_o - connect \Y $441 + connect \Y $514 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $443 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $444 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132729,12 +142007,12 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [2] connect \B \wrpick_CR_cr_a_en_o - connect \Y $443 + connect \Y $516 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $445 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $446 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132742,42 +142020,140 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [1] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $445 + connect \Y $518 end - process $group_196 - assign \wr__go$78$next \wr__go$78 - assign \wr__go$78$next [0] $441 - assign \wr__go$78$next [1] $443 - assign \wr__go$78$next [2] $445 + process $group_216 + assign \wr__go$88$next \wr__go$88 + assign \wr__go$88$next [0] $514 + assign \wr__go$88$next [1] $516 + assign \wr__go$88$next [2] $518 sync init - update \wr__go$78 3'000 + update \wr__go$88 3'000 sync posedge \clk - update \wr__go$78 \wr__go$78$next + update \wr__go$88 \wr__go$88$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" + wire width 1 \wrflag_spr0_o_0 + process $group_217 + assign \wrflag_spr0_o_0 1'0 + assign \wrflag_spr0_o_0 \fus_o_ok$183 + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_INT_o_o [4] + connect \B \wrpick_INT_o_en_o + connect \Y $520 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ca_o [2] + connect \B \wrpick_XER_xer_ca_en_o + connect \Y $522 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_ov_o [1] + connect \B \wrpick_XER_xer_ov_en_o + connect \Y $524 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_XER_xer_so_o [1] + connect \B \wrpick_XER_xer_so_en_o + connect \Y $526 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_FAST_fast1_o [2] + connect \B \wrpick_FAST_fast1_en_o + connect \Y $528 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_SPR_spr1_o + connect \B \wrpick_SPR_spr1_en_o + connect \Y $530 + end + process $group_218 + assign \wr__go$90$next \wr__go$90 + assign \wr__go$90$next [0] $520 + assign \wr__go$90$next [5] $522 + assign \wr__go$90$next [4] $524 + assign \wr__go$90$next [3] $526 + assign \wr__go$90$next [2] $528 + assign \wr__go$90$next [1] $530 + sync init + update \wr__go$90 6'000000 + sync posedge \clk + update \wr__go$90 \wr__go$90$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_shiftrot0_o_0 - process $group_197 + process $group_219 assign \wrflag_shiftrot0_o_0 1'0 - assign \wrflag_shiftrot0_o_0 \fus_o_ok$162 + assign \wrflag_shiftrot0_o_0 \fus_o_ok$184 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $447 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $448 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [4] + connect \A \wrpick_INT_o_o [5] connect \B \wrpick_INT_o_en_o - connect \Y $447 + connect \Y $532 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $449 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $450 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132785,55 +142161,55 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [3] connect \B \wrpick_CR_cr_a_en_o - connect \Y $449 + connect \Y $534 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $451 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [2] + connect \A \wrpick_XER_xer_ca_o [3] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $451 + connect \Y $536 end - process $group_198 - assign \wr__go$80$next \wr__go$80 - assign \wr__go$80$next [0] $447 - assign \wr__go$80$next [1] $449 - assign \wr__go$80$next [2] $451 + process $group_220 + assign \wr__go$92$next \wr__go$92 + assign \wr__go$92$next [0] $532 + assign \wr__go$92$next [1] $534 + assign \wr__go$92$next [2] $536 sync init - update \wr__go$80 3'000 + update \wr__go$92 3'000 sync posedge \clk - update \wr__go$80 \wr__go$80$next + update \wr__go$92 \wr__go$92$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_ldst0_o_0 - process $group_199 + process $group_221 assign \wrflag_ldst0_o_0 1'0 assign \wrflag_ldst0_o_0 \o_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $453 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $454 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [5] + connect \A \wrpick_INT_o_o [6] connect \B \wrpick_INT_o_en_o - connect \Y $453 + connect \Y $538 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $455 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $456 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $540 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132841,85 +142217,98 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o1_o connect \B \wrpick_INT_o1_en_o - connect \Y $455 + connect \Y $540 end - process $group_200 - assign \wr__go$82$next \wr__go$82 - assign \wr__go$82$next [0] $453 - assign \wr__go$82$next [1] $455 + process $group_222 + assign \wr__go$94$next \wr__go$94 + assign \wr__go$94$next [0] $538 + assign \wr__go$94$next [1] $540 sync init - update \wr__go$82 2'00 + update \wr__go$94 2'00 sync posedge \clk - update \wr__go$82 \wr__go$82$next + update \wr__go$94 \wr__go$94$next end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 64 $457 + wire width 64 $542 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $458 + cell $or $543 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_o$163 - connect \B \fus_o$164 - connect \Y $457 + connect \A \fus_o$185 + connect \B \fus_o$186 + connect \Y $542 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - wire width 64 $459 + wire width 64 $544 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - cell $or $460 + cell $or $545 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_o - connect \B $457 - connect \Y $459 + connect \B $542 + connect \Y $544 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + wire width 64 $546 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + cell $or $547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_o$187 + connect \B \fus_o$188 + connect \Y $546 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 64 $461 + wire width 64 $548 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $462 + cell $or $549 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_o$166 + connect \A \fus_o$189 connect \B \o - connect \Y $461 + connect \Y $548 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - wire width 64 $463 + wire width 64 $550 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - cell $or $464 + cell $or $551 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_o$165 - connect \B $461 - connect \Y $463 + connect \A $546 + connect \B $548 + connect \Y $550 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - wire width 64 $465 + wire width 64 $552 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - cell $or $466 + cell $or $553 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $459 - connect \B $463 - connect \Y $465 + connect \A $544 + connect \B $550 + connect \Y $552 end - process $group_201 + process $group_223 assign \int_data_i$next \int_data_i - assign \int_data_i$next $465 + assign \int_data_i$next $552 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -132930,10 +142319,10 @@ module \core sync posedge \clk update \int_data_i \int_data_i$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:110" - wire width 32 $467 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:110" - cell $sshl $468 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:113" + wire width 32 $554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:113" + cell $sshl $555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -132941,75 +142330,75 @@ module \core parameter \Y_WIDTH 32 connect \A 1'1 connect \B \ea - connect \Y $467 + connect \Y $554 end - process $group_202 - assign \int_wen$183$next \int_wen$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + process $group_224 + assign \int_wen$214$next \int_wen$214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" switch { \wrpick_INT_o1_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" case 1'1 - assign \int_wen$183$next $467 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + assign \int_wen$214$next $554 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" case - assign \int_wen$183$next 32'00000000000000000000000000000000 + assign \int_wen$214$next 32'00000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \int_wen$183$next 32'00000000000000000000000000000000 + assign \int_wen$214$next 32'00000000000000000000000000000000 end sync init - update \int_wen$183 32'00000000000000000000000000000000 + update \int_wen$214 32'00000000000000000000000000000000 sync posedge \clk - update \int_wen$183 \int_wen$183$next + update \int_wen$214 \int_wen$214$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_ldst0_o1_1 - process $group_203 + process $group_225 assign \wrflag_ldst0_o1_1 1'0 assign \wrflag_ldst0_o1_1 \ea_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $469 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $470 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $556 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$81 [1] - connect \B \fu_enable [6] - connect \Y $469 + connect \A \wr__rel$93 [1] + connect \B \fu_enable [7] + connect \Y $556 end - process $group_204 + process $group_226 assign \wrpick_INT_o1_i 1'0 - assign \wrpick_INT_o1_i $469 + assign \wrpick_INT_o1_i $556 sync init end - process $group_205 - assign \int_data_i$184$next \int_data_i$184 - assign \int_data_i$184$next \ea$83 + process $group_227 + assign \int_data_i$215$next \int_data_i$215 + assign \int_data_i$215$next \ea$95 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \int_data_i$184$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \int_data_i$215$next 64'0000000000000000000000000000000000000000000000000000000000000000 end sync init - update \int_data_i$184 64'0000000000000000000000000000000000000000000000000000000000000000 + update \int_data_i$215 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk - update \int_data_i$184 \int_data_i$184$next + update \int_data_i$215 \int_data_i$215$next end - process $group_206 + process $group_228 assign \cr_full_wr__wen$next \cr_full_wr__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" switch { \wrpick_CR_full_cr_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" case 1'1 assign \cr_full_wr__wen$next 8'11111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" case assign \cr_full_wr__wen$next 8'00000000 end @@ -133023,32 +142412,32 @@ module \core sync posedge \clk update \cr_full_wr__wen \cr_full_wr__wen$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_cr0_full_cr_1 - process $group_207 + process $group_229 assign \wrflag_cr0_full_cr_1 1'0 assign \wrflag_cr0_full_cr_1 \fus_full_cr_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $471 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $472 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$73 [1] + connect \A \wr__rel$83 [1] connect \B \fu_enable [1] - connect \Y $471 + connect \Y $558 end - process $group_208 + process $group_230 assign \wrpick_CR_full_cr_i 1'0 - assign \wrpick_CR_full_cr_i $471 + assign \wrpick_CR_full_cr_i $558 sync init end - process $group_209 + process $group_231 assign \cr_full_wr__data_i$next \cr_full_wr__data_i assign \cr_full_wr__data_i$next \fus_full_cr attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" @@ -133061,12 +142450,12 @@ module \core sync posedge \clk update \cr_full_wr__data_i \cr_full_wr__data_i$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118" - wire width 16 $473 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118" - wire width 4 $474 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118" - cell $sub $475 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:121" + wire width 16 $560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:121" + wire width 4 $561 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:121" + cell $sub $562 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -133074,30 +142463,30 @@ module \core parameter \Y_WIDTH 4 connect \A 3'111 connect \B \cr_out - connect \Y $474 + connect \Y $561 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118" - wire width 16 $476 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:118" - cell $sshl $477 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:121" + wire width 16 $563 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:121" + cell $sshl $564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 16 connect \A 1'1 - connect \B $474 - connect \Y $476 + connect \B $561 + connect \Y $563 end - connect $473 $476 - process $group_210 + connect $560 $563 + process $group_232 assign \cr_wen$next \cr_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" switch { \wrpick_CR_cr_a_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" case 1'1 - assign \cr_wen$next $473 [7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + assign \cr_wen$next $560 [7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" case assign \cr_wen$next 8'00000000 end @@ -133111,17 +142500,17 @@ module \core sync posedge \clk update \cr_wen \cr_wen$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_alu0_cr_a_1 - process $group_211 + process $group_233 assign \wrflag_alu0_cr_a_1 1'0 assign \wrflag_alu0_cr_a_1 \fus_cr_a_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $478 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $479 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133129,118 +142518,118 @@ module \core parameter \Y_WIDTH 1 connect \A \wr__rel [1] connect \B \fu_enable [0] - connect \Y $478 + connect \Y $565 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $480 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $481 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$73 [2] + connect \A \wr__rel$83 [2] connect \B \fu_enable [1] - connect \Y $480 + connect \Y $567 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $482 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $483 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$77 [1] + connect \A \wr__rel$87 [1] connect \B \fu_enable [4] - connect \Y $482 + connect \Y $569 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $484 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $485 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $571 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$79 [1] - connect \B \fu_enable [5] - connect \Y $484 + connect \A \wr__rel$91 [1] + connect \B \fu_enable [6] + connect \Y $571 end - process $group_212 + process $group_234 assign \wrpick_CR_cr_a_i 4'0000 - assign \wrpick_CR_cr_a_i [0] $478 - assign \wrpick_CR_cr_a_i [1] $480 - assign \wrpick_CR_cr_a_i [2] $482 - assign \wrpick_CR_cr_a_i [3] $484 + assign \wrpick_CR_cr_a_i [0] $565 + assign \wrpick_CR_cr_a_i [1] $567 + assign \wrpick_CR_cr_a_i [2] $569 + assign \wrpick_CR_cr_a_i [3] $571 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_cr0_cr_a_2 - process $group_213 + process $group_235 assign \wrflag_cr0_cr_a_2 1'0 - assign \wrflag_cr0_cr_a_2 \fus_cr_a_ok$167 + assign \wrflag_cr0_cr_a_2 \fus_cr_a_ok$190 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_logical0_cr_a_1 - process $group_214 + process $group_236 assign \wrflag_logical0_cr_a_1 1'0 - assign \wrflag_logical0_cr_a_1 \fus_cr_a_ok$168 + assign \wrflag_logical0_cr_a_1 \fus_cr_a_ok$191 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_shiftrot0_cr_a_1 - process $group_215 + process $group_237 assign \wrflag_shiftrot0_cr_a_1 1'0 - assign \wrflag_shiftrot0_cr_a_1 \fus_cr_a_ok$169 + assign \wrflag_shiftrot0_cr_a_1 \fus_cr_a_ok$192 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 4 $486 + wire width 4 $573 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $487 + cell $or $574 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 connect \A \fus_cr_a - connect \B \fus_cr_a$170 - connect \Y $486 + connect \B \fus_cr_a$193 + connect \Y $573 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 4 $488 + wire width 4 $575 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $489 + cell $or $576 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A \fus_cr_a$171 - connect \B \fus_cr_a$172 - connect \Y $488 + connect \A \fus_cr_a$194 + connect \B \fus_cr_a$195 + connect \Y $575 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - wire width 4 $490 + wire width 4 $577 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - cell $or $491 + cell $or $578 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $486 - connect \B $488 - connect \Y $490 + connect \A $573 + connect \B $575 + connect \Y $577 end - process $group_216 + process $group_238 assign \cr_data_i$next \cr_data_i - assign \cr_data_i$next $490 + assign \cr_data_i$next $577 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -133251,14 +142640,14 @@ module \core sync posedge \clk update \cr_data_i \cr_data_i$next end - process $group_217 + process $group_239 assign \xer_wen$next \xer_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" switch { \wrpick_XER_xer_ca_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" case 1'1 assign \xer_wen$next 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" case assign \xer_wen$next 3'000 end @@ -133272,17 +142661,17 @@ module \core sync posedge \clk update \xer_wen \xer_wen$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_alu0_xer_ca_2 - process $group_218 + process $group_240 assign \wrflag_alu0_xer_ca_2 1'0 assign \wrflag_alu0_xer_ca_2 \fus_xer_ca_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $492 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $493 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133290,84 +142679,118 @@ module \core parameter \Y_WIDTH 1 connect \A \wr__rel [2] connect \B \fu_enable [0] - connect \Y $492 + connect \Y $579 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $494 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $495 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $581 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$77 [2] + connect \A \wr__rel$87 [2] connect \B \fu_enable [4] - connect \Y $494 + connect \Y $581 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $496 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $497 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $583 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$79 [2] + connect \A \wr__rel$89 [5] connect \B \fu_enable [5] - connect \Y $496 + connect \Y $583 end - process $group_219 - assign \wrpick_XER_xer_ca_i 3'000 - assign \wrpick_XER_xer_ca_i [0] $492 - assign \wrpick_XER_xer_ca_i [1] $494 - assign \wrpick_XER_xer_ca_i [2] $496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $585 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr__rel$91 [2] + connect \B \fu_enable [6] + connect \Y $585 + end + process $group_241 + assign \wrpick_XER_xer_ca_i 4'0000 + assign \wrpick_XER_xer_ca_i [0] $579 + assign \wrpick_XER_xer_ca_i [1] $581 + assign \wrpick_XER_xer_ca_i [2] $583 + assign \wrpick_XER_xer_ca_i [3] $585 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_logical0_xer_ca_2 - process $group_220 + process $group_242 assign \wrflag_logical0_xer_ca_2 1'0 - assign \wrflag_logical0_xer_ca_2 \fus_xer_ca_ok$173 + assign \wrflag_logical0_xer_ca_2 \fus_xer_ca_ok$196 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" + wire width 1 \wrflag_spr0_xer_ca_5 + process $group_243 + assign \wrflag_spr0_xer_ca_5 1'0 + assign \wrflag_spr0_xer_ca_5 \fus_xer_ca_ok$197 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_shiftrot0_xer_ca_2 - process $group_221 + process $group_244 assign \wrflag_shiftrot0_xer_ca_2 1'0 - assign \wrflag_shiftrot0_xer_ca_2 \fus_xer_ca_ok$174 + assign \wrflag_shiftrot0_xer_ca_2 \fus_xer_ca_ok$198 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 2 $498 + wire width 2 $587 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $499 + cell $or $588 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \fus_xer_ca$175 - connect \B \fus_xer_ca$176 - connect \Y $498 + connect \A \fus_xer_ca + connect \B \fus_xer_ca$199 + connect \Y $587 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + wire width 2 $589 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + cell $or $590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \fus_xer_ca$200 + connect \B \fus_xer_ca$201 + connect \Y $589 end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - wire width 2 $500 + wire width 2 $591 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" - cell $or $501 + cell $or $592 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 2 - connect \A \fus_xer_ca - connect \B $498 - connect \Y $500 + connect \A $587 + connect \B $589 + connect \Y $591 end - process $group_222 + process $group_245 assign \xer_data_i$next \xer_data_i - assign \xer_data_i$next $500 + assign \xer_data_i$next $591 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -133378,38 +142801,38 @@ module \core sync posedge \clk update \xer_data_i \xer_data_i$next end - process $group_223 - assign \xer_wen$185$next \xer_wen$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + process $group_246 + assign \xer_wen$216$next \xer_wen$216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" switch { \wrpick_XER_xer_ov_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" case 1'1 - assign \xer_wen$185$next 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + assign \xer_wen$216$next 3'100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" case - assign \xer_wen$185$next 3'000 + assign \xer_wen$216$next 3'000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \xer_wen$185$next 3'000 + assign \xer_wen$216$next 3'000 end sync init - update \xer_wen$185 3'000 + update \xer_wen$216 3'000 sync posedge \clk - update \xer_wen$185 \xer_wen$185$next + update \xer_wen$216 \xer_wen$216$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_alu0_xer_ov_3 - process $group_224 + process $group_247 assign \wrflag_alu0_xer_ov_3 1'0 assign \wrflag_alu0_xer_ov_3 \fus_xer_ov_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $502 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133417,58 +142840,92 @@ module \core parameter \Y_WIDTH 1 connect \A \wr__rel [3] connect \B \fu_enable [0] - connect \Y $502 + connect \Y $593 end - process $group_225 - assign \wrpick_XER_xer_ov_i 1'0 - assign \wrpick_XER_xer_ov_i $502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr__rel$89 [4] + connect \B \fu_enable [5] + connect \Y $595 + end + process $group_248 + assign \wrpick_XER_xer_ov_i 2'00 + assign \wrpick_XER_xer_ov_i [0] $593 + assign \wrpick_XER_xer_ov_i [1] $595 sync init end - process $group_226 - assign \xer_data_i$186$next \xer_data_i$186 - assign \xer_data_i$186$next \fus_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" + wire width 1 \wrflag_spr0_xer_ov_4 + process $group_249 + assign \wrflag_spr0_xer_ov_4 1'0 + assign \wrflag_spr0_xer_ov_4 \fus_xer_ov_ok$202 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + wire width 2 $597 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + cell $or $598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \fus_xer_ov + connect \B \fus_xer_ov$203 + connect \Y $597 + end + process $group_250 + assign \xer_data_i$217$next \xer_data_i$217 + assign \xer_data_i$217$next $597 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \xer_data_i$186$next 2'00 + assign \xer_data_i$217$next 2'00 end sync init - update \xer_data_i$186 2'00 + update \xer_data_i$217 2'00 sync posedge \clk - update \xer_data_i$186 \xer_data_i$186$next + update \xer_data_i$217 \xer_data_i$217$next end - process $group_227 - assign \xer_wen$187$next \xer_wen$187 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + process $group_251 + assign \xer_wen$218$next \xer_wen$218 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" switch { \wrpick_XER_xer_so_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" case 1'1 - assign \xer_wen$187$next 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + assign \xer_wen$218$next 3'001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" case - assign \xer_wen$187$next 3'000 + assign \xer_wen$218$next 3'000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \xer_wen$187$next 3'000 + assign \xer_wen$218$next 3'000 end sync init - update \xer_wen$187 3'000 + update \xer_wen$218 3'000 sync posedge \clk - update \xer_wen$187 \xer_wen$187$next + update \xer_wen$218 \xer_wen$218$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_alu0_xer_so_4 - process $group_228 + process $group_252 assign \wrflag_alu0_xer_so_4 1'0 assign \wrflag_alu0_xer_so_4 \fus_xer_so_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $504 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $505 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $599 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133476,40 +142933,74 @@ module \core parameter \Y_WIDTH 1 connect \A \wr__rel [4] connect \B \fu_enable [0] - connect \Y $504 + connect \Y $599 end - process $group_229 - assign \wrpick_XER_xer_so_i 1'0 - assign \wrpick_XER_xer_so_i $504 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr__rel$89 [3] + connect \B \fu_enable [5] + connect \Y $601 + end + process $group_253 + assign \wrpick_XER_xer_so_i 2'00 + assign \wrpick_XER_xer_so_i [0] $599 + assign \wrpick_XER_xer_so_i [1] $601 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 2 $506 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - cell $pos $507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" + wire width 1 \wrflag_spr0_xer_so_3 + process $group_254 + assign \wrflag_spr0_xer_so_3 1'0 + assign \wrflag_spr0_xer_so_3 \fus_xer_so_ok$204 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + wire width 2 $603 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + wire width 1 $604 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + cell $or $605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \Y_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 connect \A \fus_xer_so - connect \Y $506 + connect \B \fus_xer_so$205 + connect \Y $604 end - process $group_230 - assign \xer_data_i$188$next \xer_data_i$188 - assign \xer_data_i$188$next $506 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" + cell $pos $606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A $604 + connect \Y $603 + end + process $group_255 + assign \xer_data_i$219$next \xer_data_i$219 + assign \xer_data_i$219$next $603 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \xer_data_i$188$next 2'00 + assign \xer_data_i$219$next 2'00 end sync init - update \xer_data_i$188 2'00 + update \xer_data_i$219 2'00 sync posedge \clk - update \xer_data_i$188 \xer_data_i$188$next + update \xer_data_i$219 \xer_data_i$219$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:147" - wire width 8 $508 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:147" - cell $sshl $509 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:150" + wire width 8 $607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:150" + cell $sshl $608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133517,16 +143008,16 @@ module \core parameter \Y_WIDTH 8 connect \A 1'1 connect \B \fasto1 - connect \Y $508 + connect \Y $607 end - process $group_231 + process $group_256 assign \fast_wen$next \fast_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - switch { \wrpick_FAST_spr1_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" + switch { \wrpick_FAST_fast1_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" case 1'1 - assign \fast_wen$next $508 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + assign \fast_wen$next $607 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" case assign \fast_wen$next 8'00000000 end @@ -133540,75 +143031,89 @@ module \core sync posedge \clk update \fast_wen \fast_wen$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 \wrflag_branch0_spr1_0 - process $group_232 - assign \wrflag_branch0_spr1_0 1'0 - assign \wrflag_branch0_spr1_0 \fus_spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" + wire width 1 \wrflag_branch0_fast1_0 + process $group_257 + assign \wrflag_branch0_fast1_0 1'0 + assign \wrflag_branch0_fast1_0 \fus_fast1_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $510 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $511 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$84 [0] + connect \A \wr__rel$96 [0] connect \B \fu_enable [2] - connect \Y $510 + connect \Y $609 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $512 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $611 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$75 [1] + connect \A \wr__rel$85 [1] connect \B \fu_enable [3] - connect \Y $512 + connect \Y $611 end - process $group_233 - assign \wrpick_FAST_spr1_i 2'00 - assign \wrpick_FAST_spr1_i [0] $510 - assign \wrpick_FAST_spr1_i [1] $512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $613 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr__rel$89 [2] + connect \B \fu_enable [5] + connect \Y $613 + end + process $group_258 + assign \wrpick_FAST_fast1_i 3'000 + assign \wrpick_FAST_fast1_i [0] $609 + assign \wrpick_FAST_fast1_i [1] $611 + assign \wrpick_FAST_fast1_i [2] $613 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $514 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $615 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_spr1_o [0] - connect \B \wrpick_FAST_spr1_en_o - connect \Y $514 + connect \A \wrpick_FAST_fast1_o [0] + connect \B \wrpick_FAST_fast1_en_o + connect \Y $615 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $516 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $617 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_spr2_o [0] - connect \B \wrpick_FAST_spr2_en_o - connect \Y $516 + connect \A \wrpick_FAST_fast2_o [0] + connect \B \wrpick_FAST_fast2_en_o + connect \Y $617 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - wire width 1 $518 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:243" - cell $and $519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + wire width 1 $619 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242" + cell $and $620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133616,41 +143121,61 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_nia_o [0] connect \B \wrpick_FAST_nia_en_o - connect \Y $518 + connect \Y $619 end - process $group_234 - assign \wr__go$85$next \wr__go$85 - assign \wr__go$85$next [0] $514 - assign \wr__go$85$next [1] $516 - assign \wr__go$85$next [2] $518 + process $group_259 + assign \wr__go$97$next \wr__go$97 + assign \wr__go$97$next [0] $615 + assign \wr__go$97$next [1] $617 + assign \wr__go$97$next [2] $619 sync init - update \wr__go$85 3'000 + update \wr__go$97 3'000 sync posedge \clk - update \wr__go$85 \wr__go$85$next + update \wr__go$97 \wr__go$97$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 \wrflag_trap0_spr1_1 - process $group_235 - assign \wrflag_trap0_spr1_1 1'0 - assign \wrflag_trap0_spr1_1 \fus_spr1_ok$177 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" + wire width 1 \wrflag_trap0_fast1_1 + process $group_260 + assign \wrflag_trap0_fast1_1 1'0 + assign \wrflag_trap0_fast1_1 \fus_fast1_ok$206 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" + wire width 1 \wrflag_spr0_fast1_2 + process $group_261 + assign \wrflag_spr0_fast1_2 1'0 + assign \wrflag_spr0_fast1_2 \fus_fast1_ok$207 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 64 $520 + wire width 64 $621 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $521 + cell $or $622 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_spr1 - connect \B \fus_spr1$178 - connect \Y $520 + connect \A \fus_fast1$208 + connect \B \fus_fast1$209 + connect \Y $621 end - process $group_236 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" + wire width 64 $623 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28" + cell $or $624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \fus_fast1 + connect \B $621 + connect \Y $623 + end + process $group_262 assign \fast_data_i$next \fast_data_i - assign \fast_data_i$next $520 + assign \fast_data_i$next $623 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 @@ -133661,10 +143186,10 @@ module \core sync posedge \clk update \fast_data_i \fast_data_i$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:149" - wire width 8 $522 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:149" - cell $sshl $523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:152" + wire width 8 $625 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:152" + cell $sshl $626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -133672,109 +143197,109 @@ module \core parameter \Y_WIDTH 8 connect \A 1'1 connect \B \fasto2 - connect \Y $522 + connect \Y $625 end - process $group_237 - assign \fast_wen$189$next \fast_wen$189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" - switch { \wrpick_FAST_spr2_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + process $group_263 + assign \fast_wen$220$next \fast_wen$220 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" + switch { \wrpick_FAST_fast2_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" case 1'1 - assign \fast_wen$189$next $522 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + assign \fast_wen$220$next $625 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" case - assign \fast_wen$189$next 8'00000000 + assign \fast_wen$220$next 8'00000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \fast_wen$189$next 8'00000000 + assign \fast_wen$220$next 8'00000000 end sync init - update \fast_wen$189 8'00000000 + update \fast_wen$220 8'00000000 sync posedge \clk - update \fast_wen$189 \fast_wen$189$next + update \fast_wen$220 \fast_wen$220$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 \wrflag_branch0_spr2_1 - process $group_238 - assign \wrflag_branch0_spr2_1 1'0 - assign \wrflag_branch0_spr2_1 \fus_spr2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" + wire width 1 \wrflag_branch0_fast2_1 + process $group_264 + assign \wrflag_branch0_fast2_1 1'0 + assign \wrflag_branch0_fast2_1 \fus_fast2_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $524 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $627 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$84 [1] + connect \A \wr__rel$96 [1] connect \B \fu_enable [2] - connect \Y $524 + connect \Y $627 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $526 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $527 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $629 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$75 [2] + connect \A \wr__rel$85 [2] connect \B \fu_enable [3] - connect \Y $526 + connect \Y $629 end - process $group_239 - assign \wrpick_FAST_spr2_i 2'00 - assign \wrpick_FAST_spr2_i [0] $524 - assign \wrpick_FAST_spr2_i [1] $526 + process $group_265 + assign \wrpick_FAST_fast2_i 2'00 + assign \wrpick_FAST_fast2_i [0] $627 + assign \wrpick_FAST_fast2_i [1] $629 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" - wire width 1 \wrflag_trap0_spr2_2 - process $group_240 - assign \wrflag_trap0_spr2_2 1'0 - assign \wrflag_trap0_spr2_2 \fus_spr2_ok$179 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" + wire width 1 \wrflag_trap0_fast2_2 + process $group_266 + assign \wrflag_trap0_fast2_2 1'0 + assign \wrflag_trap0_fast2_2 \fus_fast2_ok$210 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 64 $528 + wire width 64 $631 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $529 + cell $or $632 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A \fus_spr2 - connect \B \fus_spr2$180 - connect \Y $528 + connect \A \fus_fast2 + connect \B \fus_fast2$211 + connect \Y $631 end - process $group_241 - assign \fast_data_i$190$next \fast_data_i$190 - assign \fast_data_i$190$next $528 + process $group_267 + assign \fast_data_i$221$next \fast_data_i$221 + assign \fast_data_i$221$next $631 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \fast_data_i$190$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast_data_i$221$next 64'0000000000000000000000000000000000000000000000000000000000000000 end sync init - update \fast_data_i$190 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast_data_i$221 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk - update \fast_data_i$190 \fast_data_i$190$next + update \fast_data_i$221 \fast_data_i$221$next end - process $group_242 + process $group_268 assign \fast_nia_wen$next \fast_nia_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" switch { \wrpick_FAST_nia_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" case 1'1 assign \fast_nia_wen$next 8'00000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" case assign \fast_nia_wen$next 8'00000000 end @@ -133788,136 +143313,195 @@ module \core sync posedge \clk update \fast_nia_wen \fast_nia_wen$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_branch0_nia_2 - process $group_243 + process $group_269 assign \wrflag_branch0_nia_2 1'0 assign \wrflag_branch0_nia_2 \fus_nia_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $530 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $531 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $633 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$84 [2] + connect \A \wr__rel$96 [2] connect \B \fu_enable [2] - connect \Y $530 + connect \Y $633 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $532 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $533 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$75 [3] + connect \A \wr__rel$85 [3] connect \B \fu_enable [3] - connect \Y $532 + connect \Y $635 end - process $group_244 + process $group_270 assign \wrpick_FAST_nia_i 2'00 - assign \wrpick_FAST_nia_i [0] $530 - assign \wrpick_FAST_nia_i [1] $532 + assign \wrpick_FAST_nia_i [0] $633 + assign \wrpick_FAST_nia_i [1] $635 sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_trap0_nia_3 - process $group_245 + process $group_271 assign \wrflag_trap0_nia_3 1'0 - assign \wrflag_trap0_nia_3 \fus_nia_ok$181 + assign \wrflag_trap0_nia_3 \fus_nia_ok$212 sync init end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - wire width 64 $534 + wire width 64 $637 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25" - cell $or $535 + cell $or $638 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A \fus_nia - connect \B \fus_nia$182 - connect \Y $534 + connect \B \fus_nia$213 + connect \Y $637 end - process $group_246 - assign \fast_data_i$191$next \fast_data_i$191 - assign \fast_data_i$191$next $534 + process $group_272 + assign \fast_data_i$222$next \fast_data_i$222 + assign \fast_data_i$222$next $637 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \fast_data_i$191$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast_data_i$222$next 64'0000000000000000000000000000000000000000000000000000000000000000 end sync init - update \fast_data_i$191 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast_data_i$222 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk - update \fast_data_i$191 \fast_data_i$191$next + update \fast_data_i$222 \fast_data_i$222$next end - process $group_247 - assign \fast_wen$192$next \fast_wen$192 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + process $group_273 + assign \fast_wen$223$next \fast_wen$223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" switch { \wrpick_FAST_msr_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:224" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" case 1'1 - assign \fast_wen$192$next 8'00000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226" + assign \fast_wen$223$next 8'00000010 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" case - assign \fast_wen$192$next 8'00000000 + assign \fast_wen$223$next 8'00000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \fast_wen$192$next 8'00000000 + assign \fast_wen$223$next 8'00000000 end sync init - update \fast_wen$192 8'00000000 + update \fast_wen$223 8'00000000 sync posedge \clk - update \fast_wen$192 \fast_wen$192$next + update \fast_wen$223 \fast_wen$223$next end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" wire width 1 \wrflag_trap0_msr_4 - process $group_248 + process $group_274 assign \wrflag_trap0_msr_4 1'0 assign \wrflag_trap0_msr_4 \fus_msr_ok sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - wire width 1 $536 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:241" - cell $and $537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr__rel$75 [4] + connect \A \wr__rel$85 [4] connect \B \fu_enable [3] - connect \Y $536 + connect \Y $639 end - process $group_249 + process $group_275 assign \wrpick_FAST_msr_i 1'0 - assign \wrpick_FAST_msr_i $536 + assign \wrpick_FAST_msr_i $639 sync init end - process $group_250 - assign \fast_data_i$193$next \fast_data_i$193 - assign \fast_data_i$193$next \fus_msr + process $group_276 + assign \fast_data_i$224$next \fast_data_i$224 + assign \fast_data_i$224$next \fus_msr attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" switch \rst case 1'1 - assign \fast_data_i$193$next 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \fast_data_i$224$next 64'0000000000000000000000000000000000000000000000000000000000000000 end sync init - update \fast_data_i$193 64'0000000000000000000000000000000000000000000000000000000000000000 + update \fast_data_i$224 64'0000000000000000000000000000000000000000000000000000000000000000 sync posedge \clk - update \fast_data_i$193 \fast_data_i$193$next + update \fast_data_i$224 \fast_data_i$224$next + end + process $group_277 + assign \spr_dest__wen$next \spr_dest__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" + switch { \wrpick_SPR_spr1_en_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223" + case 1'1 + assign \spr_dest__wen$next \spro [0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225" + case + assign \spr_dest__wen$next 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \spr_dest__wen$next 1'0 + end + sync init + update \spr_dest__wen 1'0 + sync posedge \clk + update \spr_dest__wen \spr_dest__wen$next + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235" + wire width 1 \wrflag_spr0_spr1_1 + process $group_278 + assign \wrflag_spr0_spr1_1 1'0 + assign \wrflag_spr0_spr1_1 \fus_spr1_ok + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + wire width 1 $641 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" + cell $and $642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr__rel$89 [1] + connect \B \fu_enable [5] + connect \Y $641 + end + process $group_279 + assign \wrpick_SPR_spr1_i 1'0 + assign \wrpick_SPR_spr1_i $641 + sync init + end + process $group_280 + assign \spr_dest__data_i$next \spr_dest__data_i + assign \spr_dest__data_i$next \fus_spr1 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" + switch \rst + case 1'1 + assign \spr_dest__data_i$next 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync init + update \spr_dest__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \spr_dest__data_i \spr_dest__data_i$next end end attribute \generator "nMigen" @@ -134614,18 +144198,19 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 32 output 35 \oper_i__insn attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" - wire width 10 output 36 \oper_i__fn_unit + wire width 11 output 36 \oper_i__fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" wire width 1 output 37 \oper_i__read_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21" @@ -134727,18 +144312,19 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 7 output 50 \oper_i__insn_type$18 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" - wire width 10 output 51 \oper_i__fn_unit$19 + wire width 11 output 51 \oper_i__fn_unit$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" wire width 1 output 52 \oper_i__lk$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26" @@ -134844,22 +144430,23 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 32 output 67 \oper_i__insn$35 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 10 output 68 \oper_i__fn_unit$36 + wire width 11 output 68 \oper_i__fn_unit$36 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 1 output 69 \oper_i__is_32bit$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" - wire width 4 output 70 \oper_i__traptype + wire width 5 output 70 \oper_i__traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22" wire width 13 output 71 \oper_i__trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" @@ -134959,18 +144546,19 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 7 output 83 \oper_i__insn_type$49 attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" - wire width 10 output 84 \oper_i__fn_unit$50 + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" + wire width 11 output 84 \oper_i__fn_unit$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" wire width 1 output 85 \oper_i__lk$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32" @@ -135004,9 +144592,9 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" wire width 64 output 98 \dest1_o$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 99 \rd__go$65 + wire width 6 output 99 \rd__go$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 100 \wr__go$66 + wire width 6 output 100 \wr__go$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" wire width 1 output 101 \issue_i$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" @@ -135085,50 +144673,48 @@ module \test_issuer attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" wire width 7 output 104 \oper_i__insn_type$70 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 2 output 105 \oper_i__input_carry$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 106 \oper_i__output_carry$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 107 \oper_i__input_cr$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 108 \oper_i__output_cr$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 109 \oper_i__is_32bit$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" - wire width 1 output 110 \oper_i__is_signed$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 32 output 105 \oper_i__insn$71 + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 11 output 106 \oper_i__fn_unit$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20" + wire width 1 output 107 \oper_i__is_32bit$73 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 111 \src1_i$77 + wire width 64 output 108 \src1_i$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 112 \src2_i$78 + wire width 64 output 109 \src2_i$75 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 113 \busy_o$79 + wire width 1 output 110 \busy_o$76 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 4 output 114 \rd__rel$80 + wire width 6 output 111 \rd__rel$77 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 115 \wr__rel$81 + wire width 6 output 112 \wr__rel$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" - wire width 64 output 116 \dest1_o$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 117 \rd__go$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 118 \ad__go + wire width 64 output 113 \dest1_o$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 119 \wr__go$84 + wire width 4 output 114 \rd__go$80 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 120 \st__go + wire width 3 output 115 \wr__go$81 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" - wire width 1 output 121 \issue_i$85 + wire width 1 output 116 \issue_i$82 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" - wire width 1 input 122 \shadown_i$86 + wire width 1 input 117 \shadown_i$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 1 input 123 \go_die_i$87 + wire width 1 input 118 \go_die_i$84 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -135201,271 +144787,50 @@ module \test_issuer attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 7 output 124 \oper_i__insn_type$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 125 \oper_i__is_32bit$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 126 \oper_i__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 127 \oper_i__is_signed$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 4 output 128 \oper_i__data_len$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 129 \oper_i__byte_reverse$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 130 \oper_i__sign_extend$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" - wire width 1 output 131 \oper_i__update - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 132 \src1_i$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" + wire width 7 output 119 \oper_i__insn_type$85 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" + wire width 2 output 120 \oper_i__input_carry$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" + wire width 1 output 121 \oper_i__output_carry$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" + wire width 1 output 122 \oper_i__input_cr$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" + wire width 1 output 123 \oper_i__output_cr$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" + wire width 1 output 124 \oper_i__is_32bit$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29" + wire width 1 output 125 \oper_i__is_signed$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 133 \src2_i$95 + wire width 64 output 126 \src1_i$92 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" - wire width 64 output 134 \src3_i + wire width 64 output 127 \src2_i$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" - wire width 1 output 135 \busy_o$96 + wire width 1 output 128 \busy_o$94 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 3 output 136 \rd__rel$97 + wire width 4 output 129 \rd__rel$95 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 137 \ad__rel + wire width 3 output 130 \wr__rel$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81" + wire width 64 output 131 \dest1_o$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 1 output 138 \st__rel + wire width 3 output 132 \rd__go$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" - wire width 2 output 139 \wr__rel$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 140 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 input 141 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 142 \ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 input 143 \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112" - wire width 1 output 144 \load_mem_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" - wire width 1 output 145 \stwd_mem_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" - wire width 32 output 146 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:319" - wire width 1 output 147 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" - wire width 32 output 148 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" - wire width 10 output 149 \function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" - wire width 3 output 150 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" - wire width 4 output 151 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" - wire width 2 output 152 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" - wire width 2 output 153 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" - wire width 3 output 154 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" - wire width 3 output 155 \cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" - wire width 4 output 156 \ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" - wire width 2 output 157 \rc_sel - attribute \enum_base_type "InternalOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" - wire width 7 output 158 \internal_op - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" - wire width 5 output 159 \form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123" - wire width 8 output 160 \asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 161 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 162 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 163 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 164 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 165 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 166 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 167 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 168 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 169 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 170 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" - wire width 1 output 171 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:32" - wire width 1 output 172 \valid + wire width 1 output 133 \ad__go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 2 output 134 \wr__go$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 1 output 135 \st__go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94" + wire width 1 output 136 \issue_i$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95" + wire width 1 input 137 \shadown_i$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 1 input 138 \go_die_i$102 attribute \enum_base_type "InternalOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -135538,302 +144903,859 @@ module \test_issuer attribute \enum_value_1000111 "OP_MFMSR" attribute \enum_value_1001000 "OP_MTMSRD" attribute \enum_value_1001001 "OP_SC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33" - wire width 7 output 173 \insn_type - attribute \enum_base_type "Function" - attribute \enum_value_0000000000 "NONE" - attribute \enum_value_0000000010 "ALU" - attribute \enum_value_0000000100 "LDST" - attribute \enum_value_0000001000 "SHIFT_ROT" - attribute \enum_value_0000010000 "LOGICAL" - attribute \enum_value_0000100000 "BRANCH" - attribute \enum_value_0001000000 "CR" - attribute \enum_value_0010000000 "TRAP" - attribute \enum_value_0100000000 "MUL" - attribute \enum_value_1000000000 "DIV" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34" - wire width 10 output 174 \fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:36" - wire width 8 input 175 \asmcode$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37" - wire width 64 output 176 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 177 \rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 178 \rego_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 179 \ea$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 180 \ea_ok$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 181 \reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 182 \reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 183 \reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 184 \reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 5 output 185 \reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 186 \reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 187 \imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 188 \imm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 10 output 189 \spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 190 \spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 10 output 191 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 192 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 10 input 193 \spr2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 input 194 \spr2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 195 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 196 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 197 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 198 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 199 \fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 200 \fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 201 \fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 202 \fasto2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 203 \cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 204 \cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 205 \cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 206 \cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" + wire width 7 output 139 \oper_i__insn_type$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" + wire width 1 output 140 \oper_i__is_32bit$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" + wire width 1 output 141 \oper_i__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" + wire width 1 output 142 \oper_i__is_signed$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" + wire width 4 output 143 \oper_i__data_len$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" + wire width 1 output 144 \oper_i__byte_reverse$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" + wire width 1 output 145 \oper_i__sign_extend$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24" + wire width 1 output 146 \oper_i__update + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 output 147 \src1_i$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 output 148 \src2_i$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69" + wire width 64 output 149 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99" + wire width 1 output 150 \busy_o$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 3 output 151 \rd__rel$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 1 output 152 \ad__rel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 1 output 153 \st__rel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33" + wire width 2 output 154 \wr__rel$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 207 \cr_in2$102 + wire width 64 output 155 \o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 208 \cr_in2_ok$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 output 209 \read_cr_whole + wire width 1 input 156 \o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 3 output 210 \cr_out$104 + wire width 64 output 157 \ea attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 211 \cr_out_ok + wire width 1 input 158 \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112" + wire width 1 output 159 \load_mem_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" + wire width 1 output 160 \stwd_mem_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318" + wire width 32 output 161 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:319" + wire width 1 output 162 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219" + wire width 32 output 163 \opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119" + wire width 11 output 164 \function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124" + wire width 3 output 165 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125" + wire width 4 output 166 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126" + wire width 2 output 167 \in3_sel + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127" + wire width 2 output 168 \out_sel + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128" + wire width 3 output 169 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129" + wire width 3 output 170 \cr_out + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130" + wire width 4 output 171 \ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131" + wire width 2 output 172 \rc_sel + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120" + wire width 7 output 173 \internal_op + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121" + wire width 5 output 174 \form + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123" + wire width 8 output 175 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 1 output 176 \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 1 output 177 \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 1 output 178 \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 1 output 179 \br + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 1 output 180 \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 1 output 181 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 1 output 182 \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 1 output 183 \is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 1 output 184 \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 1 output 185 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135" + wire width 1 output 186 \sgl_pipe + attribute \enum_base_type "InternalOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:32" + wire width 7 output 187 \insn_type + attribute \enum_base_type "Function" + attribute \enum_value_00000000000 "NONE" + attribute \enum_value_00000000010 "ALU" + attribute \enum_value_00000000100 "LDST" + attribute \enum_value_00000001000 "SHIFT_ROT" + attribute \enum_value_00000010000 "LOGICAL" + attribute \enum_value_00000100000 "BRANCH" + attribute \enum_value_00001000000 "CR" + attribute \enum_value_00010000000 "TRAP" + attribute \enum_value_00100000000 "MUL" + attribute \enum_value_01000000000 "DIV" + attribute \enum_value_10000000000 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33" + wire width 11 output 188 \fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35" + wire width 8 output 189 \asmcode$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:36" + wire width 64 output 190 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 5 output 191 \rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 192 \rego_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 5 output 193 \ea$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 194 \ea_ok$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 5 output 195 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 196 \reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 5 output 197 \reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 198 \reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 5 output 199 \reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 200 \reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 64 output 201 \imm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 202 \imm_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 10 output 203 \spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 204 \spro_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 10 output 205 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 206 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 207 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 208 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 209 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 210 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 211 \fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 212 \fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 213 \fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 214 \fasto2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 215 \cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 216 \cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 217 \cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 218 \cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 219 \cr_in2$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 220 \cr_in2_ok$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 1 output 221 \read_cr_whole + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 3 output 222 \cr_out$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" + wire width 1 output 223 \cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57" + wire width 1 output 224 \write_cr_whole attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" - wire width 1 output 212 \write_cr_whole - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" - wire width 1 output 213 \lk$105 + wire width 1 output 225 \lk$120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 214 \rc + wire width 1 output 226 \rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 215 \rc_ok + wire width 1 output 227 \rc_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 216 \oe + wire width 1 output 228 \oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 217 \oe_ok + wire width 1 output 229 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61" + wire width 1 output 230 \invert_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62" - wire width 1 output 218 \invert_a + wire width 1 output 231 \zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63" - wire width 1 output 219 \zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64" - wire width 1 output 220 \invert_out + wire width 1 output 232 \invert_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64" + wire width 2 output 233 \input_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65" - wire width 2 output 221 \input_carry + wire width 1 output 234 \output_carry attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66" - wire width 1 output 222 \output_carry + wire width 1 output 235 \input_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67" - wire width 1 output 223 \input_cr + wire width 1 output 236 \output_cr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68" - wire width 1 output 224 \output_cr + wire width 1 output 237 \is_32bit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69" - wire width 1 output 225 \is_32bit + wire width 1 output 238 \is_signed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70" - wire width 1 output 226 \is_signed + wire width 32 output 239 \insn attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71" - wire width 32 output 227 \insn + wire width 4 output 240 \data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72" - wire width 4 output 228 \data_len + wire width 1 output 241 \byte_reverse attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73" - wire width 1 output 229 \byte_reverse + wire width 1 output 242 \sign_extend attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74" - wire width 1 output 230 \sign_extend + wire width 1 output 243 \update attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:75" - wire width 1 output 231 \update + wire width 5 output 244 \traptype attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:76" - wire width 4 input 232 \traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:77" - wire width 13 output 233 \trapaddr + wire width 13 output 245 \trapaddr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 output 234 \ldst_port0_is_ld_i + wire width 1 output 246 \ldst_port0_is_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 output 235 \ldst_port0_is_st_i + wire width 1 output 247 \ldst_port0_is_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 output 236 \ldst_port0_data_len + wire width 4 output 248 \ldst_port0_data_len attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 1 output 237 \ldst_port0_busy_o + wire width 1 output 249 \ldst_port0_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" - wire width 1 output 238 \ldst_port0_go_die_i + wire width 1 output 250 \ldst_port0_go_die_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 48 output 239 \ldst_port0_addr_i + wire width 48 output 251 \ldst_port0_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 240 \ldst_port0_addr_i_ok + wire width 1 output 252 \ldst_port0_addr_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 output 241 \ldst_port0_addr_ok_o + wire width 1 output 253 \ldst_port0_addr_ok_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 input 242 \ldst_port0_addr_exc_o + wire width 1 input 254 \ldst_port0_addr_exc_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 243 \ldst_port0_ld_data_o + wire width 64 output 255 \ldst_port0_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 244 \ldst_port0_ld_data_o_ok + wire width 1 output 256 \ldst_port0_ld_data_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 245 \ldst_port0_st_data_i + wire width 64 output 257 \ldst_port0_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 246 \ldst_port0_st_data_i_ok + wire width 1 output 258 \ldst_port0_st_data_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26" - wire width 48 output 247 \x_addr_i + wire width 48 output 259 \x_addr_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27" - wire width 8 output 248 \x_mask_i + wire width 8 output 260 \x_mask_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28" - wire width 1 output 249 \x_ld_i + wire width 1 output 261 \x_ld_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29" - wire width 1 output 250 \x_st_i + wire width 1 output 262 \x_st_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30" - wire width 64 output 251 \x_st_data_i + wire width 64 output 263 \x_st_data_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 input 252 \x_stall_i + wire width 1 input 264 \x_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33" - wire width 1 output 253 \x_valid_i + wire width 1 output 265 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36" - wire width 1 input 254 \m_stall_i + wire width 1 input 266 \m_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37" - wire width 1 output 255 \m_valid_i + wire width 1 output 267 \m_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42" - wire width 1 output 256 \x_busy_o + wire width 1 output 268 \x_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" - wire width 1 output 257 \m_busy_o + wire width 1 output 269 \m_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" - wire width 64 output 258 \m_ld_data_o + wire width 64 output 270 \m_ld_data_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire width 1 output 259 \m_load_err_o + wire width 1 output 271 \m_load_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" - wire width 1 output 260 \m_store_err_o + wire width 1 output 272 \m_store_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" - wire width 45 output 261 \m_badaddr_o + wire width 45 output 273 \m_badaddr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 45 output 262 \dbus__adr + wire width 45 output 274 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 output 263 \dbus__dat_w + wire width 64 output 275 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 64 input 264 \dbus__dat_r + wire width 64 input 276 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 8 output 265 \dbus__sel + wire width 8 output 277 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 266 \dbus__cyc + wire width 1 output 278 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 267 \dbus__stb + wire width 1 output 279 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 268 \dbus__ack + wire width 1 input 280 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 output 269 \dbus__we + wire width 1 output 281 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 3 input 270 \dbus__cti + wire width 3 input 282 \dbus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 2 input 271 \dbus__bte + wire width 2 input 283 \dbus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16" - wire width 1 input 272 \dbus__err + wire width 1 input 284 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95" - wire width 1 output 273 \ldst_port0_is_ld_i$106 + wire width 1 output 285 \ldst_port0_is_ld_i$121 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96" - wire width 1 output 274 \ldst_port0_is_st_i$107 + wire width 1 output 286 \ldst_port0_is_st_i$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 4 output 275 \ldst_port0_data_len$108 + wire width 4 output 287 \ldst_port0_data_len$123 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 1 output 276 \ldst_port0_busy_o$109 + wire width 1 output 288 \ldst_port0_busy_o$124 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103" - wire width 1 input 277 \ldst_port0_go_die_i$110 + wire width 1 input 289 \ldst_port0_go_die_i$125 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 96 output 278 \ldst_port0_addr_i$111 + wire width 96 output 290 \ldst_port0_addr_i$126 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 279 \ldst_port0_addr_i_ok$112 + wire width 1 output 291 \ldst_port0_addr_i_ok$127 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 output 280 \ldst_port0_addr_ok_o$113 + wire width 1 output 292 \ldst_port0_addr_ok_o$128 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107" - wire width 1 output 281 \ldst_port0_addr_exc_o$114 + wire width 1 output 293 \ldst_port0_addr_exc_o$129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 282 \ldst_port0_ld_data_o$115 + wire width 64 output 294 \ldst_port0_ld_data_o$130 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 283 \ldst_port0_ld_data_o_ok$116 + wire width 1 output 295 \ldst_port0_ld_data_o_ok$131 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 64 output 284 \ldst_port0_st_data_i$117 + wire width 64 output 296 \ldst_port0_st_data_i$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16" - wire width 1 output 285 \ldst_port0_st_data_i_ok$118 + wire width 1 output 297 \ldst_port0_st_data_i_ok$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:21" - wire width 48 output 286 \a_pc_i + wire width 48 output 298 \a_pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:22" - wire width 1 input 287 \a_stall_i + wire width 1 input 299 \a_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:23" - wire width 1 output 288 \a_valid_i + wire width 1 output 300 \a_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 1 input 289 \f_stall_i + wire width 1 input 301 \f_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" - wire width 1 output 290 \f_valid_i + wire width 1 output 302 \f_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire width 1 output 291 \a_busy_o + wire width 1 output 303 \a_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:29" - wire width 1 output 292 \f_busy_o + wire width 1 output 304 \f_busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:30" - wire width 64 output 293 \f_instr_o + wire width 64 output 305 \f_instr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" - wire width 1 output 294 \f_fetch_err_o + wire width 1 output 306 \f_fetch_err_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire width 45 output 295 \f_badaddr_o + wire width 45 output 307 \f_badaddr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 45 output 296 \ibus__adr + wire width 45 output 308 \ibus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 64 input 297 \ibus__dat_w + wire width 64 input 309 \ibus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 64 input 298 \ibus__dat_r + wire width 64 input 310 \ibus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 8 input 299 \ibus__sel + wire width 8 input 311 \ibus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 1 output 300 \ibus__cyc + wire width 1 output 312 \ibus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 1 output 301 \ibus__stb + wire width 1 output 313 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 1 input 302 \ibus__ack + wire width 1 input 314 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 1 input 303 \ibus__we + wire width 1 input 315 \ibus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 3 input 304 \ibus__cti + wire width 3 input 316 \ibus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 2 input 305 \ibus__bte + wire width 2 input 317 \ibus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17" - wire width 1 input 306 \ibus__err + wire width 1 input 318 \ibus__err attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" - wire width 1 input 307 \clk + wire width 1 input 319 \clk attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" - wire width 1 input 308 \rst + wire width 1 input 320 \rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 8 \core_d_rd1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 64 \core_d_rd1__data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:75" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:546" + wire width 1 \core_valid + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:74" wire width 1 \core_issue_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 8 \core_fast_nia_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:76" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:75" wire width 1 \core_corebusy_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" wire width 8 \core_wen @@ -135846,7 +145768,7 @@ module \test_issuer connect \st__rel \st__rel connect \d_rd1__ren \core_d_rd1__ren connect \d_rd1__data_o \core_d_rd1__data_o - connect \valid \valid + connect \valid \core_valid connect \issue_i \core_issue_i connect \bigendian \bigendian connect \raw_opcode_in \raw_opcode_in @@ -135862,7 +145784,7 @@ module \test_issuer connect \imm \imm connect \imm_ok \imm_ok connect \oper_i__lk \oper_i__lk - connect \lk \lk$105 + connect \lk \lk$120 connect \rc \rc connect \rc_ok \rc_ok connect \oe \oe @@ -135872,7 +145794,7 @@ module \test_issuer connect \zero_a \zero_a connect \oper_i__invert_out \oper_i__invert_out connect \invert_out \invert_out - connect \cr_out \cr_out$104 + connect \cr_out \cr_out$119 connect \cr_out_ok \cr_out_ok connect \oper_i__input_carry \oper_i__input_carry connect \input_carry \input_carry @@ -135908,7 +145830,7 @@ module \test_issuer connect \busy_o$4 \busy_o$9 connect \cr_in1_ok \cr_in1_ok connect \cr_in2_ok \cr_in2_ok - connect \cr_in2_ok$5 \cr_in2_ok$103 + connect \cr_in2_ok$5 \cr_in2_ok$118 connect \oper_i__insn_type$6 \oper_i__insn_type$18 connect \oper_i__fn_unit$7 \oper_i__fn_unit$19 connect \oper_i__lk$8 \oper_i__lk$20 @@ -135941,85 +145863,100 @@ module \test_issuer connect \issue_i$29 \issue_i$46 connect \busy_o$30 \busy_o$61 connect \oper_i__insn_type$31 \oper_i__insn_type$70 - connect \oper_i__input_carry$32 \oper_i__input_carry$71 - connect \oper_i__output_carry$33 \oper_i__output_carry$72 - connect \oper_i__input_cr$34 \oper_i__input_cr$73 - connect \oper_i__output_cr$35 \oper_i__output_cr$74 - connect \oper_i__is_32bit$36 \oper_i__is_32bit$75 - connect \oper_i__is_signed$37 \oper_i__is_signed$76 - connect \issue_i$38 \issue_i$67 - connect \busy_o$39 \busy_o$79 + connect \oper_i__fn_unit$32 \oper_i__fn_unit$72 + connect \oper_i__insn$33 \oper_i__insn$71 + connect \oper_i__is_32bit$34 \oper_i__is_32bit$73 + connect \issue_i$35 \issue_i$67 + connect \busy_o$36 \busy_o$76 + connect \spr1_ok \spr1_ok + connect \oper_i__insn_type$37 \oper_i__insn_type$85 + connect \oper_i__input_carry$38 \oper_i__input_carry$86 + connect \oper_i__output_carry$39 \oper_i__output_carry$87 + connect \oper_i__input_cr$40 \oper_i__input_cr$88 + connect \oper_i__output_cr$41 \oper_i__output_cr$89 + connect \oper_i__is_32bit$42 \oper_i__is_32bit$90 + connect \oper_i__is_signed$43 \oper_i__is_signed$91 + connect \issue_i$44 \issue_i$82 + connect \busy_o$45 \busy_o$94 connect \reg3_ok \reg3_ok - connect \oper_i__insn_type$40 \oper_i__insn_type$88 + connect \oper_i__insn_type$46 \oper_i__insn_type$103 connect \oper_i__zero_a \oper_i__zero_a - connect \oper_i__is_32bit$41 \oper_i__is_32bit$89 - connect \oper_i__is_signed$42 \oper_i__is_signed$90 - connect \oper_i__data_len$43 \oper_i__data_len$91 - connect \oper_i__byte_reverse$44 \oper_i__byte_reverse$92 - connect \oper_i__sign_extend$45 \oper_i__sign_extend$93 + connect \oper_i__is_32bit$47 \oper_i__is_32bit$104 + connect \oper_i__is_signed$48 \oper_i__is_signed$105 + connect \oper_i__data_len$49 \oper_i__data_len$106 + connect \oper_i__byte_reverse$50 \oper_i__byte_reverse$107 + connect \oper_i__sign_extend$51 \oper_i__sign_extend$108 connect \oper_i__update \oper_i__update connect \update \update - connect \issue_i$46 \issue_i$85 - connect \busy_o$47 \busy_o$96 + connect \issue_i$52 \issue_i$100 + connect \busy_o$53 \busy_o$111 connect \reg1 \reg1 connect \rd__rel \rd__rel connect \rd__go \rd__go connect \src1_i \src1_i - connect \rd__rel$48 \rd__rel$10 - connect \rd__go$49 \rd__go$1 - connect \src1_i$50 \src1_i$7 - connect \rd__rel$51 \rd__rel$41 - connect \rd__go$52 \rd__go$29 - connect \src1_i$53 \src1_i$38 - connect \rd__rel$54 \rd__rel$62 - connect \rd__go$55 \rd__go$44 - connect \src1_i$56 \src1_i$59 - connect \rd__rel$57 \rd__rel$80 - connect \rd__go$58 \rd__go$65 - connect \src1_i$59 \src1_i$77 - connect \rd__rel$60 \rd__rel$97 - connect \rd__go$61 \rd__go$83 - connect \src1_i$62 \src1_i$94 + connect \rd__rel$54 \rd__rel$10 + connect \rd__go$55 \rd__go$1 + connect \src1_i$56 \src1_i$7 + connect \rd__rel$57 \rd__rel$41 + connect \rd__go$58 \rd__go$29 + connect \src1_i$59 \src1_i$38 + connect \rd__rel$60 \rd__rel$62 + connect \rd__go$61 \rd__go$44 + connect \src1_i$62 \src1_i$59 + connect \rd__rel$63 \rd__rel$77 + connect \rd__go$64 \rd__go$65 + connect \src1_i$65 \src1_i$74 + connect \rd__rel$66 \rd__rel$95 + connect \rd__go$67 \rd__go$80 + connect \src1_i$68 \src1_i$92 + connect \rd__rel$69 \rd__rel$112 + connect \rd__go$70 \rd__go$98 + connect \src1_i$71 \src1_i$109 connect \reg2 \reg2 connect \src2_i \src2_i - connect \src2_i$63 \src2_i$8 - connect \src2_i$64 \src2_i$39 - connect \src2_i$65 \src2_i$60 - connect \src2_i$66 \src2_i$78 - connect \src2_i$67 \src2_i$95 + connect \src2_i$72 \src2_i$8 + connect \src2_i$73 \src2_i$39 + connect \src2_i$74 \src2_i$60 + connect \src2_i$75 \src2_i$93 + connect \src2_i$76 \src2_i$110 connect \reg3 \reg3 connect \src3_i \src3_i connect \cr_in1 \cr_in1 - connect \rd__rel$68 \rd__rel$26 - connect \rd__go$69 \rd__go$13 + connect \rd__rel$77 \rd__rel$26 + connect \rd__go$78 \rd__go$13 connect \cr_in2 \cr_in2 - connect \cr_in2$70 \cr_in2$102 + connect \cr_in2$79 \cr_in2$117 connect \fast1 \fast1 - connect \src1_i$71 \src1_i$23 + connect \src1_i$80 \src1_i$23 connect \fast2 \fast2 - connect \src2_i$72 \src2_i$24 + connect \src2_i$81 \src2_i$24 + connect \spr1 \spr1 + connect \src2_i$82 \src2_i$75 connect \rego \rego connect \wr__rel \wr__rel connect \wr__go \wr__go - connect \wr__rel$73 \wr__rel$11 - connect \wr__go$74 \wr__go$2 - connect \wr__rel$75 \wr__rel$42 - connect \wr__go$76 \wr__go$30 - connect \wr__rel$77 \wr__rel$63 - connect \wr__go$78 \wr__go$45 - connect \wr__rel$79 \wr__rel$81 - connect \wr__go$80 \wr__go$66 + connect \wr__rel$83 \wr__rel$11 + connect \wr__go$84 \wr__go$2 + connect \wr__rel$85 \wr__rel$42 + connect \wr__go$86 \wr__go$30 + connect \wr__rel$87 \wr__rel$63 + connect \wr__go$88 \wr__go$45 + connect \wr__rel$89 \wr__rel$78 + connect \wr__go$90 \wr__go$66 + connect \wr__rel$91 \wr__rel$96 + connect \wr__go$92 \wr__go$81 connect \o_ok \o_ok - connect \wr__rel$81 \wr__rel$98 - connect \wr__go$82 \wr__go$84 + connect \wr__rel$93 \wr__rel$113 + connect \wr__go$94 \wr__go$99 connect \o \o - connect \ea \ea$100 + connect \ea \ea$115 connect \ea_ok \ea_ok - connect \ea$83 \ea + connect \ea$95 \ea connect \fasto1 \fasto1 - connect \wr__rel$84 \wr__rel$27 - connect \wr__go$85 \wr__go$14 + connect \wr__rel$96 \wr__rel$27 + connect \wr__go$97 \wr__go$14 connect \fasto2 \fasto2 + connect \spro \spro connect \opcode_in \opcode_in connect \in1_sel \in1_sel connect \in2_sel \in2_sel @@ -136027,15 +145964,12 @@ module \test_issuer connect \out_sel \out_sel connect \rc_sel \rc_sel connect \cr_in \cr_in - connect \cr_out$86 \cr_out + connect \cr_out$98 \cr_out connect \nia \nia connect \function_unit \function_unit connect \internal_op \internal_op connect \rego_ok \rego_ok - connect \ea_ok$87 \ea_ok$101 - connect \spr1 \spr1 - connect \spr1_ok \spr1_ok - connect \spro \spro + connect \ea_ok$99 \ea_ok$116 connect \spro_ok \spro_ok connect \fasto1_ok \fasto1_ok connect \fasto2_ok \fasto2_ok @@ -136045,71 +145979,75 @@ module \test_issuer connect \cry_out \cry_out connect \is_32b \is_32b connect \sgn \sgn - connect \lk$88 \lk + connect \lk$100 \lk connect \br \br connect \sgn_ext \sgn_ext connect \upd \upd + connect \asmcode \asmcode$114 connect \form \form connect \rsrv \rsrv connect \sgl_pipe \sgl_pipe - connect \asmcode \asmcode + connect \asmcode$101 \asmcode connect \go_die_i \go_die_i connect \shadown_i \shadown_i connect \dest1_o \dest1_o - connect \go_die_i$89 \go_die_i$5 - connect \shadown_i$90 \shadown_i$4 - connect \dest1_o$91 \dest1_o$12 - connect \go_die_i$92 \go_die_i$17 - connect \shadown_i$93 \shadown_i$16 - connect \dest1_o$94 \dest1_o$28 - connect \go_die_i$95 \go_die_i$33 - connect \shadown_i$96 \shadown_i$32 - connect \dest1_o$97 \dest1_o$43 - connect \go_die_i$98 \go_die_i$48 - connect \shadown_i$99 \shadown_i$47 - connect \dest1_o$100 \dest1_o$64 - connect \go_die_i$101 \go_die_i$69 - connect \shadown_i$102 \shadown_i$68 - connect \dest1_o$103 \dest1_o$82 - connect \go_die_i$104 \go_die_i$87 + connect \go_die_i$102 \go_die_i$5 + connect \shadown_i$103 \shadown_i$4 + connect \dest1_o$104 \dest1_o$12 + connect \go_die_i$105 \go_die_i$17 + connect \shadown_i$106 \shadown_i$16 + connect \dest1_o$107 \dest1_o$28 + connect \go_die_i$108 \go_die_i$33 + connect \shadown_i$109 \shadown_i$32 + connect \dest1_o$110 \dest1_o$43 + connect \go_die_i$111 \go_die_i$48 + connect \shadown_i$112 \shadown_i$47 + connect \dest1_o$113 \dest1_o$64 + connect \go_die_i$114 \go_die_i$69 + connect \shadown_i$115 \shadown_i$68 + connect \dest1_o$116 \dest1_o$79 + connect \go_die_i$117 \go_die_i$84 + connect \shadown_i$118 \shadown_i$83 + connect \dest1_o$119 \dest1_o$97 + connect \go_die_i$120 \go_die_i$102 connect \load_mem_o \load_mem_o connect \stwd_mem_o \stwd_mem_o - connect \shadown_i$105 \shadown_i$86 - connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i$106 - connect \ldst_port0_is_st_i \ldst_port0_is_st_i$107 - connect \ldst_port0_data_len \ldst_port0_data_len$108 - connect \ldst_port0_addr_i \ldst_port0_addr_i$111 - connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$112 - connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$114 - connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$113 - connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o$115 - connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok$116 - connect \ldst_port0_st_data_i \ldst_port0_st_data_i$117 - connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok$118 - connect \ldst_port0_is_ld_i$106 \ldst_port0_is_ld_i + connect \shadown_i$121 \shadown_i$101 + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i$121 + connect \ldst_port0_is_st_i \ldst_port0_is_st_i$122 + connect \ldst_port0_data_len \ldst_port0_data_len$123 + connect \ldst_port0_addr_i \ldst_port0_addr_i$126 + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$127 + connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$129 + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$128 + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o$130 + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok$131 + connect \ldst_port0_st_data_i \ldst_port0_st_data_i$132 + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok$133 + connect \ldst_port0_is_ld_i$122 \ldst_port0_is_ld_i connect \ldst_port0_busy_o \ldst_port0_busy_o - connect \ldst_port0_is_st_i$107 \ldst_port0_is_st_i - connect \ldst_port0_data_len$108 \ldst_port0_data_len - connect \ldst_port0_addr_i$109 \ldst_port0_addr_i - connect \ldst_port0_addr_i_ok$110 \ldst_port0_addr_i_ok + connect \ldst_port0_is_st_i$123 \ldst_port0_is_st_i + connect \ldst_port0_data_len$124 \ldst_port0_data_len + connect \ldst_port0_addr_i$125 \ldst_port0_addr_i + connect \ldst_port0_addr_i_ok$126 \ldst_port0_addr_i_ok connect \x_mask_i \x_mask_i connect \x_addr_i \x_addr_i - connect \ldst_port0_addr_ok_o$111 \ldst_port0_addr_ok_o + connect \ldst_port0_addr_ok_o$127 \ldst_port0_addr_ok_o connect \m_ld_data_o \m_ld_data_o - connect \ldst_port0_ld_data_o$112 \ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok$113 \ldst_port0_ld_data_o_ok + connect \ldst_port0_ld_data_o$128 \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok$129 \ldst_port0_ld_data_o_ok connect \x_busy_o \x_busy_o - connect \ldst_port0_st_data_i_ok$114 \ldst_port0_st_data_i_ok - connect \ldst_port0_st_data_i$115 \ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok$130 \ldst_port0_st_data_i_ok + connect \ldst_port0_st_data_i$131 \ldst_port0_st_data_i connect \x_st_data_i \x_st_data_i - connect \ldst_port0_addr_exc_o$116 \ldst_port0_addr_exc_o + connect \ldst_port0_addr_exc_o$132 \ldst_port0_addr_exc_o connect \x_ld_i \x_ld_i connect \x_st_i \x_st_i connect \m_valid_i \m_valid_i connect \x_valid_i \x_valid_i connect \ldst_port0_go_die_i \ldst_port0_go_die_i - connect \ldst_port0_go_die_i$117 \ldst_port0_go_die_i$110 - connect \ldst_port0_busy_o$118 \ldst_port0_busy_o$109 + connect \ldst_port0_go_die_i$133 \ldst_port0_go_die_i$125 + connect \ldst_port0_busy_o$134 \ldst_port0_busy_o$124 connect \dbus__cyc \dbus__cyc connect \x_stall_i \x_stall_i connect \dbus__ack \dbus__ack @@ -136166,13 +146104,13 @@ module \test_issuer sync init end attribute \src "simple/issuer.py:79" - wire width 64 \nia$119 + wire width 64 \nia$134 attribute \src "simple/issuer.py:80" - wire width 65 $120 + wire width 65 $135 attribute \src "simple/issuer.py:80" - wire width 65 $121 + wire width 65 $136 attribute \src "simple/issuer.py:80" - cell $add $122 + cell $add $137 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -136180,12 +146118,12 @@ module \test_issuer parameter \Y_WIDTH 65 connect \A \current_pc connect \B 3'100 - connect \Y $121 + connect \Y $136 end - connect $120 $121 + connect $135 $136 process $group_3 - assign \nia$119 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia$119 $120 [63:0] + assign \nia$134 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \nia$134 $135 [63:0] sync init end attribute \src "simple/issuer.py:74" @@ -136197,14 +146135,14 @@ module \test_issuer attribute \src "simple/issuer.py:90" wire width 2 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - wire width 1 $123 + wire width 1 $138 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439" - cell $reduce_bool $124 + cell $reduce_bool $139 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \core_fast_nia_wen - connect \Y $123 + connect \Y $138 end process $group_4 assign \pc_changed$next \pc_changed @@ -136221,7 +146159,7 @@ module \test_issuer attribute \nmigen.decoding "INSN_ACTIVE/2" case 2'10 attribute \src "simple/issuer.py:136" - switch { $123 } + switch { $138 } attribute \src "simple/issuer.py:136" case 1'1 assign \pc_changed$next 1'1 @@ -136238,9 +146176,9 @@ module \test_issuer update \pc_changed \pc_changed$next end attribute \src "simple/issuer.py:97" - wire width 64 \pc$125 + wire width 64 \pc$140 process $group_5 - assign \pc$125 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pc$140 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "simple/issuer.py:90" switch \fsm_state attribute \src "simple/issuer.py:93" @@ -136254,10 +146192,10 @@ module \test_issuer switch { \pc_ok } attribute \src "simple/issuer.py:98" case 1'1 - assign \pc$125 \pc + assign \pc$140 \pc attribute \src "simple/issuer.py:101" case - assign \pc$125 \core_d_rd1__data_o + assign \pc$140 \core_d_rd1__data_o end end attribute \src "simple/issuer.py:115" @@ -136309,7 +146247,7 @@ module \test_issuer switch { \go_insn_i } attribute \src "simple/issuer.py:95" case 1'1 - assign \a_pc_i \pc$125 [47:0] + assign \a_pc_i \pc$140 [47:0] end attribute \src "simple/issuer.py:115" attribute \nmigen.decoding "INSN_READ/1" @@ -136391,7 +146329,7 @@ module \test_issuer switch { \go_insn_i } attribute \src "simple/issuer.py:95" case 1'1 - assign \current_pc$next \pc$125 + assign \current_pc$next \pc$140 end attribute \src "simple/issuer.py:115" attribute \nmigen.decoding "INSN_READ/1" @@ -136411,14 +146349,14 @@ module \test_issuer update \current_pc \current_pc$next end attribute \src "simple/issuer.py:138" - wire width 1 $126 + wire width 1 $141 attribute \src "simple/issuer.py:138" - cell $not $127 + cell $not $142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $126 + connect \Y $141 end process $group_11 assign \fsm_state$next \fsm_state @@ -136448,7 +146386,7 @@ module \test_issuer attribute \nmigen.decoding "INSN_ACTIVE/2" case 2'10 attribute \src "simple/issuer.py:138" - switch { $126 } + switch { $141 } attribute \src "simple/issuer.py:138" case 1'1 assign \fsm_state$next 2'00 @@ -136467,11 +146405,11 @@ module \test_issuer attribute \src "simple/issuer.py:72" wire width 32 \current_insn attribute \src "simple/issuer.py:122" - wire width 32 $128 + wire width 32 $143 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 $129 + wire width 7 $144 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $130 + cell $mul $145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -136479,18 +146417,18 @@ module \test_issuer parameter \Y_WIDTH 7 connect \A \current_pc [2] connect \B 6'100000 - connect \Y $129 + connect \Y $144 end attribute \src "simple/issuer.py:122" - cell $shift $131 + cell $shift $146 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 7 parameter \Y_WIDTH 32 connect \A \f_instr_o - connect \B $129 - connect \Y $128 + connect \B $144 + connect \Y $143 end process $group_12 assign \current_insn 32'00000000000000000000000000000000 @@ -136508,7 +146446,7 @@ module \test_issuer case 1'1 attribute \src "simple/issuer.py:120" case - assign \current_insn $128 + assign \current_insn $143 end attribute \src "simple/issuer.py:132" attribute \nmigen.decoding "INSN_ACTIVE/2" @@ -136517,7 +146455,7 @@ module \test_issuer sync init end process $group_13 - assign \valid 1'0 + assign \core_valid 1'0 attribute \src "simple/issuer.py:90" switch \fsm_state attribute \src "simple/issuer.py:93" @@ -136532,12 +146470,12 @@ module \test_issuer case 1'1 attribute \src "simple/issuer.py:120" case - assign \valid 1'1 + assign \core_valid 1'1 end attribute \src "simple/issuer.py:132" attribute \nmigen.decoding "INSN_ACTIVE/2" case 2'10 - assign \valid 1'1 + assign \core_valid 1'1 end sync init end @@ -136651,24 +146589,24 @@ module \test_issuer update \ilatch \ilatch$next end attribute \src "simple/issuer.py:138" - wire width 1 $132 + wire width 1 $147 attribute \src "simple/issuer.py:138" - cell $not $133 + cell $not $148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $132 + connect \Y $147 end attribute \src "simple/issuer.py:144" - wire width 1 $134 + wire width 1 $149 attribute \src "simple/issuer.py:144" - cell $not $135 + cell $not $150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_changed - connect \Y $134 + connect \Y $149 end process $group_18 assign \core_wen 8'00000000 @@ -136684,11 +146622,11 @@ module \test_issuer attribute \nmigen.decoding "INSN_ACTIVE/2" case 2'10 attribute \src "simple/issuer.py:138" - switch { $132 } + switch { $147 } attribute \src "simple/issuer.py:138" case 1'1 attribute \src "simple/issuer.py:144" - switch { $134 } + switch { $149 } attribute \src "simple/issuer.py:144" case 1'1 assign \core_wen 8'00000001 @@ -136698,24 +146636,24 @@ module \test_issuer sync init end attribute \src "simple/issuer.py:138" - wire width 1 $136 + wire width 1 $151 attribute \src "simple/issuer.py:138" - cell $not $137 + cell $not $152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $136 + connect \Y $151 end attribute \src "simple/issuer.py:144" - wire width 1 $138 + wire width 1 $153 attribute \src "simple/issuer.py:144" - cell $not $139 + cell $not $154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_changed - connect \Y $138 + connect \Y $153 end process $group_19 assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -136731,14 +146669,14 @@ module \test_issuer attribute \nmigen.decoding "INSN_ACTIVE/2" case 2'10 attribute \src "simple/issuer.py:138" - switch { $136 } + switch { $151 } attribute \src "simple/issuer.py:138" case 1'1 attribute \src "simple/issuer.py:144" - switch { $138 } + switch { $153 } attribute \src "simple/issuer.py:144" case 1'1 - assign \core_data_i \nia$119 + assign \core_data_i \nia$134 end end end