From: whitequark <whitequark@whitequark.org>
Date: Tue, 9 Jun 2020 09:56:23 +0000 (+0000)
Subject: flatten: accept processes.
X-Git-Tag: working-ls180~486^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=98e108034561bb3a9276594ebef2f80da38748ad;p=yosys.git

flatten: accept processes.
---

diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc
index a2794541a..a03226f9f 100644
--- a/passes/techmap/flatten.cc
+++ b/passes/techmap/flatten.cc
@@ -79,14 +79,6 @@ struct FlattenWorker
 
 	void flatten_cell(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, std::vector<RTLIL::Cell*> &new_cells)
 	{
-		if (tpl->processes.size() != 0) {
-			log("Flattening yielded processes:");
-			for (auto &it : tpl->processes)
-				log(" %s",log_id(it.first));
-			log("\n");
-			log_error("Flattening yielded processes -> this is not supported.\n");
-		}
-
 		// Copy the contents of the flattened cell
 
 		dict<IdString, IdString> memory_map;
@@ -127,6 +119,14 @@ struct FlattenWorker
 			design->select(module, new_wire);
 		}
 
+		for (auto &tpl_proc_it : tpl->processes) {
+			RTLIL::Process *new_proc = module->addProcess(map_name(cell, tpl_proc_it.second), tpl_proc_it.second);
+			map_attributes(cell, new_proc, tpl_proc_it.second->name);
+			auto rewriter = [&](RTLIL::SigSpec &sig) { map_sigspec(wire_map, sig); };
+			new_proc->rewrite_sigspecs(rewriter);
+			design->select(module, new_proc);
+		}
+
 		for (auto tpl_cell : tpl->cells()) {
 			RTLIL::Cell *new_cell = module->addCell(map_name(cell, tpl_cell), tpl_cell);
 			map_attributes(cell, new_cell, tpl_cell->name);