From: Sebastien Bourdeauducq Date: Tue, 6 Mar 2012 18:43:59 +0000 (+0100) Subject: sim: make initialization cycle optional (selectable by function attribute) X-Git-Tag: 24jan2021_ls180~2099^2~987 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=98e96b39522d92588cbfa8f5c48fa69df845f352;p=litex.git sim: make initialization cycle optional (selectable by function attribute) --- diff --git a/examples/basic_sim.py b/examples/basic_sim.py index a4f17c46..035440ca 100644 --- a/examples/basic_sim.py +++ b/examples/basic_sim.py @@ -13,6 +13,7 @@ class Counter: else: s.wr(self.ce, 1) print("Cycle: " + str(s.cycle_counter) + " Count: " + str(s.rd(self.count))) + do_simulation.initialize = True def get_fragment(self): sync = [If(self.ce, self.count.eq(self.count + 1))] diff --git a/examples/memory_sim.py b/examples/memory_sim.py index 7c58b2bb..dae39257 100644 --- a/examples/memory_sim.py +++ b/examples/memory_sim.py @@ -10,11 +10,10 @@ class Mem: self.mem = Memory(16, 2**12, p, init=list(range(20))) def do_simulation(self, s): - if s.cycle_counter >= 0: - value = s.rd(self.mem, s.cycle_counter) - print(value) - if value == 10: - s.interrupt = True + value = s.rd(self.mem, s.cycle_counter) + print(value) + if value == 10: + s.interrupt = True def get_fragment(self): return Fragment(memories=[self.mem], sim=[self.do_simulation]) diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py index e5730ff5..69f53f65 100644 --- a/migen/fhdl/structure.py +++ b/migen/fhdl/structure.py @@ -278,4 +278,5 @@ class Fragment: def call_sim(self, simulator): for s in self.sim: - s(simulator) + if simulator.cycle_counter >= 0 or (hasattr(s, "initialize") and s.initialize): + s(simulator)