From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 18 Aug 2019 05:25:32 +0000 (+0100)
Subject: add TODO code, needs sorting
X-Git-Tag: ls180-24jan2020~487
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=98ff5a04b780929acc0e67bbef5e862000efaf62;p=ieee754fpu.git

add TODO code, needs sorting
---

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index 0deb321c..ba689266 100644
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -386,6 +386,7 @@ class ProductTerm(Elaboratable):
         self.b_index = b_index
         shift = 8 * (self.a_index + self.b_index)
         self.pwidth = width
+        self.twidth = twidth
         self.width = width*2
         self.shift = shift
 
@@ -422,6 +423,24 @@ class ProductTerm(Elaboratable):
         m.d.comb += bsb.eq(self.b.bit_select(b_index * pwidth, pwidth))
         m.d.comb += self.ti.eq(bsa * bsb)
         m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled))
+        """
+        #TODO: sort out width issues, get inputs a/b switched on/off.
+        #data going into Muxes is 1/2 the required width
+
+        pwidth = self.pwidth
+        width = self.width
+        bsa = Signal(self.twidth//2, reset_less=True)
+        bsb = Signal(self.twidth//2, reset_less=True)
+        asel = Signal(width, reset_less=True)
+        bsel = Signal(width, reset_less=True)
+        a_index, b_index = self.a_index, self.b_index
+        m.d.comb += asel.eq(self.a.bit_select(a_index * pwidth, pwidth))
+        m.d.comb += bsel.eq(self.b.bit_select(b_index * pwidth, pwidth))
+        m.d.comb += bsa.eq(get_term(asel, self.shift, self.enabled))
+        m.d.comb += bsb.eq(get_term(bsel, self.shift, self.enabled))
+        m.d.comb += self.ti.eq(bsa * bsb)
+        m.d.comb += self.term.eq(self.ti)
+        """
 
         return m